1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999 4 * Author(s): Hartmut Penner (hp@de.ibm.com), 5 * Martin Schwidefsky (schwidefsky@de.ibm.com) 6 * 7 * Derived from "include/asm-i386/processor.h" 8 * Copyright (C) 1994, Linus Torvalds 9 */ 10 11 #ifndef __ASM_S390_PROCESSOR_H 12 #define __ASM_S390_PROCESSOR_H 13 14 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ 15 #define CIF_ASCE 1 /* user asce needs fixup / uaccess */ 16 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 17 18 #define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING) 19 #define _CIF_ASCE (1<<CIF_ASCE) 20 #define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY) 21 22 23 #ifndef __ASSEMBLY__ 24 25 #include <linux/linkage.h> 26 #include <linux/irqflags.h> 27 #include <asm/cpu.h> 28 #include <asm/page.h> 29 #include <asm/ptrace.h> 30 #include <asm/setup.h> 31 #include <asm/runtime_instr.h> 32 33 static inline void set_cpu_flag(int flag) 34 { 35 S390_lowcore.cpu_flags |= (1U << flag); 36 } 37 38 static inline void clear_cpu_flag(int flag) 39 { 40 S390_lowcore.cpu_flags &= ~(1U << flag); 41 } 42 43 static inline int test_cpu_flag(int flag) 44 { 45 return !!(S390_lowcore.cpu_flags & (1U << flag)); 46 } 47 48 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 49 50 /* 51 * Default implementation of macro that returns current 52 * instruction pointer ("program counter"). 53 */ 54 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 55 56 static inline void get_cpu_id(struct cpuid *ptr) 57 { 58 asm volatile("stidp %0" : "=Q" (*ptr)); 59 } 60 61 extern void s390_adjust_jiffies(void); 62 extern const struct seq_operations cpuinfo_op; 63 extern int sysctl_ieee_emulation_warnings; 64 extern void execve_tail(void); 65 66 /* 67 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 68 */ 69 #ifndef CONFIG_64BIT 70 71 #define TASK_SIZE (1UL << 31) 72 #define TASK_MAX_SIZE (1UL << 31) 73 #define TASK_UNMAPPED_BASE (1UL << 30) 74 75 #else /* CONFIG_64BIT */ 76 77 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) 78 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 79 (1UL << 30) : (1UL << 41)) 80 #define TASK_SIZE TASK_SIZE_OF(current) 81 #define TASK_MAX_SIZE (1UL << 53) 82 83 #endif /* CONFIG_64BIT */ 84 85 #ifndef CONFIG_64BIT 86 #define STACK_TOP (1UL << 31) 87 #define STACK_TOP_MAX (1UL << 31) 88 #else /* CONFIG_64BIT */ 89 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) 90 #define STACK_TOP_MAX (1UL << 42) 91 #endif /* CONFIG_64BIT */ 92 93 #define HAVE_ARCH_PICK_MMAP_LAYOUT 94 95 typedef struct { 96 __u32 ar4; 97 } mm_segment_t; 98 99 /* 100 * Thread structure 101 */ 102 struct thread_struct { 103 s390_fp_regs fp_regs; 104 unsigned int acrs[NUM_ACRS]; 105 unsigned long ksp; /* kernel stack pointer */ 106 mm_segment_t mm_segment; 107 unsigned long gmap_addr; /* address of last gmap fault. */ 108 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 109 struct per_regs per_user; /* User specified PER registers */ 110 struct per_event per_event; /* Cause of the last PER trap */ 111 unsigned long per_flags; /* Flags to control debug behavior */ 112 /* pfault_wait is used to block the process on a pfault event */ 113 unsigned long pfault_wait; 114 struct list_head list; 115 /* cpu runtime instrumentation */ 116 struct runtime_instr_cb *ri_cb; 117 int ri_signum; 118 #ifdef CONFIG_64BIT 119 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 120 __vector128 *vxrs; /* Vector register save area */ 121 #endif 122 }; 123 124 /* Flag to disable transactions. */ 125 #define PER_FLAG_NO_TE 1UL 126 /* Flag to enable random transaction aborts. */ 127 #define PER_FLAG_TE_ABORT_RAND 2UL 128 /* Flag to specify random transaction abort mode: 129 * - abort each transaction at a random instruction before TEND if set. 130 * - abort random transactions at a random instruction if cleared. 131 */ 132 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 133 134 typedef struct thread_struct thread_struct; 135 136 /* 137 * Stack layout of a C stack frame. 138 */ 139 #ifndef __PACK_STACK 140 struct stack_frame { 141 unsigned long back_chain; 142 unsigned long empty1[5]; 143 unsigned long gprs[10]; 144 unsigned int empty2[8]; 145 }; 146 #else 147 struct stack_frame { 148 unsigned long empty1[5]; 149 unsigned int empty2[8]; 150 unsigned long gprs[10]; 151 unsigned long back_chain; 152 }; 153 #endif 154 155 #define ARCH_MIN_TASKALIGN 8 156 157 #define INIT_THREAD { \ 158 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 159 } 160 161 /* 162 * Do necessary setup to start up a new thread. 163 */ 164 #define start_thread(regs, new_psw, new_stackp) do { \ 165 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 166 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 167 regs->gprs[15] = new_stackp; \ 168 execve_tail(); \ 169 } while (0) 170 171 #define start_thread31(regs, new_psw, new_stackp) do { \ 172 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 173 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 174 regs->gprs[15] = new_stackp; \ 175 crst_table_downgrade(current->mm, 1UL << 31); \ 176 execve_tail(); \ 177 } while (0) 178 179 /* Forward declaration, a strange C thing */ 180 struct task_struct; 181 struct mm_struct; 182 struct seq_file; 183 184 #ifdef CONFIG_64BIT 185 extern void show_cacheinfo(struct seq_file *m); 186 #else 187 static inline void show_cacheinfo(struct seq_file *m) { } 188 #endif 189 190 /* Free all resources held by a thread. */ 191 extern void release_thread(struct task_struct *); 192 193 /* 194 * Return saved PC of a blocked thread. 195 */ 196 extern unsigned long thread_saved_pc(struct task_struct *t); 197 198 unsigned long get_wchan(struct task_struct *p); 199 #define task_pt_regs(tsk) ((struct pt_regs *) \ 200 (task_stack_page(tsk) + THREAD_SIZE) - 1) 201 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 202 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 203 204 /* Has task runtime instrumentation enabled ? */ 205 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 206 207 static inline unsigned short stap(void) 208 { 209 unsigned short cpu_address; 210 211 asm volatile("stap %0" : "=m" (cpu_address)); 212 return cpu_address; 213 } 214 215 /* 216 * Give up the time slice of the virtual PU. 217 */ 218 void cpu_relax(void); 219 220 #define cpu_relax_lowlatency() barrier() 221 222 static inline void psw_set_key(unsigned int key) 223 { 224 asm volatile("spka 0(%0)" : : "d" (key)); 225 } 226 227 /* 228 * Set PSW to specified value. 229 */ 230 static inline void __load_psw(psw_t psw) 231 { 232 #ifndef CONFIG_64BIT 233 asm volatile("lpsw %0" : : "Q" (psw) : "cc"); 234 #else 235 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 236 #endif 237 } 238 239 /* 240 * Set PSW mask to specified value, while leaving the 241 * PSW addr pointing to the next instruction. 242 */ 243 static inline void __load_psw_mask (unsigned long mask) 244 { 245 unsigned long addr; 246 psw_t psw; 247 248 psw.mask = mask; 249 250 #ifndef CONFIG_64BIT 251 asm volatile( 252 " basr %0,0\n" 253 "0: ahi %0,1f-0b\n" 254 " st %0,%O1+4(%R1)\n" 255 " lpsw %1\n" 256 "1:" 257 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 258 #else /* CONFIG_64BIT */ 259 asm volatile( 260 " larl %0,1f\n" 261 " stg %0,%O1+8(%R1)\n" 262 " lpswe %1\n" 263 "1:" 264 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 265 #endif /* CONFIG_64BIT */ 266 } 267 268 /* 269 * Rewind PSW instruction address by specified number of bytes. 270 */ 271 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 272 { 273 #ifndef CONFIG_64BIT 274 if (psw.addr & PSW_ADDR_AMODE) 275 /* 31 bit mode */ 276 return (psw.addr - ilc) | PSW_ADDR_AMODE; 277 /* 24 bit mode */ 278 return (psw.addr - ilc) & ((1UL << 24) - 1); 279 #else 280 unsigned long mask; 281 282 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 283 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 284 (1UL << 24) - 1; 285 return (psw.addr - ilc) & mask; 286 #endif 287 } 288 289 /* 290 * Function to stop a processor until the next interrupt occurs 291 */ 292 void enabled_wait(void); 293 294 /* 295 * Function to drop a processor into disabled wait state 296 */ 297 static inline void __noreturn disabled_wait(unsigned long code) 298 { 299 unsigned long ctl_buf; 300 psw_t dw_psw; 301 302 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 303 dw_psw.addr = code; 304 /* 305 * Store status and then load disabled wait psw, 306 * the processor is dead afterwards 307 */ 308 #ifndef CONFIG_64BIT 309 asm volatile( 310 " stctl 0,0,0(%2)\n" 311 " ni 0(%2),0xef\n" /* switch off protection */ 312 " lctl 0,0,0(%2)\n" 313 " stpt 0xd8\n" /* store timer */ 314 " stckc 0xe0\n" /* store clock comparator */ 315 " stpx 0x108\n" /* store prefix register */ 316 " stam 0,15,0x120\n" /* store access registers */ 317 " std 0,0x160\n" /* store f0 */ 318 " std 2,0x168\n" /* store f2 */ 319 " std 4,0x170\n" /* store f4 */ 320 " std 6,0x178\n" /* store f6 */ 321 " stm 0,15,0x180\n" /* store general registers */ 322 " stctl 0,15,0x1c0\n" /* store control registers */ 323 " oi 0x1c0,0x10\n" /* fake protection bit */ 324 " lpsw 0(%1)" 325 : "=m" (ctl_buf) 326 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); 327 #else /* CONFIG_64BIT */ 328 asm volatile( 329 " stctg 0,0,0(%2)\n" 330 " ni 4(%2),0xef\n" /* switch off protection */ 331 " lctlg 0,0,0(%2)\n" 332 " lghi 1,0x1000\n" 333 " stpt 0x328(1)\n" /* store timer */ 334 " stckc 0x330(1)\n" /* store clock comparator */ 335 " stpx 0x318(1)\n" /* store prefix register */ 336 " stam 0,15,0x340(1)\n"/* store access registers */ 337 " stfpc 0x31c(1)\n" /* store fpu control */ 338 " std 0,0x200(1)\n" /* store f0 */ 339 " std 1,0x208(1)\n" /* store f1 */ 340 " std 2,0x210(1)\n" /* store f2 */ 341 " std 3,0x218(1)\n" /* store f3 */ 342 " std 4,0x220(1)\n" /* store f4 */ 343 " std 5,0x228(1)\n" /* store f5 */ 344 " std 6,0x230(1)\n" /* store f6 */ 345 " std 7,0x238(1)\n" /* store f7 */ 346 " std 8,0x240(1)\n" /* store f8 */ 347 " std 9,0x248(1)\n" /* store f9 */ 348 " std 10,0x250(1)\n" /* store f10 */ 349 " std 11,0x258(1)\n" /* store f11 */ 350 " std 12,0x260(1)\n" /* store f12 */ 351 " std 13,0x268(1)\n" /* store f13 */ 352 " std 14,0x270(1)\n" /* store f14 */ 353 " std 15,0x278(1)\n" /* store f15 */ 354 " stmg 0,15,0x280(1)\n"/* store general registers */ 355 " stctg 0,15,0x380(1)\n"/* store control registers */ 356 " oi 0x384(1),0x10\n"/* fake protection bit */ 357 " lpswe 0(%1)" 358 : "=m" (ctl_buf) 359 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); 360 #endif /* CONFIG_64BIT */ 361 while (1); 362 } 363 364 /* 365 * Use to set psw mask except for the first byte which 366 * won't be changed by this function. 367 */ 368 static inline void 369 __set_psw_mask(unsigned long mask) 370 { 371 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); 372 } 373 374 #define local_mcck_enable() \ 375 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK) 376 #define local_mcck_disable() \ 377 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT) 378 379 /* 380 * Basic Machine Check/Program Check Handler. 381 */ 382 383 extern void s390_base_mcck_handler(void); 384 extern void s390_base_pgm_handler(void); 385 extern void s390_base_ext_handler(void); 386 387 extern void (*s390_base_mcck_handler_fn)(void); 388 extern void (*s390_base_pgm_handler_fn)(void); 389 extern void (*s390_base_ext_handler_fn)(void); 390 391 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 392 393 extern int memcpy_real(void *, void *, size_t); 394 extern void memcpy_absolute(void *, void *, size_t); 395 396 #define mem_assign_absolute(dest, val) { \ 397 __typeof__(dest) __tmp = (val); \ 398 \ 399 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 400 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 401 } 402 403 /* 404 * Helper macro for exception table entries 405 */ 406 #define EX_TABLE(_fault, _target) \ 407 ".section __ex_table,\"a\"\n" \ 408 ".align 4\n" \ 409 ".long (" #_fault ") - .\n" \ 410 ".long (" #_target ") - .\n" \ 411 ".previous\n" 412 413 #else /* __ASSEMBLY__ */ 414 415 #define EX_TABLE(_fault, _target) \ 416 .section __ex_table,"a" ; \ 417 .align 4 ; \ 418 .long (_fault) - . ; \ 419 .long (_target) - . ; \ 420 .previous 421 422 #endif /* __ASSEMBLY__ */ 423 424 #endif /* __ASM_S390_PROCESSOR_H */ 425