1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999 4 * Author(s): Hartmut Penner (hp@de.ibm.com), 5 * Martin Schwidefsky (schwidefsky@de.ibm.com) 6 * 7 * Derived from "include/asm-i386/processor.h" 8 * Copyright (C) 1994, Linus Torvalds 9 */ 10 11 #ifndef __ASM_S390_PROCESSOR_H 12 #define __ASM_S390_PROCESSOR_H 13 14 #include <linux/const.h> 15 16 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ 17 #define CIF_ASCE 1 /* user asce needs fixup / uaccess */ 18 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 19 #define CIF_FPU 3 /* restore FPU registers */ 20 #define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */ 21 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 22 23 #define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) 24 #define _CIF_ASCE _BITUL(CIF_ASCE) 25 #define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) 26 #define _CIF_FPU _BITUL(CIF_FPU) 27 #define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) 28 #define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT) 29 30 #ifndef __ASSEMBLY__ 31 32 #include <linux/linkage.h> 33 #include <linux/irqflags.h> 34 #include <asm/cpu.h> 35 #include <asm/page.h> 36 #include <asm/ptrace.h> 37 #include <asm/setup.h> 38 #include <asm/runtime_instr.h> 39 #include <asm/fpu/types.h> 40 #include <asm/fpu/internal.h> 41 42 static inline void set_cpu_flag(int flag) 43 { 44 S390_lowcore.cpu_flags |= (1UL << flag); 45 } 46 47 static inline void clear_cpu_flag(int flag) 48 { 49 S390_lowcore.cpu_flags &= ~(1UL << flag); 50 } 51 52 static inline int test_cpu_flag(int flag) 53 { 54 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 55 } 56 57 /* 58 * Test CIF flag of another CPU. The caller needs to ensure that 59 * CPU hotplug can not happen, e.g. by disabling preemption. 60 */ 61 static inline int test_cpu_flag_of(int flag, int cpu) 62 { 63 struct lowcore *lc = lowcore_ptr[cpu]; 64 return !!(lc->cpu_flags & (1UL << flag)); 65 } 66 67 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 68 69 /* 70 * Default implementation of macro that returns current 71 * instruction pointer ("program counter"). 72 */ 73 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 74 75 static inline void get_cpu_id(struct cpuid *ptr) 76 { 77 asm volatile("stidp %0" : "=Q" (*ptr)); 78 } 79 80 void s390_adjust_jiffies(void); 81 void s390_update_cpu_mhz(void); 82 void cpu_detect_mhz_feature(void); 83 84 extern const struct seq_operations cpuinfo_op; 85 extern int sysctl_ieee_emulation_warnings; 86 extern void execve_tail(void); 87 88 /* 89 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 90 */ 91 92 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) 93 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 94 (1UL << 30) : (1UL << 41)) 95 #define TASK_SIZE TASK_SIZE_OF(current) 96 #define TASK_MAX_SIZE (1UL << 53) 97 98 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) 99 #define STACK_TOP_MAX (1UL << 42) 100 101 #define HAVE_ARCH_PICK_MMAP_LAYOUT 102 103 typedef struct { 104 __u32 ar4; 105 } mm_segment_t; 106 107 /* 108 * Thread structure 109 */ 110 struct thread_struct { 111 unsigned int acrs[NUM_ACRS]; 112 unsigned long ksp; /* kernel stack pointer */ 113 mm_segment_t mm_segment; 114 unsigned long gmap_addr; /* address of last gmap fault. */ 115 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 116 struct per_regs per_user; /* User specified PER registers */ 117 struct per_event per_event; /* Cause of the last PER trap */ 118 unsigned long per_flags; /* Flags to control debug behavior */ 119 /* pfault_wait is used to block the process on a pfault event */ 120 unsigned long pfault_wait; 121 struct list_head list; 122 /* cpu runtime instrumentation */ 123 struct runtime_instr_cb *ri_cb; 124 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 125 /* 126 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 127 * the end. 128 */ 129 struct fpu fpu; /* FP and VX register save area */ 130 }; 131 132 /* Flag to disable transactions. */ 133 #define PER_FLAG_NO_TE 1UL 134 /* Flag to enable random transaction aborts. */ 135 #define PER_FLAG_TE_ABORT_RAND 2UL 136 /* Flag to specify random transaction abort mode: 137 * - abort each transaction at a random instruction before TEND if set. 138 * - abort random transactions at a random instruction if cleared. 139 */ 140 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 141 142 typedef struct thread_struct thread_struct; 143 144 /* 145 * Stack layout of a C stack frame. 146 */ 147 #ifndef __PACK_STACK 148 struct stack_frame { 149 unsigned long back_chain; 150 unsigned long empty1[5]; 151 unsigned long gprs[10]; 152 unsigned int empty2[8]; 153 }; 154 #else 155 struct stack_frame { 156 unsigned long empty1[5]; 157 unsigned int empty2[8]; 158 unsigned long gprs[10]; 159 unsigned long back_chain; 160 }; 161 #endif 162 163 #define ARCH_MIN_TASKALIGN 8 164 165 #define INIT_THREAD { \ 166 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 167 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 168 } 169 170 /* 171 * Do necessary setup to start up a new thread. 172 */ 173 #define start_thread(regs, new_psw, new_stackp) do { \ 174 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 175 regs->psw.addr = new_psw; \ 176 regs->gprs[15] = new_stackp; \ 177 execve_tail(); \ 178 } while (0) 179 180 #define start_thread31(regs, new_psw, new_stackp) do { \ 181 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 182 regs->psw.addr = new_psw; \ 183 regs->gprs[15] = new_stackp; \ 184 crst_table_downgrade(current->mm); \ 185 execve_tail(); \ 186 } while (0) 187 188 /* Forward declaration, a strange C thing */ 189 struct task_struct; 190 struct mm_struct; 191 struct seq_file; 192 193 typedef int (*dump_trace_func_t)(void *data, unsigned long address); 194 void dump_trace(dump_trace_func_t func, void *data, 195 struct task_struct *task, unsigned long sp); 196 197 void show_cacheinfo(struct seq_file *m); 198 199 /* Free all resources held by a thread. */ 200 extern void release_thread(struct task_struct *); 201 202 /* 203 * Return saved PC of a blocked thread. 204 */ 205 extern unsigned long thread_saved_pc(struct task_struct *t); 206 207 unsigned long get_wchan(struct task_struct *p); 208 #define task_pt_regs(tsk) ((struct pt_regs *) \ 209 (task_stack_page(tsk) + THREAD_SIZE) - 1) 210 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 211 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 212 213 /* Has task runtime instrumentation enabled ? */ 214 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 215 216 static inline unsigned long current_stack_pointer(void) 217 { 218 unsigned long sp; 219 220 asm volatile("la %0,0(15)" : "=a" (sp)); 221 return sp; 222 } 223 224 static inline unsigned short stap(void) 225 { 226 unsigned short cpu_address; 227 228 asm volatile("stap %0" : "=m" (cpu_address)); 229 return cpu_address; 230 } 231 232 /* 233 * Give up the time slice of the virtual PU. 234 */ 235 void cpu_relax(void); 236 237 #define cpu_relax_lowlatency() barrier() 238 239 #define ECAG_CACHE_ATTRIBUTE 0 240 #define ECAG_CPU_ATTRIBUTE 1 241 242 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 243 { 244 unsigned long val; 245 246 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */ 247 : "=d" (val) : "a" (asi << 8 | parm)); 248 return val; 249 } 250 251 static inline void psw_set_key(unsigned int key) 252 { 253 asm volatile("spka 0(%0)" : : "d" (key)); 254 } 255 256 /* 257 * Set PSW to specified value. 258 */ 259 static inline void __load_psw(psw_t psw) 260 { 261 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 262 } 263 264 /* 265 * Set PSW mask to specified value, while leaving the 266 * PSW addr pointing to the next instruction. 267 */ 268 static inline void __load_psw_mask(unsigned long mask) 269 { 270 unsigned long addr; 271 psw_t psw; 272 273 psw.mask = mask; 274 275 asm volatile( 276 " larl %0,1f\n" 277 " stg %0,%O1+8(%R1)\n" 278 " lpswe %1\n" 279 "1:" 280 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 281 } 282 283 /* 284 * Extract current PSW mask 285 */ 286 static inline unsigned long __extract_psw(void) 287 { 288 unsigned int reg1, reg2; 289 290 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 291 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 292 } 293 294 static inline void local_mcck_enable(void) 295 { 296 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 297 } 298 299 static inline void local_mcck_disable(void) 300 { 301 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 302 } 303 304 /* 305 * Rewind PSW instruction address by specified number of bytes. 306 */ 307 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 308 { 309 unsigned long mask; 310 311 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 312 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 313 (1UL << 24) - 1; 314 return (psw.addr - ilc) & mask; 315 } 316 317 /* 318 * Function to stop a processor until the next interrupt occurs 319 */ 320 void enabled_wait(void); 321 322 /* 323 * Function to drop a processor into disabled wait state 324 */ 325 static inline void __noreturn disabled_wait(unsigned long code) 326 { 327 psw_t psw; 328 329 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 330 psw.addr = code; 331 __load_psw(psw); 332 while (1); 333 } 334 335 /* 336 * Basic Machine Check/Program Check Handler. 337 */ 338 339 extern void s390_base_mcck_handler(void); 340 extern void s390_base_pgm_handler(void); 341 extern void s390_base_ext_handler(void); 342 343 extern void (*s390_base_mcck_handler_fn)(void); 344 extern void (*s390_base_pgm_handler_fn)(void); 345 extern void (*s390_base_ext_handler_fn)(void); 346 347 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 348 349 extern int memcpy_real(void *, void *, size_t); 350 extern void memcpy_absolute(void *, void *, size_t); 351 352 #define mem_assign_absolute(dest, val) { \ 353 __typeof__(dest) __tmp = (val); \ 354 \ 355 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 356 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 357 } 358 359 #endif /* __ASSEMBLY__ */ 360 361 #endif /* __ASM_S390_PROCESSOR_H */ 362