1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/const.h> 16 17 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ 18 #define CIF_ASCE_PRIMARY 1 /* primary asce needs fixup / uaccess */ 19 #define CIF_ASCE_SECONDARY 2 /* secondary asce needs fixup / uaccess */ 20 #define CIF_NOHZ_DELAY 3 /* delay HZ disable for a tick */ 21 #define CIF_FPU 4 /* restore FPU registers */ 22 #define CIF_IGNORE_IRQ 5 /* ignore interrupt (for udelay) */ 23 #define CIF_ENABLED_WAIT 6 /* in enabled wait state */ 24 #define CIF_MCCK_GUEST 7 /* machine check happening in guest */ 25 #define CIF_DEDICATED_CPU 8 /* this CPU is dedicated */ 26 27 #define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) 28 #define _CIF_ASCE_PRIMARY _BITUL(CIF_ASCE_PRIMARY) 29 #define _CIF_ASCE_SECONDARY _BITUL(CIF_ASCE_SECONDARY) 30 #define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) 31 #define _CIF_FPU _BITUL(CIF_FPU) 32 #define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) 33 #define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT) 34 #define _CIF_MCCK_GUEST _BITUL(CIF_MCCK_GUEST) 35 #define _CIF_DEDICATED_CPU _BITUL(CIF_DEDICATED_CPU) 36 37 #ifndef __ASSEMBLY__ 38 39 #include <linux/linkage.h> 40 #include <linux/irqflags.h> 41 #include <asm/cpu.h> 42 #include <asm/page.h> 43 #include <asm/ptrace.h> 44 #include <asm/setup.h> 45 #include <asm/runtime_instr.h> 46 #include <asm/fpu/types.h> 47 #include <asm/fpu/internal.h> 48 49 static inline void set_cpu_flag(int flag) 50 { 51 S390_lowcore.cpu_flags |= (1UL << flag); 52 } 53 54 static inline void clear_cpu_flag(int flag) 55 { 56 S390_lowcore.cpu_flags &= ~(1UL << flag); 57 } 58 59 static inline int test_cpu_flag(int flag) 60 { 61 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 62 } 63 64 /* 65 * Test CIF flag of another CPU. The caller needs to ensure that 66 * CPU hotplug can not happen, e.g. by disabling preemption. 67 */ 68 static inline int test_cpu_flag_of(int flag, int cpu) 69 { 70 struct lowcore *lc = lowcore_ptr[cpu]; 71 return !!(lc->cpu_flags & (1UL << flag)); 72 } 73 74 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 75 76 /* 77 * Default implementation of macro that returns current 78 * instruction pointer ("program counter"). 79 */ 80 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 81 82 static inline void get_cpu_id(struct cpuid *ptr) 83 { 84 asm volatile("stidp %0" : "=Q" (*ptr)); 85 } 86 87 void s390_adjust_jiffies(void); 88 void s390_update_cpu_mhz(void); 89 void cpu_detect_mhz_feature(void); 90 91 extern const struct seq_operations cpuinfo_op; 92 extern int sysctl_ieee_emulation_warnings; 93 extern void execve_tail(void); 94 95 /* 96 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 97 */ 98 99 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \ 100 (1UL << 31) : -PAGE_SIZE) 101 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 102 (1UL << 30) : (1UL << 41)) 103 #define TASK_SIZE TASK_SIZE_OF(current) 104 #define TASK_SIZE_MAX (-PAGE_SIZE) 105 106 #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \ 107 (1UL << 31) : (1UL << 42)) 108 #define STACK_TOP_MAX (1UL << 42) 109 110 #define HAVE_ARCH_PICK_MMAP_LAYOUT 111 112 typedef unsigned int mm_segment_t; 113 114 /* 115 * Thread structure 116 */ 117 struct thread_struct { 118 unsigned int acrs[NUM_ACRS]; 119 unsigned long ksp; /* kernel stack pointer */ 120 unsigned long user_timer; /* task cputime in user space */ 121 unsigned long guest_timer; /* task cputime in kvm guest */ 122 unsigned long system_timer; /* task cputime in kernel space */ 123 unsigned long hardirq_timer; /* task cputime in hardirq context */ 124 unsigned long softirq_timer; /* task cputime in softirq context */ 125 unsigned long sys_call_table; /* system call table address */ 126 mm_segment_t mm_segment; 127 unsigned long gmap_addr; /* address of last gmap fault. */ 128 unsigned int gmap_write_flag; /* gmap fault write indication */ 129 unsigned int gmap_int_code; /* int code of last gmap fault */ 130 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 131 /* Per-thread information related to debugging */ 132 struct per_regs per_user; /* User specified PER registers */ 133 struct per_event per_event; /* Cause of the last PER trap */ 134 unsigned long per_flags; /* Flags to control debug behavior */ 135 unsigned int system_call; /* system call number in signal */ 136 unsigned long last_break; /* last breaking-event-address. */ 137 /* pfault_wait is used to block the process on a pfault event */ 138 unsigned long pfault_wait; 139 struct list_head list; 140 /* cpu runtime instrumentation */ 141 struct runtime_instr_cb *ri_cb; 142 struct gs_cb *gs_cb; /* Current guarded storage cb */ 143 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 144 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 145 /* 146 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 147 * the end. 148 */ 149 struct fpu fpu; /* FP and VX register save area */ 150 }; 151 152 /* Flag to disable transactions. */ 153 #define PER_FLAG_NO_TE 1UL 154 /* Flag to enable random transaction aborts. */ 155 #define PER_FLAG_TE_ABORT_RAND 2UL 156 /* Flag to specify random transaction abort mode: 157 * - abort each transaction at a random instruction before TEND if set. 158 * - abort random transactions at a random instruction if cleared. 159 */ 160 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 161 162 typedef struct thread_struct thread_struct; 163 164 /* 165 * Stack layout of a C stack frame. 166 */ 167 #ifndef __PACK_STACK 168 struct stack_frame { 169 unsigned long back_chain; 170 unsigned long empty1[5]; 171 unsigned long gprs[10]; 172 unsigned int empty2[8]; 173 }; 174 #else 175 struct stack_frame { 176 unsigned long empty1[5]; 177 unsigned int empty2[8]; 178 unsigned long gprs[10]; 179 unsigned long back_chain; 180 }; 181 #endif 182 183 #define ARCH_MIN_TASKALIGN 8 184 185 #define INIT_THREAD { \ 186 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 187 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 188 } 189 190 /* 191 * Do necessary setup to start up a new thread. 192 */ 193 #define start_thread(regs, new_psw, new_stackp) do { \ 194 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 195 regs->psw.addr = new_psw; \ 196 regs->gprs[15] = new_stackp; \ 197 execve_tail(); \ 198 } while (0) 199 200 #define start_thread31(regs, new_psw, new_stackp) do { \ 201 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 202 regs->psw.addr = new_psw; \ 203 regs->gprs[15] = new_stackp; \ 204 crst_table_downgrade(current->mm); \ 205 execve_tail(); \ 206 } while (0) 207 208 /* Forward declaration, a strange C thing */ 209 struct task_struct; 210 struct mm_struct; 211 struct seq_file; 212 struct pt_regs; 213 214 typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable); 215 void dump_trace(dump_trace_func_t func, void *data, 216 struct task_struct *task, unsigned long sp); 217 void show_registers(struct pt_regs *regs); 218 219 void show_cacheinfo(struct seq_file *m); 220 221 /* Free all resources held by a thread. */ 222 static inline void release_thread(struct task_struct *tsk) { } 223 224 /* Free guarded storage control block */ 225 void guarded_storage_release(struct task_struct *tsk); 226 227 unsigned long get_wchan(struct task_struct *p); 228 #define task_pt_regs(tsk) ((struct pt_regs *) \ 229 (task_stack_page(tsk) + THREAD_SIZE) - 1) 230 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 231 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 232 233 /* Has task runtime instrumentation enabled ? */ 234 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 235 236 static inline unsigned long current_stack_pointer(void) 237 { 238 unsigned long sp; 239 240 asm volatile("la %0,0(15)" : "=a" (sp)); 241 return sp; 242 } 243 244 static inline unsigned short stap(void) 245 { 246 unsigned short cpu_address; 247 248 asm volatile("stap %0" : "=Q" (cpu_address)); 249 return cpu_address; 250 } 251 252 /* 253 * Give up the time slice of the virtual PU. 254 */ 255 #define cpu_relax_yield cpu_relax_yield 256 void cpu_relax_yield(void); 257 258 #define cpu_relax() barrier() 259 260 #define ECAG_CACHE_ATTRIBUTE 0 261 #define ECAG_CPU_ATTRIBUTE 1 262 263 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 264 { 265 unsigned long val; 266 267 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */ 268 : "=d" (val) : "a" (asi << 8 | parm)); 269 return val; 270 } 271 272 static inline void psw_set_key(unsigned int key) 273 { 274 asm volatile("spka 0(%0)" : : "d" (key)); 275 } 276 277 /* 278 * Set PSW to specified value. 279 */ 280 static inline void __load_psw(psw_t psw) 281 { 282 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 283 } 284 285 /* 286 * Set PSW mask to specified value, while leaving the 287 * PSW addr pointing to the next instruction. 288 */ 289 static inline void __load_psw_mask(unsigned long mask) 290 { 291 unsigned long addr; 292 psw_t psw; 293 294 psw.mask = mask; 295 296 asm volatile( 297 " larl %0,1f\n" 298 " stg %0,%O1+8(%R1)\n" 299 " lpswe %1\n" 300 "1:" 301 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 302 } 303 304 /* 305 * Extract current PSW mask 306 */ 307 static inline unsigned long __extract_psw(void) 308 { 309 unsigned int reg1, reg2; 310 311 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 312 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 313 } 314 315 static inline void local_mcck_enable(void) 316 { 317 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 318 } 319 320 static inline void local_mcck_disable(void) 321 { 322 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 323 } 324 325 /* 326 * Rewind PSW instruction address by specified number of bytes. 327 */ 328 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 329 { 330 unsigned long mask; 331 332 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 333 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 334 (1UL << 24) - 1; 335 return (psw.addr - ilc) & mask; 336 } 337 338 /* 339 * Function to stop a processor until the next interrupt occurs 340 */ 341 void enabled_wait(void); 342 343 /* 344 * Function to drop a processor into disabled wait state 345 */ 346 static inline void __noreturn disabled_wait(unsigned long code) 347 { 348 psw_t psw; 349 350 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 351 psw.addr = code; 352 __load_psw(psw); 353 while (1); 354 } 355 356 /* 357 * Basic Machine Check/Program Check Handler. 358 */ 359 360 extern void s390_base_mcck_handler(void); 361 extern void s390_base_pgm_handler(void); 362 extern void s390_base_ext_handler(void); 363 364 extern void (*s390_base_mcck_handler_fn)(void); 365 extern void (*s390_base_pgm_handler_fn)(void); 366 extern void (*s390_base_ext_handler_fn)(void); 367 368 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 369 370 extern int memcpy_real(void *, void *, size_t); 371 extern void memcpy_absolute(void *, void *, size_t); 372 373 #define mem_assign_absolute(dest, val) do { \ 374 __typeof__(dest) __tmp = (val); \ 375 \ 376 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 377 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 378 } while (0) 379 380 #endif /* __ASSEMBLY__ */ 381 382 #endif /* __ASM_S390_PROCESSOR_H */ 383