1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/const.h> 16 17 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ 18 #define CIF_ASCE_PRIMARY 1 /* primary asce needs fixup / uaccess */ 19 #define CIF_ASCE_SECONDARY 2 /* secondary asce needs fixup / uaccess */ 20 #define CIF_NOHZ_DELAY 3 /* delay HZ disable for a tick */ 21 #define CIF_FPU 4 /* restore FPU registers */ 22 #define CIF_IGNORE_IRQ 5 /* ignore interrupt (for udelay) */ 23 #define CIF_ENABLED_WAIT 6 /* in enabled wait state */ 24 #define CIF_MCCK_GUEST 7 /* machine check happening in guest */ 25 #define CIF_DEDICATED_CPU 8 /* this CPU is dedicated */ 26 27 #define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) 28 #define _CIF_ASCE_PRIMARY _BITUL(CIF_ASCE_PRIMARY) 29 #define _CIF_ASCE_SECONDARY _BITUL(CIF_ASCE_SECONDARY) 30 #define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) 31 #define _CIF_FPU _BITUL(CIF_FPU) 32 #define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) 33 #define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT) 34 #define _CIF_MCCK_GUEST _BITUL(CIF_MCCK_GUEST) 35 #define _CIF_DEDICATED_CPU _BITUL(CIF_DEDICATED_CPU) 36 37 #ifndef __ASSEMBLY__ 38 39 #include <linux/linkage.h> 40 #include <linux/irqflags.h> 41 #include <asm/cpu.h> 42 #include <asm/page.h> 43 #include <asm/ptrace.h> 44 #include <asm/setup.h> 45 #include <asm/runtime_instr.h> 46 #include <asm/fpu/types.h> 47 #include <asm/fpu/internal.h> 48 49 static inline void set_cpu_flag(int flag) 50 { 51 S390_lowcore.cpu_flags |= (1UL << flag); 52 } 53 54 static inline void clear_cpu_flag(int flag) 55 { 56 S390_lowcore.cpu_flags &= ~(1UL << flag); 57 } 58 59 static inline int test_cpu_flag(int flag) 60 { 61 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 62 } 63 64 /* 65 * Test CIF flag of another CPU. The caller needs to ensure that 66 * CPU hotplug can not happen, e.g. by disabling preemption. 67 */ 68 static inline int test_cpu_flag_of(int flag, int cpu) 69 { 70 struct lowcore *lc = lowcore_ptr[cpu]; 71 return !!(lc->cpu_flags & (1UL << flag)); 72 } 73 74 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 75 76 static inline void get_cpu_id(struct cpuid *ptr) 77 { 78 asm volatile("stidp %0" : "=Q" (*ptr)); 79 } 80 81 void s390_adjust_jiffies(void); 82 void s390_update_cpu_mhz(void); 83 void cpu_detect_mhz_feature(void); 84 85 extern const struct seq_operations cpuinfo_op; 86 extern int sysctl_ieee_emulation_warnings; 87 extern void execve_tail(void); 88 extern void __bpon(void); 89 90 /* 91 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 92 */ 93 94 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \ 95 (1UL << 31) : -PAGE_SIZE) 96 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 97 (1UL << 30) : (1UL << 41)) 98 #define TASK_SIZE TASK_SIZE_OF(current) 99 #define TASK_SIZE_MAX (-PAGE_SIZE) 100 101 #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \ 102 (1UL << 31) : (1UL << 42)) 103 #define STACK_TOP_MAX (1UL << 42) 104 105 #define HAVE_ARCH_PICK_MMAP_LAYOUT 106 107 typedef unsigned int mm_segment_t; 108 109 /* 110 * Thread structure 111 */ 112 struct thread_struct { 113 unsigned int acrs[NUM_ACRS]; 114 unsigned long ksp; /* kernel stack pointer */ 115 unsigned long user_timer; /* task cputime in user space */ 116 unsigned long guest_timer; /* task cputime in kvm guest */ 117 unsigned long system_timer; /* task cputime in kernel space */ 118 unsigned long hardirq_timer; /* task cputime in hardirq context */ 119 unsigned long softirq_timer; /* task cputime in softirq context */ 120 unsigned long sys_call_table; /* system call table address */ 121 mm_segment_t mm_segment; 122 unsigned long gmap_addr; /* address of last gmap fault. */ 123 unsigned int gmap_write_flag; /* gmap fault write indication */ 124 unsigned int gmap_int_code; /* int code of last gmap fault */ 125 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 126 /* Per-thread information related to debugging */ 127 struct per_regs per_user; /* User specified PER registers */ 128 struct per_event per_event; /* Cause of the last PER trap */ 129 unsigned long per_flags; /* Flags to control debug behavior */ 130 unsigned int system_call; /* system call number in signal */ 131 unsigned long last_break; /* last breaking-event-address. */ 132 /* pfault_wait is used to block the process on a pfault event */ 133 unsigned long pfault_wait; 134 struct list_head list; 135 /* cpu runtime instrumentation */ 136 struct runtime_instr_cb *ri_cb; 137 struct gs_cb *gs_cb; /* Current guarded storage cb */ 138 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 139 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 140 /* 141 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 142 * the end. 143 */ 144 struct fpu fpu; /* FP and VX register save area */ 145 }; 146 147 /* Flag to disable transactions. */ 148 #define PER_FLAG_NO_TE 1UL 149 /* Flag to enable random transaction aborts. */ 150 #define PER_FLAG_TE_ABORT_RAND 2UL 151 /* Flag to specify random transaction abort mode: 152 * - abort each transaction at a random instruction before TEND if set. 153 * - abort random transactions at a random instruction if cleared. 154 */ 155 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 156 157 typedef struct thread_struct thread_struct; 158 159 /* 160 * Stack layout of a C stack frame. 161 */ 162 #ifndef __PACK_STACK 163 struct stack_frame { 164 unsigned long back_chain; 165 unsigned long empty1[5]; 166 unsigned long gprs[10]; 167 unsigned int empty2[8]; 168 }; 169 #else 170 struct stack_frame { 171 unsigned long empty1[5]; 172 unsigned int empty2[8]; 173 unsigned long gprs[10]; 174 unsigned long back_chain; 175 }; 176 #endif 177 178 #define ARCH_MIN_TASKALIGN 8 179 180 #define INIT_THREAD { \ 181 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 182 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 183 } 184 185 /* 186 * Do necessary setup to start up a new thread. 187 */ 188 #define start_thread(regs, new_psw, new_stackp) do { \ 189 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 190 regs->psw.addr = new_psw; \ 191 regs->gprs[15] = new_stackp; \ 192 execve_tail(); \ 193 } while (0) 194 195 #define start_thread31(regs, new_psw, new_stackp) do { \ 196 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 197 regs->psw.addr = new_psw; \ 198 regs->gprs[15] = new_stackp; \ 199 crst_table_downgrade(current->mm); \ 200 execve_tail(); \ 201 } while (0) 202 203 /* Forward declaration, a strange C thing */ 204 struct task_struct; 205 struct mm_struct; 206 struct seq_file; 207 struct pt_regs; 208 209 typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable); 210 void dump_trace(dump_trace_func_t func, void *data, 211 struct task_struct *task, unsigned long sp); 212 void show_registers(struct pt_regs *regs); 213 214 void show_cacheinfo(struct seq_file *m); 215 216 /* Free all resources held by a thread. */ 217 static inline void release_thread(struct task_struct *tsk) { } 218 219 /* Free guarded storage control block */ 220 void guarded_storage_release(struct task_struct *tsk); 221 222 unsigned long get_wchan(struct task_struct *p); 223 #define task_pt_regs(tsk) ((struct pt_regs *) \ 224 (task_stack_page(tsk) + THREAD_SIZE) - 1) 225 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 226 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 227 228 /* Has task runtime instrumentation enabled ? */ 229 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 230 231 static inline unsigned long current_stack_pointer(void) 232 { 233 unsigned long sp; 234 235 asm volatile("la %0,0(15)" : "=a" (sp)); 236 return sp; 237 } 238 239 static __no_sanitize_address_or_inline unsigned short stap(void) 240 { 241 unsigned short cpu_address; 242 243 asm volatile("stap %0" : "=Q" (cpu_address)); 244 return cpu_address; 245 } 246 247 #define CALL_ARGS_0() \ 248 register unsigned long r2 asm("2") 249 #define CALL_ARGS_1(arg1) \ 250 register unsigned long r2 asm("2") = (unsigned long)(arg1) 251 #define CALL_ARGS_2(arg1, arg2) \ 252 CALL_ARGS_1(arg1); \ 253 register unsigned long r3 asm("3") = (unsigned long)(arg2) 254 #define CALL_ARGS_3(arg1, arg2, arg3) \ 255 CALL_ARGS_2(arg1, arg2); \ 256 register unsigned long r4 asm("4") = (unsigned long)(arg3) 257 #define CALL_ARGS_4(arg1, arg2, arg3, arg4) \ 258 CALL_ARGS_3(arg1, arg2, arg3); \ 259 register unsigned long r4 asm("5") = (unsigned long)(arg4) 260 #define CALL_ARGS_5(arg1, arg2, arg3, arg4, arg5) \ 261 CALL_ARGS_4(arg1, arg2, arg3, arg4); \ 262 register unsigned long r4 asm("6") = (unsigned long)(arg5) 263 264 #define CALL_FMT_0 265 #define CALL_FMT_1 CALL_FMT_0, "0" (r2) 266 #define CALL_FMT_2 CALL_FMT_1, "d" (r3) 267 #define CALL_FMT_3 CALL_FMT_2, "d" (r4) 268 #define CALL_FMT_4 CALL_FMT_3, "d" (r5) 269 #define CALL_FMT_5 CALL_FMT_4, "d" (r6) 270 271 #define CALL_CLOBBER_5 "0", "1", "14", "cc", "memory" 272 #define CALL_CLOBBER_4 CALL_CLOBBER_5 273 #define CALL_CLOBBER_3 CALL_CLOBBER_4, "5" 274 #define CALL_CLOBBER_2 CALL_CLOBBER_3, "4" 275 #define CALL_CLOBBER_1 CALL_CLOBBER_2, "3" 276 #define CALL_CLOBBER_0 CALL_CLOBBER_1 277 278 #define CALL_ON_STACK(fn, stack, nr, args...) \ 279 ({ \ 280 CALL_ARGS_##nr(args); \ 281 unsigned long prev; \ 282 \ 283 asm volatile( \ 284 " la %[_prev],0(15)\n" \ 285 " la 15,0(%[_stack])\n" \ 286 " stg %[_prev],%[_bc](15)\n" \ 287 " brasl 14,%[_fn]\n" \ 288 " la 15,0(%[_prev])\n" \ 289 : "+&d" (r2), [_prev] "=&a" (prev) \ 290 : [_stack] "a" (stack), \ 291 [_bc] "i" (offsetof(struct stack_frame, back_chain)), \ 292 [_fn] "X" (fn) CALL_FMT_##nr : CALL_CLOBBER_##nr); \ 293 r2; \ 294 }) 295 296 /* 297 * Give up the time slice of the virtual PU. 298 */ 299 #define cpu_relax_yield cpu_relax_yield 300 void cpu_relax_yield(void); 301 302 #define cpu_relax() barrier() 303 304 #define ECAG_CACHE_ATTRIBUTE 0 305 #define ECAG_CPU_ATTRIBUTE 1 306 307 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 308 { 309 unsigned long val; 310 311 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */ 312 : "=d" (val) : "a" (asi << 8 | parm)); 313 return val; 314 } 315 316 static inline void psw_set_key(unsigned int key) 317 { 318 asm volatile("spka 0(%0)" : : "d" (key)); 319 } 320 321 /* 322 * Set PSW to specified value. 323 */ 324 static inline void __load_psw(psw_t psw) 325 { 326 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 327 } 328 329 /* 330 * Set PSW mask to specified value, while leaving the 331 * PSW addr pointing to the next instruction. 332 */ 333 static __no_sanitize_address_or_inline void __load_psw_mask(unsigned long mask) 334 { 335 unsigned long addr; 336 psw_t psw; 337 338 psw.mask = mask; 339 340 asm volatile( 341 " larl %0,1f\n" 342 " stg %0,%O1+8(%R1)\n" 343 " lpswe %1\n" 344 "1:" 345 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 346 } 347 348 /* 349 * Extract current PSW mask 350 */ 351 static inline unsigned long __extract_psw(void) 352 { 353 unsigned int reg1, reg2; 354 355 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 356 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 357 } 358 359 static inline void local_mcck_enable(void) 360 { 361 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 362 } 363 364 static inline void local_mcck_disable(void) 365 { 366 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 367 } 368 369 /* 370 * Rewind PSW instruction address by specified number of bytes. 371 */ 372 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 373 { 374 unsigned long mask; 375 376 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 377 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 378 (1UL << 24) - 1; 379 return (psw.addr - ilc) & mask; 380 } 381 382 /* 383 * Function to stop a processor until the next interrupt occurs 384 */ 385 void enabled_wait(void); 386 387 /* 388 * Function to drop a processor into disabled wait state 389 */ 390 static inline void __noreturn disabled_wait(unsigned long code) 391 { 392 psw_t psw; 393 394 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 395 psw.addr = code; 396 __load_psw(psw); 397 while (1); 398 } 399 400 /* 401 * Basic Machine Check/Program Check Handler. 402 */ 403 404 extern void s390_base_mcck_handler(void); 405 extern void s390_base_pgm_handler(void); 406 extern void s390_base_ext_handler(void); 407 408 extern void (*s390_base_mcck_handler_fn)(void); 409 extern void (*s390_base_pgm_handler_fn)(void); 410 extern void (*s390_base_ext_handler_fn)(void); 411 412 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 413 414 extern int memcpy_real(void *, void *, size_t); 415 extern void memcpy_absolute(void *, void *, size_t); 416 417 #define mem_assign_absolute(dest, val) do { \ 418 __typeof__(dest) __tmp = (val); \ 419 \ 420 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 421 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 422 } while (0) 423 424 extern int s390_isolate_bp(void); 425 extern int s390_isolate_bp_guest(void); 426 427 #endif /* __ASSEMBLY__ */ 428 429 #endif /* __ASM_S390_PROCESSOR_H */ 430