1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/bits.h> 16 17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 18 #define CIF_FPU 3 /* restore FPU registers */ 19 #define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */ 20 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 21 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */ 22 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */ 23 24 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY) 25 #define _CIF_FPU BIT(CIF_FPU) 26 #define _CIF_IGNORE_IRQ BIT(CIF_IGNORE_IRQ) 27 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) 28 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) 29 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) 30 31 #ifndef __ASSEMBLY__ 32 33 #include <linux/cpumask.h> 34 #include <linux/linkage.h> 35 #include <linux/irqflags.h> 36 #include <asm/cpu.h> 37 #include <asm/page.h> 38 #include <asm/ptrace.h> 39 #include <asm/setup.h> 40 #include <asm/runtime_instr.h> 41 #include <asm/fpu/types.h> 42 #include <asm/fpu/internal.h> 43 44 static inline void set_cpu_flag(int flag) 45 { 46 S390_lowcore.cpu_flags |= (1UL << flag); 47 } 48 49 static inline void clear_cpu_flag(int flag) 50 { 51 S390_lowcore.cpu_flags &= ~(1UL << flag); 52 } 53 54 static inline int test_cpu_flag(int flag) 55 { 56 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 57 } 58 59 /* 60 * Test CIF flag of another CPU. The caller needs to ensure that 61 * CPU hotplug can not happen, e.g. by disabling preemption. 62 */ 63 static inline int test_cpu_flag_of(int flag, int cpu) 64 { 65 struct lowcore *lc = lowcore_ptr[cpu]; 66 return !!(lc->cpu_flags & (1UL << flag)); 67 } 68 69 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 70 71 static inline void get_cpu_id(struct cpuid *ptr) 72 { 73 asm volatile("stidp %0" : "=Q" (*ptr)); 74 } 75 76 void s390_adjust_jiffies(void); 77 void s390_update_cpu_mhz(void); 78 void cpu_detect_mhz_feature(void); 79 80 extern const struct seq_operations cpuinfo_op; 81 extern void execve_tail(void); 82 extern void __bpon(void); 83 84 /* 85 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 86 */ 87 88 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \ 89 _REGION3_SIZE : TASK_SIZE_MAX) 90 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 91 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1)) 92 #define TASK_SIZE TASK_SIZE_OF(current) 93 #define TASK_SIZE_MAX (-PAGE_SIZE) 94 95 #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \ 96 _REGION3_SIZE : _REGION2_SIZE) 97 #define STACK_TOP_MAX _REGION2_SIZE 98 99 #define HAVE_ARCH_PICK_MMAP_LAYOUT 100 101 /* 102 * Thread structure 103 */ 104 struct thread_struct { 105 unsigned int acrs[NUM_ACRS]; 106 unsigned long ksp; /* kernel stack pointer */ 107 unsigned long user_timer; /* task cputime in user space */ 108 unsigned long guest_timer; /* task cputime in kvm guest */ 109 unsigned long system_timer; /* task cputime in kernel space */ 110 unsigned long hardirq_timer; /* task cputime in hardirq context */ 111 unsigned long softirq_timer; /* task cputime in softirq context */ 112 unsigned long sys_call_table; /* system call table address */ 113 unsigned long gmap_addr; /* address of last gmap fault. */ 114 unsigned int gmap_write_flag; /* gmap fault write indication */ 115 unsigned int gmap_int_code; /* int code of last gmap fault */ 116 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 117 /* Per-thread information related to debugging */ 118 struct per_regs per_user; /* User specified PER registers */ 119 struct per_event per_event; /* Cause of the last PER trap */ 120 unsigned long per_flags; /* Flags to control debug behavior */ 121 unsigned int system_call; /* system call number in signal */ 122 unsigned long last_break; /* last breaking-event-address. */ 123 /* pfault_wait is used to block the process on a pfault event */ 124 unsigned long pfault_wait; 125 struct list_head list; 126 /* cpu runtime instrumentation */ 127 struct runtime_instr_cb *ri_cb; 128 struct gs_cb *gs_cb; /* Current guarded storage cb */ 129 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 130 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 131 /* 132 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 133 * the end. 134 */ 135 struct fpu fpu; /* FP and VX register save area */ 136 }; 137 138 /* Flag to disable transactions. */ 139 #define PER_FLAG_NO_TE 1UL 140 /* Flag to enable random transaction aborts. */ 141 #define PER_FLAG_TE_ABORT_RAND 2UL 142 /* Flag to specify random transaction abort mode: 143 * - abort each transaction at a random instruction before TEND if set. 144 * - abort random transactions at a random instruction if cleared. 145 */ 146 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 147 148 typedef struct thread_struct thread_struct; 149 150 #define ARCH_MIN_TASKALIGN 8 151 152 #define INIT_THREAD { \ 153 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 154 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 155 .last_break = 1, \ 156 } 157 158 /* 159 * Do necessary setup to start up a new thread. 160 */ 161 #define start_thread(regs, new_psw, new_stackp) do { \ 162 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 163 regs->psw.addr = new_psw; \ 164 regs->gprs[15] = new_stackp; \ 165 execve_tail(); \ 166 } while (0) 167 168 #define start_thread31(regs, new_psw, new_stackp) do { \ 169 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 170 regs->psw.addr = new_psw; \ 171 regs->gprs[15] = new_stackp; \ 172 execve_tail(); \ 173 } while (0) 174 175 /* Forward declaration, a strange C thing */ 176 struct task_struct; 177 struct mm_struct; 178 struct seq_file; 179 struct pt_regs; 180 181 void show_registers(struct pt_regs *regs); 182 void show_cacheinfo(struct seq_file *m); 183 184 /* Free all resources held by a thread. */ 185 static inline void release_thread(struct task_struct *tsk) { } 186 187 /* Free guarded storage control block */ 188 void guarded_storage_release(struct task_struct *tsk); 189 190 unsigned long get_wchan(struct task_struct *p); 191 #define task_pt_regs(tsk) ((struct pt_regs *) \ 192 (task_stack_page(tsk) + THREAD_SIZE) - 1) 193 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 194 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 195 196 /* Has task runtime instrumentation enabled ? */ 197 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 198 199 static __always_inline unsigned long current_stack_pointer(void) 200 { 201 unsigned long sp; 202 203 asm volatile("la %0,0(15)" : "=a" (sp)); 204 return sp; 205 } 206 207 static __no_kasan_or_inline unsigned short stap(void) 208 { 209 unsigned short cpu_address; 210 211 asm volatile("stap %0" : "=Q" (cpu_address)); 212 return cpu_address; 213 } 214 215 #define cpu_relax() barrier() 216 217 #define ECAG_CACHE_ATTRIBUTE 0 218 #define ECAG_CPU_ATTRIBUTE 1 219 220 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 221 { 222 unsigned long val; 223 224 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */ 225 : "=d" (val) : "a" (asi << 8 | parm)); 226 return val; 227 } 228 229 static inline void psw_set_key(unsigned int key) 230 { 231 asm volatile("spka 0(%0)" : : "d" (key)); 232 } 233 234 /* 235 * Set PSW to specified value. 236 */ 237 static inline void __load_psw(psw_t psw) 238 { 239 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 240 } 241 242 /* 243 * Set PSW mask to specified value, while leaving the 244 * PSW addr pointing to the next instruction. 245 */ 246 static __no_kasan_or_inline void __load_psw_mask(unsigned long mask) 247 { 248 unsigned long addr; 249 psw_t psw; 250 251 psw.mask = mask; 252 253 asm volatile( 254 " larl %0,1f\n" 255 " stg %0,%1\n" 256 " lpswe %2\n" 257 "1:" 258 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc"); 259 } 260 261 /* 262 * Extract current PSW mask 263 */ 264 static inline unsigned long __extract_psw(void) 265 { 266 unsigned int reg1, reg2; 267 268 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 269 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 270 } 271 272 static inline void local_mcck_enable(void) 273 { 274 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 275 } 276 277 static inline void local_mcck_disable(void) 278 { 279 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 280 } 281 282 /* 283 * Rewind PSW instruction address by specified number of bytes. 284 */ 285 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 286 { 287 unsigned long mask; 288 289 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 290 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 291 (1UL << 24) - 1; 292 return (psw.addr - ilc) & mask; 293 } 294 295 /* 296 * Function to stop a processor until the next interrupt occurs 297 */ 298 void enabled_wait(void); 299 300 /* 301 * Function to drop a processor into disabled wait state 302 */ 303 static __always_inline void __noreturn disabled_wait(void) 304 { 305 psw_t psw; 306 307 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 308 psw.addr = _THIS_IP_; 309 __load_psw(psw); 310 while (1); 311 } 312 313 /* 314 * Basic Program Check Handler. 315 */ 316 extern void s390_base_pgm_handler(void); 317 extern void (*s390_base_pgm_handler_fn)(void); 318 319 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 320 321 extern int memcpy_real(void *, void *, size_t); 322 extern void memcpy_absolute(void *, void *, size_t); 323 324 #define mem_assign_absolute(dest, val) do { \ 325 __typeof__(dest) __tmp = (val); \ 326 \ 327 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 328 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 329 } while (0) 330 331 extern int s390_isolate_bp(void); 332 extern int s390_isolate_bp_guest(void); 333 334 #endif /* __ASSEMBLY__ */ 335 336 #endif /* __ASM_S390_PROCESSOR_H */ 337