1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/bug.h> 22 #include <asm/page.h> 23 #include <asm/uv.h> 24 25 extern pgd_t swapper_pg_dir[]; 26 extern pgd_t invalid_pg_dir[]; 27 extern void paging_init(void); 28 extern unsigned long s390_invalid_asce; 29 30 enum { 31 PG_DIRECT_MAP_4K = 0, 32 PG_DIRECT_MAP_1M, 33 PG_DIRECT_MAP_2G, 34 PG_DIRECT_MAP_MAX 35 }; 36 37 extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; 38 39 static inline void update_page_count(int level, long count) 40 { 41 if (IS_ENABLED(CONFIG_PROC_FS)) 42 atomic_long_add(count, &direct_pages_count[level]); 43 } 44 45 struct seq_file; 46 void arch_report_meminfo(struct seq_file *m); 47 48 /* 49 * The S390 doesn't have any external MMU info: the kernel page 50 * tables contain all the necessary information. 51 */ 52 #define update_mmu_cache(vma, address, ptep) do { } while (0) 53 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 54 55 /* 56 * ZERO_PAGE is a global shared page that is always zero; used 57 * for zero-mapped memory areas etc.. 58 */ 59 60 extern unsigned long empty_zero_page; 61 extern unsigned long zero_page_mask; 62 63 #define ZERO_PAGE(vaddr) \ 64 (virt_to_page((void *)(empty_zero_page + \ 65 (((unsigned long)(vaddr)) &zero_page_mask)))) 66 #define __HAVE_COLOR_ZERO_PAGE 67 68 /* TODO: s390 cannot support io_remap_pfn_range... */ 69 70 #define pte_ERROR(e) \ 71 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 72 #define pmd_ERROR(e) \ 73 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 74 #define pud_ERROR(e) \ 75 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 76 #define p4d_ERROR(e) \ 77 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 78 #define pgd_ERROR(e) \ 79 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 80 81 /* 82 * The vmalloc and module area will always be on the topmost area of the 83 * kernel mapping. 512GB are reserved for vmalloc by default. 84 * At the top of the vmalloc area a 2GB area is reserved where modules 85 * will reside. That makes sure that inter module branches always 86 * happen without trampolines and in addition the placement within a 87 * 2GB frame is branch prediction unit friendly. 88 */ 89 extern unsigned long __bootdata_preserved(VMALLOC_START); 90 extern unsigned long __bootdata_preserved(VMALLOC_END); 91 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 92 extern struct page *__bootdata_preserved(vmemmap); 93 extern unsigned long __bootdata_preserved(vmemmap_size); 94 95 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 96 97 extern unsigned long __bootdata_preserved(MODULES_VADDR); 98 extern unsigned long __bootdata_preserved(MODULES_END); 99 #define MODULES_VADDR MODULES_VADDR 100 #define MODULES_END MODULES_END 101 #define MODULES_LEN (1UL << 31) 102 103 static inline int is_module_addr(void *addr) 104 { 105 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 106 if (addr < (void *)MODULES_VADDR) 107 return 0; 108 if (addr > (void *)MODULES_END) 109 return 0; 110 return 1; 111 } 112 113 /* 114 * A 64 bit pagetable entry of S390 has following format: 115 * | PFRA |0IPC| OS | 116 * 0000000000111111111122222222223333333333444444444455555555556666 117 * 0123456789012345678901234567890123456789012345678901234567890123 118 * 119 * I Page-Invalid Bit: Page is not available for address-translation 120 * P Page-Protection Bit: Store access not possible for page 121 * C Change-bit override: HW is not required to set change bit 122 * 123 * A 64 bit segmenttable entry of S390 has following format: 124 * | P-table origin | TT 125 * 0000000000111111111122222222223333333333444444444455555555556666 126 * 0123456789012345678901234567890123456789012345678901234567890123 127 * 128 * I Segment-Invalid Bit: Segment is not available for address-translation 129 * C Common-Segment Bit: Segment is not private (PoP 3-30) 130 * P Page-Protection Bit: Store access not possible for page 131 * TT Type 00 132 * 133 * A 64 bit region table entry of S390 has following format: 134 * | S-table origin | TF TTTL 135 * 0000000000111111111122222222223333333333444444444455555555556666 136 * 0123456789012345678901234567890123456789012345678901234567890123 137 * 138 * I Segment-Invalid Bit: Segment is not available for address-translation 139 * TT Type 01 140 * TF 141 * TL Table length 142 * 143 * The 64 bit regiontable origin of S390 has following format: 144 * | region table origon | DTTL 145 * 0000000000111111111122222222223333333333444444444455555555556666 146 * 0123456789012345678901234567890123456789012345678901234567890123 147 * 148 * X Space-Switch event: 149 * G Segment-Invalid Bit: 150 * P Private-Space Bit: 151 * S Storage-Alteration: 152 * R Real space 153 * TL Table-Length: 154 * 155 * A storage key has the following format: 156 * | ACC |F|R|C|0| 157 * 0 3 4 5 6 7 158 * ACC: access key 159 * F : fetch protection bit 160 * R : referenced bit 161 * C : changed bit 162 */ 163 164 /* Hardware bits in the page table entry */ 165 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 166 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 167 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 168 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 169 170 /* Software bits in the page table entry */ 171 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 172 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 173 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 174 #define _PAGE_READ 0x010 /* SW pte read bit */ 175 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 176 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 177 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 178 179 #ifdef CONFIG_MEM_SOFT_DIRTY 180 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 181 #else 182 #define _PAGE_SOFT_DIRTY 0x000 183 #endif 184 185 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 186 187 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 188 189 /* Set of bits not changed in pte_modify */ 190 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 191 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 192 193 /* 194 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 195 * HW bit and all SW bits. 196 */ 197 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 198 199 /* 200 * handle_pte_fault uses pte_present and pte_none to find out the pte type 201 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 202 * distinguish present from not-present ptes. It is changed only with the page 203 * table lock held. 204 * 205 * The following table gives the different possible bit combinations for 206 * the pte hardware and software bits in the last 12 bits of a pte 207 * (. unassigned bit, x don't care, t swap type): 208 * 209 * 842100000000 210 * 000084210000 211 * 000000008421 212 * .IR.uswrdy.p 213 * empty .10.00000000 214 * swap .11..ttttt.0 215 * prot-none, clean, old .11.xx0000.1 216 * prot-none, clean, young .11.xx0001.1 217 * prot-none, dirty, old .11.xx0010.1 218 * prot-none, dirty, young .11.xx0011.1 219 * read-only, clean, old .11.xx0100.1 220 * read-only, clean, young .01.xx0101.1 221 * read-only, dirty, old .11.xx0110.1 222 * read-only, dirty, young .01.xx0111.1 223 * read-write, clean, old .11.xx1100.1 224 * read-write, clean, young .01.xx1101.1 225 * read-write, dirty, old .10.xx1110.1 226 * read-write, dirty, young .00.xx1111.1 227 * HW-bits: R read-only, I invalid 228 * SW-bits: p present, y young, d dirty, r read, w write, s special, 229 * u unused, l large 230 * 231 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 232 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 233 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 234 */ 235 236 /* Bits in the segment/region table address-space-control-element */ 237 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 238 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 239 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 240 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 241 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 242 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 243 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 244 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 245 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 246 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 247 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 248 249 /* Bits in the region table entry */ 250 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 251 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 252 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 253 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 254 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 255 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 256 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 257 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 258 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 259 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 260 261 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 262 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 263 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 264 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 265 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 266 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 267 268 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 269 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 270 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 271 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 272 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 273 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 274 275 #ifdef CONFIG_MEM_SOFT_DIRTY 276 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 277 #else 278 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 279 #endif 280 281 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 282 283 /* Bits in the segment table entry */ 284 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 285 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 286 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 287 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 288 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 289 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 290 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 291 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 292 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 293 294 #define _SEGMENT_ENTRY (0) 295 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 296 297 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 298 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 299 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 300 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 301 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 302 303 #ifdef CONFIG_MEM_SOFT_DIRTY 304 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 305 #else 306 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 307 #endif 308 309 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 310 #define _PAGE_ENTRIES 256 /* number of page table entries */ 311 312 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 313 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 314 315 #define _REGION1_SHIFT 53 316 #define _REGION2_SHIFT 42 317 #define _REGION3_SHIFT 31 318 #define _SEGMENT_SHIFT 20 319 320 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 321 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 322 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 323 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 324 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 325 326 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 327 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 328 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 329 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 330 331 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 332 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 333 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 334 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 335 336 #define PMD_SHIFT _SEGMENT_SHIFT 337 #define PUD_SHIFT _REGION3_SHIFT 338 #define P4D_SHIFT _REGION2_SHIFT 339 #define PGDIR_SHIFT _REGION1_SHIFT 340 341 #define PMD_SIZE _SEGMENT_SIZE 342 #define PUD_SIZE _REGION3_SIZE 343 #define P4D_SIZE _REGION2_SIZE 344 #define PGDIR_SIZE _REGION1_SIZE 345 346 #define PMD_MASK _SEGMENT_MASK 347 #define PUD_MASK _REGION3_MASK 348 #define P4D_MASK _REGION2_MASK 349 #define PGDIR_MASK _REGION1_MASK 350 351 #define PTRS_PER_PTE _PAGE_ENTRIES 352 #define PTRS_PER_PMD _CRST_ENTRIES 353 #define PTRS_PER_PUD _CRST_ENTRIES 354 #define PTRS_PER_P4D _CRST_ENTRIES 355 #define PTRS_PER_PGD _CRST_ENTRIES 356 357 /* 358 * Segment table and region3 table entry encoding 359 * (R = read-only, I = invalid, y = young bit): 360 * dy..R...I...wr 361 * prot-none, clean, old 00..1...1...00 362 * prot-none, clean, young 01..1...1...00 363 * prot-none, dirty, old 10..1...1...00 364 * prot-none, dirty, young 11..1...1...00 365 * read-only, clean, old 00..1...1...01 366 * read-only, clean, young 01..1...0...01 367 * read-only, dirty, old 10..1...1...01 368 * read-only, dirty, young 11..1...0...01 369 * read-write, clean, old 00..1...1...11 370 * read-write, clean, young 01..1...0...11 371 * read-write, dirty, old 10..0...1...11 372 * read-write, dirty, young 11..0...0...11 373 * The segment table origin is used to distinguish empty (origin==0) from 374 * read-write, old segment table entries (origin!=0) 375 * HW-bits: R read-only, I invalid 376 * SW-bits: y young, d dirty, r read, w write 377 */ 378 379 /* Page status table bits for virtualization */ 380 #define PGSTE_ACC_BITS 0xf000000000000000UL 381 #define PGSTE_FP_BIT 0x0800000000000000UL 382 #define PGSTE_PCL_BIT 0x0080000000000000UL 383 #define PGSTE_HR_BIT 0x0040000000000000UL 384 #define PGSTE_HC_BIT 0x0020000000000000UL 385 #define PGSTE_GR_BIT 0x0004000000000000UL 386 #define PGSTE_GC_BIT 0x0002000000000000UL 387 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 388 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 389 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 390 391 /* Guest Page State used for virtualization */ 392 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 393 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 394 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 395 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 396 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 397 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 398 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 399 400 /* 401 * A user page table pointer has the space-switch-event bit, the 402 * private-space-control bit and the storage-alteration-event-control 403 * bit set. A kernel page table pointer doesn't need them. 404 */ 405 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 406 _ASCE_ALT_EVENT) 407 408 /* 409 * Page protection definitions. 410 */ 411 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 412 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 413 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 414 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 415 _PAGE_INVALID | _PAGE_PROTECT) 416 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 417 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 418 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 419 _PAGE_INVALID | _PAGE_PROTECT) 420 421 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 422 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 423 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 424 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 425 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 426 _PAGE_PROTECT | _PAGE_NOEXEC) 427 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 428 _PAGE_YOUNG | _PAGE_DIRTY) 429 430 /* 431 * On s390 the page table entry has an invalid bit and a read-only bit. 432 * Read permission implies execute permission and write permission 433 * implies read permission. 434 */ 435 /*xwr*/ 436 437 /* 438 * Segment entry (large page) protection definitions. 439 */ 440 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 441 _SEGMENT_ENTRY_PROTECT) 442 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 443 _SEGMENT_ENTRY_READ | \ 444 _SEGMENT_ENTRY_NOEXEC) 445 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 446 _SEGMENT_ENTRY_READ) 447 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 448 _SEGMENT_ENTRY_WRITE | \ 449 _SEGMENT_ENTRY_NOEXEC) 450 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 451 _SEGMENT_ENTRY_WRITE) 452 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 453 _SEGMENT_ENTRY_LARGE | \ 454 _SEGMENT_ENTRY_READ | \ 455 _SEGMENT_ENTRY_WRITE | \ 456 _SEGMENT_ENTRY_YOUNG | \ 457 _SEGMENT_ENTRY_DIRTY | \ 458 _SEGMENT_ENTRY_NOEXEC) 459 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 460 _SEGMENT_ENTRY_LARGE | \ 461 _SEGMENT_ENTRY_READ | \ 462 _SEGMENT_ENTRY_YOUNG | \ 463 _SEGMENT_ENTRY_PROTECT | \ 464 _SEGMENT_ENTRY_NOEXEC) 465 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 466 _SEGMENT_ENTRY_LARGE | \ 467 _SEGMENT_ENTRY_READ | \ 468 _SEGMENT_ENTRY_WRITE | \ 469 _SEGMENT_ENTRY_YOUNG | \ 470 _SEGMENT_ENTRY_DIRTY) 471 472 /* 473 * Region3 entry (large page) protection definitions. 474 */ 475 476 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 477 _REGION3_ENTRY_LARGE | \ 478 _REGION3_ENTRY_READ | \ 479 _REGION3_ENTRY_WRITE | \ 480 _REGION3_ENTRY_YOUNG | \ 481 _REGION3_ENTRY_DIRTY | \ 482 _REGION_ENTRY_NOEXEC) 483 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 484 _REGION3_ENTRY_LARGE | \ 485 _REGION3_ENTRY_READ | \ 486 _REGION3_ENTRY_YOUNG | \ 487 _REGION_ENTRY_PROTECT | \ 488 _REGION_ENTRY_NOEXEC) 489 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 490 _REGION3_ENTRY_LARGE | \ 491 _REGION3_ENTRY_READ | \ 492 _REGION3_ENTRY_WRITE | \ 493 _REGION3_ENTRY_YOUNG | \ 494 _REGION3_ENTRY_DIRTY) 495 496 static inline bool mm_p4d_folded(struct mm_struct *mm) 497 { 498 return mm->context.asce_limit <= _REGION1_SIZE; 499 } 500 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 501 502 static inline bool mm_pud_folded(struct mm_struct *mm) 503 { 504 return mm->context.asce_limit <= _REGION2_SIZE; 505 } 506 #define mm_pud_folded(mm) mm_pud_folded(mm) 507 508 static inline bool mm_pmd_folded(struct mm_struct *mm) 509 { 510 return mm->context.asce_limit <= _REGION3_SIZE; 511 } 512 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 513 514 static inline int mm_has_pgste(struct mm_struct *mm) 515 { 516 #ifdef CONFIG_PGSTE 517 if (unlikely(mm->context.has_pgste)) 518 return 1; 519 #endif 520 return 0; 521 } 522 523 static inline int mm_is_protected(struct mm_struct *mm) 524 { 525 #ifdef CONFIG_PGSTE 526 if (unlikely(atomic_read(&mm->context.protected_count))) 527 return 1; 528 #endif 529 return 0; 530 } 531 532 static inline int mm_alloc_pgste(struct mm_struct *mm) 533 { 534 #ifdef CONFIG_PGSTE 535 if (unlikely(mm->context.alloc_pgste)) 536 return 1; 537 #endif 538 return 0; 539 } 540 541 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 542 { 543 return __pte(pte_val(pte) & ~pgprot_val(prot)); 544 } 545 546 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 547 { 548 return __pte(pte_val(pte) | pgprot_val(prot)); 549 } 550 551 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 552 { 553 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 554 } 555 556 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 557 { 558 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 559 } 560 561 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 562 { 563 return __pud(pud_val(pud) & ~pgprot_val(prot)); 564 } 565 566 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 567 { 568 return __pud(pud_val(pud) | pgprot_val(prot)); 569 } 570 571 /* 572 * In the case that a guest uses storage keys 573 * faults should no longer be backed by zero pages 574 */ 575 #define mm_forbids_zeropage mm_has_pgste 576 static inline int mm_uses_skeys(struct mm_struct *mm) 577 { 578 #ifdef CONFIG_PGSTE 579 if (mm->context.uses_skeys) 580 return 1; 581 #endif 582 return 0; 583 } 584 585 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 586 { 587 union register_pair r1 = { .even = old, .odd = new, }; 588 unsigned long address = (unsigned long)ptr | 1; 589 590 asm volatile( 591 " csp %[r1],%[address]" 592 : [r1] "+&d" (r1.pair), "+m" (*ptr) 593 : [address] "d" (address) 594 : "cc"); 595 } 596 597 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 598 { 599 union register_pair r1 = { .even = old, .odd = new, }; 600 unsigned long address = (unsigned long)ptr | 1; 601 602 asm volatile( 603 " cspg %[r1],%[address]" 604 : [r1] "+&d" (r1.pair), "+m" (*ptr) 605 : [address] "d" (address) 606 : "cc"); 607 } 608 609 #define CRDTE_DTT_PAGE 0x00UL 610 #define CRDTE_DTT_SEGMENT 0x10UL 611 #define CRDTE_DTT_REGION3 0x14UL 612 #define CRDTE_DTT_REGION2 0x18UL 613 #define CRDTE_DTT_REGION1 0x1cUL 614 615 static inline void crdte(unsigned long old, unsigned long new, 616 unsigned long *table, unsigned long dtt, 617 unsigned long address, unsigned long asce) 618 { 619 union register_pair r1 = { .even = old, .odd = new, }; 620 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 621 622 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 623 : [r1] "+&d" (r1.pair) 624 : [r2] "d" (r2.pair), [asce] "a" (asce) 625 : "memory", "cc"); 626 } 627 628 /* 629 * pgd/p4d/pud/pmd/pte query functions 630 */ 631 static inline int pgd_folded(pgd_t pgd) 632 { 633 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 634 } 635 636 static inline int pgd_present(pgd_t pgd) 637 { 638 if (pgd_folded(pgd)) 639 return 1; 640 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 641 } 642 643 static inline int pgd_none(pgd_t pgd) 644 { 645 if (pgd_folded(pgd)) 646 return 0; 647 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 648 } 649 650 static inline int pgd_bad(pgd_t pgd) 651 { 652 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 653 return 0; 654 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 655 } 656 657 static inline unsigned long pgd_pfn(pgd_t pgd) 658 { 659 unsigned long origin_mask; 660 661 origin_mask = _REGION_ENTRY_ORIGIN; 662 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 663 } 664 665 static inline int p4d_folded(p4d_t p4d) 666 { 667 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 668 } 669 670 static inline int p4d_present(p4d_t p4d) 671 { 672 if (p4d_folded(p4d)) 673 return 1; 674 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 675 } 676 677 static inline int p4d_none(p4d_t p4d) 678 { 679 if (p4d_folded(p4d)) 680 return 0; 681 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 682 } 683 684 static inline unsigned long p4d_pfn(p4d_t p4d) 685 { 686 unsigned long origin_mask; 687 688 origin_mask = _REGION_ENTRY_ORIGIN; 689 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 690 } 691 692 static inline int pud_folded(pud_t pud) 693 { 694 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 695 } 696 697 static inline int pud_present(pud_t pud) 698 { 699 if (pud_folded(pud)) 700 return 1; 701 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 702 } 703 704 static inline int pud_none(pud_t pud) 705 { 706 if (pud_folded(pud)) 707 return 0; 708 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 709 } 710 711 #define pud_leaf pud_large 712 static inline int pud_large(pud_t pud) 713 { 714 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 715 return 0; 716 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 717 } 718 719 #define pmd_leaf pmd_large 720 static inline int pmd_large(pmd_t pmd) 721 { 722 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 723 } 724 725 static inline int pmd_bad(pmd_t pmd) 726 { 727 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 728 return 1; 729 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 730 } 731 732 static inline int pud_bad(pud_t pud) 733 { 734 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 735 736 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud)) 737 return 1; 738 if (type < _REGION_ENTRY_TYPE_R3) 739 return 0; 740 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 741 } 742 743 static inline int p4d_bad(p4d_t p4d) 744 { 745 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 746 747 if (type > _REGION_ENTRY_TYPE_R2) 748 return 1; 749 if (type < _REGION_ENTRY_TYPE_R2) 750 return 0; 751 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 752 } 753 754 static inline int pmd_present(pmd_t pmd) 755 { 756 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 757 } 758 759 static inline int pmd_none(pmd_t pmd) 760 { 761 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 762 } 763 764 #define pmd_write pmd_write 765 static inline int pmd_write(pmd_t pmd) 766 { 767 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 768 } 769 770 #define pud_write pud_write 771 static inline int pud_write(pud_t pud) 772 { 773 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 774 } 775 776 static inline int pmd_dirty(pmd_t pmd) 777 { 778 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 779 } 780 781 #define pmd_young pmd_young 782 static inline int pmd_young(pmd_t pmd) 783 { 784 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 785 } 786 787 static inline int pte_present(pte_t pte) 788 { 789 /* Bit pattern: (pte & 0x001) == 0x001 */ 790 return (pte_val(pte) & _PAGE_PRESENT) != 0; 791 } 792 793 static inline int pte_none(pte_t pte) 794 { 795 /* Bit pattern: pte == 0x400 */ 796 return pte_val(pte) == _PAGE_INVALID; 797 } 798 799 static inline int pte_swap(pte_t pte) 800 { 801 /* Bit pattern: (pte & 0x201) == 0x200 */ 802 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 803 == _PAGE_PROTECT; 804 } 805 806 static inline int pte_special(pte_t pte) 807 { 808 return (pte_val(pte) & _PAGE_SPECIAL); 809 } 810 811 #define __HAVE_ARCH_PTE_SAME 812 static inline int pte_same(pte_t a, pte_t b) 813 { 814 return pte_val(a) == pte_val(b); 815 } 816 817 #ifdef CONFIG_NUMA_BALANCING 818 static inline int pte_protnone(pte_t pte) 819 { 820 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 821 } 822 823 static inline int pmd_protnone(pmd_t pmd) 824 { 825 /* pmd_large(pmd) implies pmd_present(pmd) */ 826 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 827 } 828 #endif 829 830 static inline int pte_swp_exclusive(pte_t pte) 831 { 832 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 833 } 834 835 static inline pte_t pte_swp_mkexclusive(pte_t pte) 836 { 837 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 838 } 839 840 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 841 { 842 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 843 } 844 845 static inline int pte_soft_dirty(pte_t pte) 846 { 847 return pte_val(pte) & _PAGE_SOFT_DIRTY; 848 } 849 #define pte_swp_soft_dirty pte_soft_dirty 850 851 static inline pte_t pte_mksoft_dirty(pte_t pte) 852 { 853 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 854 } 855 #define pte_swp_mksoft_dirty pte_mksoft_dirty 856 857 static inline pte_t pte_clear_soft_dirty(pte_t pte) 858 { 859 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 860 } 861 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 862 863 static inline int pmd_soft_dirty(pmd_t pmd) 864 { 865 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 866 } 867 868 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 869 { 870 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 871 } 872 873 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 874 { 875 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 876 } 877 878 /* 879 * query functions pte_write/pte_dirty/pte_young only work if 880 * pte_present() is true. Undefined behaviour if not.. 881 */ 882 static inline int pte_write(pte_t pte) 883 { 884 return (pte_val(pte) & _PAGE_WRITE) != 0; 885 } 886 887 static inline int pte_dirty(pte_t pte) 888 { 889 return (pte_val(pte) & _PAGE_DIRTY) != 0; 890 } 891 892 static inline int pte_young(pte_t pte) 893 { 894 return (pte_val(pte) & _PAGE_YOUNG) != 0; 895 } 896 897 #define __HAVE_ARCH_PTE_UNUSED 898 static inline int pte_unused(pte_t pte) 899 { 900 return pte_val(pte) & _PAGE_UNUSED; 901 } 902 903 /* 904 * Extract the pgprot value from the given pte while at the same time making it 905 * usable for kernel address space mappings where fault driven dirty and 906 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 907 * must not be set. 908 */ 909 static inline pgprot_t pte_pgprot(pte_t pte) 910 { 911 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 912 913 if (pte_write(pte)) 914 pte_flags |= pgprot_val(PAGE_KERNEL); 915 else 916 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 917 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 918 919 return __pgprot(pte_flags); 920 } 921 922 /* 923 * pgd/pmd/pte modification functions 924 */ 925 926 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 927 { 928 WRITE_ONCE(*pgdp, pgd); 929 } 930 931 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 932 { 933 WRITE_ONCE(*p4dp, p4d); 934 } 935 936 static inline void set_pud(pud_t *pudp, pud_t pud) 937 { 938 WRITE_ONCE(*pudp, pud); 939 } 940 941 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 942 { 943 WRITE_ONCE(*pmdp, pmd); 944 } 945 946 static inline void set_pte(pte_t *ptep, pte_t pte) 947 { 948 WRITE_ONCE(*ptep, pte); 949 } 950 951 static inline void pgd_clear(pgd_t *pgd) 952 { 953 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 954 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 955 } 956 957 static inline void p4d_clear(p4d_t *p4d) 958 { 959 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 960 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 961 } 962 963 static inline void pud_clear(pud_t *pud) 964 { 965 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 966 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 967 } 968 969 static inline void pmd_clear(pmd_t *pmdp) 970 { 971 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 972 } 973 974 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 975 { 976 set_pte(ptep, __pte(_PAGE_INVALID)); 977 } 978 979 /* 980 * The following pte modification functions only work if 981 * pte_present() is true. Undefined behaviour if not.. 982 */ 983 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 984 { 985 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 986 pte = set_pte_bit(pte, newprot); 987 /* 988 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 989 * has the invalid bit set, clear it again for readable, young pages 990 */ 991 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 992 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 993 /* 994 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 995 * protection bit set, clear it again for writable, dirty pages 996 */ 997 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 998 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 999 return pte; 1000 } 1001 1002 static inline pte_t pte_wrprotect(pte_t pte) 1003 { 1004 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1005 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1006 } 1007 1008 static inline pte_t pte_mkwrite(pte_t pte) 1009 { 1010 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1011 if (pte_val(pte) & _PAGE_DIRTY) 1012 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1013 return pte; 1014 } 1015 1016 static inline pte_t pte_mkclean(pte_t pte) 1017 { 1018 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1019 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1020 } 1021 1022 static inline pte_t pte_mkdirty(pte_t pte) 1023 { 1024 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1025 if (pte_val(pte) & _PAGE_WRITE) 1026 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1027 return pte; 1028 } 1029 1030 static inline pte_t pte_mkold(pte_t pte) 1031 { 1032 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1033 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1034 } 1035 1036 static inline pte_t pte_mkyoung(pte_t pte) 1037 { 1038 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1039 if (pte_val(pte) & _PAGE_READ) 1040 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1041 return pte; 1042 } 1043 1044 static inline pte_t pte_mkspecial(pte_t pte) 1045 { 1046 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1047 } 1048 1049 #ifdef CONFIG_HUGETLB_PAGE 1050 static inline pte_t pte_mkhuge(pte_t pte) 1051 { 1052 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1053 } 1054 #endif 1055 1056 #define IPTE_GLOBAL 0 1057 #define IPTE_LOCAL 1 1058 1059 #define IPTE_NODAT 0x400 1060 #define IPTE_GUEST_ASCE 0x800 1061 1062 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1063 unsigned long opt, unsigned long asce, 1064 int local) 1065 { 1066 unsigned long pto; 1067 1068 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1069 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1070 : "+m" (*ptep) 1071 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1072 [asce] "a" (asce), [m4] "i" (local)); 1073 } 1074 1075 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1076 unsigned long opt, unsigned long asce, 1077 int local) 1078 { 1079 unsigned long pto = __pa(ptep); 1080 1081 if (__builtin_constant_p(opt) && opt == 0) { 1082 /* Invalidation + TLB flush for the pte */ 1083 asm volatile( 1084 " ipte %[r1],%[r2],0,%[m4]" 1085 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1086 [m4] "i" (local)); 1087 return; 1088 } 1089 1090 /* Invalidate ptes with options + TLB flush of the ptes */ 1091 opt = opt | (asce & _ASCE_ORIGIN); 1092 asm volatile( 1093 " ipte %[r1],%[r2],%[r3],%[m4]" 1094 : [r2] "+a" (address), [r3] "+a" (opt) 1095 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1096 } 1097 1098 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1099 pte_t *ptep, int local) 1100 { 1101 unsigned long pto = __pa(ptep); 1102 1103 /* Invalidate a range of ptes + TLB flush of the ptes */ 1104 do { 1105 asm volatile( 1106 " ipte %[r1],%[r2],%[r3],%[m4]" 1107 : [r2] "+a" (address), [r3] "+a" (nr) 1108 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1109 } while (nr != 255); 1110 } 1111 1112 /* 1113 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1114 * both clear the TLB for the unmapped pte. The reason is that 1115 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1116 * to modify an active pte. The sequence is 1117 * 1) ptep_get_and_clear 1118 * 2) set_pte_at 1119 * 3) flush_tlb_range 1120 * On s390 the tlb needs to get flushed with the modification of the pte 1121 * if the pte is active. The only way how this can be implemented is to 1122 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1123 * is a nop. 1124 */ 1125 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1126 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1127 1128 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1129 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1130 unsigned long addr, pte_t *ptep) 1131 { 1132 pte_t pte = *ptep; 1133 1134 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1135 return pte_young(pte); 1136 } 1137 1138 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1139 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1140 unsigned long address, pte_t *ptep) 1141 { 1142 return ptep_test_and_clear_young(vma, address, ptep); 1143 } 1144 1145 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1146 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1147 unsigned long addr, pte_t *ptep) 1148 { 1149 pte_t res; 1150 1151 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1152 /* At this point the reference through the mapping is still present */ 1153 if (mm_is_protected(mm) && pte_present(res)) 1154 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1155 return res; 1156 } 1157 1158 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1159 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1160 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1161 pte_t *, pte_t, pte_t); 1162 1163 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1164 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1165 unsigned long addr, pte_t *ptep) 1166 { 1167 pte_t res; 1168 1169 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1170 /* At this point the reference through the mapping is still present */ 1171 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1172 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1173 return res; 1174 } 1175 1176 /* 1177 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1178 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1179 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1180 * cannot be accessed while the batched unmap is running. In this case 1181 * full==1 and a simple pte_clear is enough. See tlb.h. 1182 */ 1183 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1184 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1185 unsigned long addr, 1186 pte_t *ptep, int full) 1187 { 1188 pte_t res; 1189 1190 if (full) { 1191 res = *ptep; 1192 set_pte(ptep, __pte(_PAGE_INVALID)); 1193 } else { 1194 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1195 } 1196 /* Nothing to do */ 1197 if (!mm_is_protected(mm) || !pte_present(res)) 1198 return res; 1199 /* 1200 * At this point the reference through the mapping is still present. 1201 * The notifier should have destroyed all protected vCPUs at this 1202 * point, so the destroy should be successful. 1203 */ 1204 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1205 return res; 1206 /* 1207 * If something went wrong and the page could not be destroyed, or 1208 * if this is not a mm teardown, the slower export is used as 1209 * fallback instead. 1210 */ 1211 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1212 return res; 1213 } 1214 1215 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1216 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1217 unsigned long addr, pte_t *ptep) 1218 { 1219 pte_t pte = *ptep; 1220 1221 if (pte_write(pte)) 1222 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1223 } 1224 1225 /* 1226 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1227 * bits in the comparison. Those might change e.g. because of dirty and young 1228 * tracking. 1229 */ 1230 static inline int pte_allow_rdp(pte_t old, pte_t new) 1231 { 1232 /* 1233 * Only allow changes from RO to RW 1234 */ 1235 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1236 return 0; 1237 1238 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1239 } 1240 1241 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1242 unsigned long address) 1243 { 1244 /* 1245 * RDP might not have propagated the PTE protection reset to all CPUs, 1246 * so there could be spurious TLB protection faults. 1247 * NOTE: This will also be called when a racing pagetable update on 1248 * another thread already installed the correct PTE. Both cases cannot 1249 * really be distinguished. 1250 * Therefore, only do the local TLB flush when RDP can be used, to avoid 1251 * unnecessary overhead. 1252 */ 1253 if (MACHINE_HAS_RDP) 1254 asm volatile("ptlb" : : : "memory"); 1255 } 1256 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1257 1258 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1259 pte_t new); 1260 1261 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1262 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1263 unsigned long addr, pte_t *ptep, 1264 pte_t entry, int dirty) 1265 { 1266 if (pte_same(*ptep, entry)) 1267 return 0; 1268 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1269 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1270 else 1271 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1272 return 1; 1273 } 1274 1275 /* 1276 * Additional functions to handle KVM guest page tables 1277 */ 1278 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1279 pte_t *ptep, pte_t entry); 1280 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1281 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1282 pte_t *ptep, unsigned long bits); 1283 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1284 pte_t *ptep, int prot, unsigned long bit); 1285 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1286 pte_t *ptep , int reset); 1287 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1288 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1289 pte_t *sptep, pte_t *tptep, pte_t pte); 1290 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1291 1292 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1293 pte_t *ptep); 1294 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1295 unsigned char key, bool nq); 1296 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1297 unsigned char key, unsigned char *oldkey, 1298 bool nq, bool mr, bool mc); 1299 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1300 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1301 unsigned char *key); 1302 1303 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1304 unsigned long bits, unsigned long value); 1305 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1306 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1307 unsigned long *oldpte, unsigned long *oldpgste); 1308 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1309 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1310 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1311 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1312 1313 #define pgprot_writecombine pgprot_writecombine 1314 pgprot_t pgprot_writecombine(pgprot_t prot); 1315 1316 #define pgprot_writethrough pgprot_writethrough 1317 pgprot_t pgprot_writethrough(pgprot_t prot); 1318 1319 /* 1320 * Certain architectures need to do special things when PTEs 1321 * within a page table are directly modified. Thus, the following 1322 * hook is made available. 1323 */ 1324 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 1325 pte_t *ptep, pte_t entry) 1326 { 1327 if (pte_present(entry)) 1328 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1329 if (mm_has_pgste(mm)) 1330 ptep_set_pte_at(mm, addr, ptep, entry); 1331 else 1332 set_pte(ptep, entry); 1333 } 1334 1335 /* 1336 * Conversion functions: convert a page and protection to a page entry, 1337 * and a page entry and page directory to the page they refer to. 1338 */ 1339 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1340 { 1341 pte_t __pte; 1342 1343 __pte = __pte(physpage | pgprot_val(pgprot)); 1344 if (!MACHINE_HAS_NX) 1345 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1346 return pte_mkyoung(__pte); 1347 } 1348 1349 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1350 { 1351 unsigned long physpage = page_to_phys(page); 1352 pte_t __pte = mk_pte_phys(physpage, pgprot); 1353 1354 if (pte_write(__pte) && PageDirty(page)) 1355 __pte = pte_mkdirty(__pte); 1356 return __pte; 1357 } 1358 1359 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1360 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1361 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1362 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1363 1364 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1365 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1366 1367 static inline unsigned long pmd_deref(pmd_t pmd) 1368 { 1369 unsigned long origin_mask; 1370 1371 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1372 if (pmd_large(pmd)) 1373 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1374 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1375 } 1376 1377 static inline unsigned long pmd_pfn(pmd_t pmd) 1378 { 1379 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1380 } 1381 1382 static inline unsigned long pud_deref(pud_t pud) 1383 { 1384 unsigned long origin_mask; 1385 1386 origin_mask = _REGION_ENTRY_ORIGIN; 1387 if (pud_large(pud)) 1388 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1389 return (unsigned long)__va(pud_val(pud) & origin_mask); 1390 } 1391 1392 static inline unsigned long pud_pfn(pud_t pud) 1393 { 1394 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1395 } 1396 1397 /* 1398 * The pgd_offset function *always* adds the index for the top-level 1399 * region/segment table. This is done to get a sequence like the 1400 * following to work: 1401 * pgdp = pgd_offset(current->mm, addr); 1402 * pgd = READ_ONCE(*pgdp); 1403 * p4dp = p4d_offset(&pgd, addr); 1404 * ... 1405 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1406 * only add an index if they dereferenced the pointer. 1407 */ 1408 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1409 { 1410 unsigned long rste; 1411 unsigned int shift; 1412 1413 /* Get the first entry of the top level table */ 1414 rste = pgd_val(*pgd); 1415 /* Pick up the shift from the table type of the first entry */ 1416 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1417 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1418 } 1419 1420 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1421 1422 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1423 { 1424 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1425 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1426 return (p4d_t *) pgdp; 1427 } 1428 #define p4d_offset_lockless p4d_offset_lockless 1429 1430 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1431 { 1432 return p4d_offset_lockless(pgdp, *pgdp, address); 1433 } 1434 1435 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1436 { 1437 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1438 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1439 return (pud_t *) p4dp; 1440 } 1441 #define pud_offset_lockless pud_offset_lockless 1442 1443 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1444 { 1445 return pud_offset_lockless(p4dp, *p4dp, address); 1446 } 1447 #define pud_offset pud_offset 1448 1449 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1450 { 1451 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1452 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1453 return (pmd_t *) pudp; 1454 } 1455 #define pmd_offset_lockless pmd_offset_lockless 1456 1457 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1458 { 1459 return pmd_offset_lockless(pudp, *pudp, address); 1460 } 1461 #define pmd_offset pmd_offset 1462 1463 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1464 { 1465 return (unsigned long) pmd_deref(pmd); 1466 } 1467 1468 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1469 { 1470 return end <= current->mm->context.asce_limit; 1471 } 1472 #define gup_fast_permitted gup_fast_permitted 1473 1474 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1475 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1476 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1477 1478 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1479 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1480 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1481 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1482 1483 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1484 { 1485 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1486 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1487 } 1488 1489 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1490 { 1491 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1492 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1493 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1494 return pmd; 1495 } 1496 1497 static inline pmd_t pmd_mkclean(pmd_t pmd) 1498 { 1499 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1500 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1501 } 1502 1503 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1504 { 1505 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1506 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1507 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1508 return pmd; 1509 } 1510 1511 static inline pud_t pud_wrprotect(pud_t pud) 1512 { 1513 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1514 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1515 } 1516 1517 static inline pud_t pud_mkwrite(pud_t pud) 1518 { 1519 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1520 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1521 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1522 return pud; 1523 } 1524 1525 static inline pud_t pud_mkclean(pud_t pud) 1526 { 1527 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1528 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1529 } 1530 1531 static inline pud_t pud_mkdirty(pud_t pud) 1532 { 1533 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1534 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1535 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1536 return pud; 1537 } 1538 1539 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1540 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1541 { 1542 /* 1543 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1544 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1545 */ 1546 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1547 return pgprot_val(SEGMENT_NONE); 1548 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1549 return pgprot_val(SEGMENT_RO); 1550 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1551 return pgprot_val(SEGMENT_RX); 1552 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1553 return pgprot_val(SEGMENT_RW); 1554 return pgprot_val(SEGMENT_RWX); 1555 } 1556 1557 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1558 { 1559 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1560 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1561 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1562 return pmd; 1563 } 1564 1565 static inline pmd_t pmd_mkold(pmd_t pmd) 1566 { 1567 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1568 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1569 } 1570 1571 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1572 { 1573 unsigned long mask; 1574 1575 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1576 mask |= _SEGMENT_ENTRY_DIRTY; 1577 mask |= _SEGMENT_ENTRY_YOUNG; 1578 mask |= _SEGMENT_ENTRY_LARGE; 1579 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1580 pmd = __pmd(pmd_val(pmd) & mask); 1581 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1582 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1583 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1584 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1585 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1586 return pmd; 1587 } 1588 1589 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1590 { 1591 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1592 } 1593 1594 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1595 1596 static inline void __pmdp_csp(pmd_t *pmdp) 1597 { 1598 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1599 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1600 } 1601 1602 #define IDTE_GLOBAL 0 1603 #define IDTE_LOCAL 1 1604 1605 #define IDTE_PTOA 0x0800 1606 #define IDTE_NODAT 0x1000 1607 #define IDTE_GUEST_ASCE 0x2000 1608 1609 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1610 unsigned long opt, unsigned long asce, 1611 int local) 1612 { 1613 unsigned long sto; 1614 1615 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1616 if (__builtin_constant_p(opt) && opt == 0) { 1617 /* flush without guest asce */ 1618 asm volatile( 1619 " idte %[r1],0,%[r2],%[m4]" 1620 : "+m" (*pmdp) 1621 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1622 [m4] "i" (local) 1623 : "cc" ); 1624 } else { 1625 /* flush with guest asce */ 1626 asm volatile( 1627 " idte %[r1],%[r3],%[r2],%[m4]" 1628 : "+m" (*pmdp) 1629 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1630 [r3] "a" (asce), [m4] "i" (local) 1631 : "cc" ); 1632 } 1633 } 1634 1635 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1636 unsigned long opt, unsigned long asce, 1637 int local) 1638 { 1639 unsigned long r3o; 1640 1641 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1642 r3o |= _ASCE_TYPE_REGION3; 1643 if (__builtin_constant_p(opt) && opt == 0) { 1644 /* flush without guest asce */ 1645 asm volatile( 1646 " idte %[r1],0,%[r2],%[m4]" 1647 : "+m" (*pudp) 1648 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1649 [m4] "i" (local) 1650 : "cc"); 1651 } else { 1652 /* flush with guest asce */ 1653 asm volatile( 1654 " idte %[r1],%[r3],%[r2],%[m4]" 1655 : "+m" (*pudp) 1656 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1657 [r3] "a" (asce), [m4] "i" (local) 1658 : "cc" ); 1659 } 1660 } 1661 1662 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1663 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1664 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1665 1666 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1667 1668 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1669 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1670 pgtable_t pgtable); 1671 1672 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1673 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1674 1675 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1676 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1677 unsigned long addr, pmd_t *pmdp, 1678 pmd_t entry, int dirty) 1679 { 1680 VM_BUG_ON(addr & ~HPAGE_MASK); 1681 1682 entry = pmd_mkyoung(entry); 1683 if (dirty) 1684 entry = pmd_mkdirty(entry); 1685 if (pmd_val(*pmdp) == pmd_val(entry)) 1686 return 0; 1687 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1688 return 1; 1689 } 1690 1691 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1692 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1693 unsigned long addr, pmd_t *pmdp) 1694 { 1695 pmd_t pmd = *pmdp; 1696 1697 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1698 return pmd_young(pmd); 1699 } 1700 1701 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1702 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1703 unsigned long addr, pmd_t *pmdp) 1704 { 1705 VM_BUG_ON(addr & ~HPAGE_MASK); 1706 return pmdp_test_and_clear_young(vma, addr, pmdp); 1707 } 1708 1709 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1710 pmd_t *pmdp, pmd_t entry) 1711 { 1712 if (!MACHINE_HAS_NX) 1713 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1714 set_pmd(pmdp, entry); 1715 } 1716 1717 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1718 { 1719 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1720 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1721 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1722 } 1723 1724 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1725 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1726 unsigned long addr, pmd_t *pmdp) 1727 { 1728 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1729 } 1730 1731 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1732 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1733 unsigned long addr, 1734 pmd_t *pmdp, int full) 1735 { 1736 if (full) { 1737 pmd_t pmd = *pmdp; 1738 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1739 return pmd; 1740 } 1741 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1742 } 1743 1744 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1745 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1746 unsigned long addr, pmd_t *pmdp) 1747 { 1748 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1749 } 1750 1751 #define __HAVE_ARCH_PMDP_INVALIDATE 1752 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1753 unsigned long addr, pmd_t *pmdp) 1754 { 1755 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1756 1757 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1758 } 1759 1760 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1761 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1762 unsigned long addr, pmd_t *pmdp) 1763 { 1764 pmd_t pmd = *pmdp; 1765 1766 if (pmd_write(pmd)) 1767 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1768 } 1769 1770 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1771 unsigned long address, 1772 pmd_t *pmdp) 1773 { 1774 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1775 } 1776 #define pmdp_collapse_flush pmdp_collapse_flush 1777 1778 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1779 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1780 1781 static inline int pmd_trans_huge(pmd_t pmd) 1782 { 1783 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1784 } 1785 1786 #define has_transparent_hugepage has_transparent_hugepage 1787 static inline int has_transparent_hugepage(void) 1788 { 1789 return MACHINE_HAS_EDAT1 ? 1 : 0; 1790 } 1791 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1792 1793 /* 1794 * 64 bit swap entry format: 1795 * A page-table entry has some bits we have to treat in a special way. 1796 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1797 * as invalid. 1798 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1799 * | offset |E11XX|type |S0| 1800 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1801 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1802 * 1803 * Bits 0-51 store the offset. 1804 * Bit 52 (E) is used to remember PG_anon_exclusive. 1805 * Bits 57-61 store the type. 1806 * Bit 62 (S) is used for softdirty tracking. 1807 * Bits 55 and 56 (X) are unused. 1808 */ 1809 1810 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1811 #define __SWP_OFFSET_SHIFT 12 1812 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1813 #define __SWP_TYPE_SHIFT 2 1814 1815 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1816 { 1817 unsigned long pteval; 1818 1819 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1820 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1821 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1822 return __pte(pteval); 1823 } 1824 1825 static inline unsigned long __swp_type(swp_entry_t entry) 1826 { 1827 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1828 } 1829 1830 static inline unsigned long __swp_offset(swp_entry_t entry) 1831 { 1832 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1833 } 1834 1835 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1836 { 1837 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1838 } 1839 1840 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1841 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1842 1843 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1844 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1845 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1846 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1847 extern void vmem_unmap_4k_page(unsigned long addr); 1848 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1849 extern int s390_enable_sie(void); 1850 extern int s390_enable_skey(void); 1851 extern void s390_reset_cmma(struct mm_struct *mm); 1852 1853 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1854 #define HAVE_ARCH_UNMAPPED_AREA 1855 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1856 1857 #define pmd_pgtable(pmd) \ 1858 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1859 1860 #endif /* _S390_PAGE_H */ 1861