1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. For 16 * s390 31 bit we "fold" the mid level into the top-level page table, so 17 * that we physically have the same two-level page table as the s390 mmu 18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels 19 * the hardware provides (region first and region second tables are not 20 * used). 21 * 22 * The "pgd_xxx()" functions are trivial for a folded two-level 23 * setup: the pgd is never bad, and a pmd always exists (as it's folded 24 * into the pgd entry) 25 * 26 * This file contains the functions and defines necessary to modify and use 27 * the S390 page table tree. 28 */ 29 #ifndef __ASSEMBLY__ 30 #include <linux/sched.h> 31 #include <linux/mm_types.h> 32 #include <linux/page-flags.h> 33 #include <asm/bug.h> 34 #include <asm/page.h> 35 36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 37 extern void paging_init(void); 38 extern void vmem_map_init(void); 39 40 /* 41 * The S390 doesn't have any external MMU info: the kernel page 42 * tables contain all the necessary information. 43 */ 44 #define update_mmu_cache(vma, address, ptep) do { } while (0) 45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 46 47 /* 48 * ZERO_PAGE is a global shared page that is always zero; used 49 * for zero-mapped memory areas etc.. 50 */ 51 52 extern unsigned long empty_zero_page; 53 extern unsigned long zero_page_mask; 54 55 #define ZERO_PAGE(vaddr) \ 56 (virt_to_page((void *)(empty_zero_page + \ 57 (((unsigned long)(vaddr)) &zero_page_mask)))) 58 #define __HAVE_COLOR_ZERO_PAGE 59 60 /* TODO: s390 cannot support io_remap_pfn_range... */ 61 #endif /* !__ASSEMBLY__ */ 62 63 /* 64 * PMD_SHIFT determines the size of the area a second-level page 65 * table can map 66 * PGDIR_SHIFT determines what a third-level page table entry can map 67 */ 68 #ifndef CONFIG_64BIT 69 # define PMD_SHIFT 20 70 # define PUD_SHIFT 20 71 # define PGDIR_SHIFT 20 72 #else /* CONFIG_64BIT */ 73 # define PMD_SHIFT 20 74 # define PUD_SHIFT 31 75 # define PGDIR_SHIFT 42 76 #endif /* CONFIG_64BIT */ 77 78 #define PMD_SIZE (1UL << PMD_SHIFT) 79 #define PMD_MASK (~(PMD_SIZE-1)) 80 #define PUD_SIZE (1UL << PUD_SHIFT) 81 #define PUD_MASK (~(PUD_SIZE-1)) 82 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 83 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 84 85 /* 86 * entries per page directory level: the S390 is two-level, so 87 * we don't really have any PMD directory physically. 88 * for S390 segment-table entries are combined to one PGD 89 * that leads to 1024 pte per pgd 90 */ 91 #define PTRS_PER_PTE 256 92 #ifndef CONFIG_64BIT 93 #define PTRS_PER_PMD 1 94 #define PTRS_PER_PUD 1 95 #else /* CONFIG_64BIT */ 96 #define PTRS_PER_PMD 2048 97 #define PTRS_PER_PUD 2048 98 #endif /* CONFIG_64BIT */ 99 #define PTRS_PER_PGD 2048 100 101 #define FIRST_USER_ADDRESS 0 102 103 #define pte_ERROR(e) \ 104 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 105 #define pmd_ERROR(e) \ 106 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 107 #define pud_ERROR(e) \ 108 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 109 #define pgd_ERROR(e) \ 110 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 111 112 #ifndef __ASSEMBLY__ 113 /* 114 * The vmalloc and module area will always be on the topmost area of the kernel 115 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. 116 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 117 * modules will reside. That makes sure that inter module branches always 118 * happen without trampolines and in addition the placement within a 2GB frame 119 * is branch prediction unit friendly. 120 */ 121 extern unsigned long VMALLOC_START; 122 extern unsigned long VMALLOC_END; 123 extern struct page *vmemmap; 124 125 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 126 127 #ifdef CONFIG_64BIT 128 extern unsigned long MODULES_VADDR; 129 extern unsigned long MODULES_END; 130 #define MODULES_VADDR MODULES_VADDR 131 #define MODULES_END MODULES_END 132 #define MODULES_LEN (1UL << 31) 133 #endif 134 135 /* 136 * A 31 bit pagetable entry of S390 has following format: 137 * | PFRA | | OS | 138 * 0 0IP0 139 * 00000000001111111111222222222233 140 * 01234567890123456789012345678901 141 * 142 * I Page-Invalid Bit: Page is not available for address-translation 143 * P Page-Protection Bit: Store access not possible for page 144 * 145 * A 31 bit segmenttable entry of S390 has following format: 146 * | P-table origin | |PTL 147 * 0 IC 148 * 00000000001111111111222222222233 149 * 01234567890123456789012345678901 150 * 151 * I Segment-Invalid Bit: Segment is not available for address-translation 152 * C Common-Segment Bit: Segment is not private (PoP 3-30) 153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) 154 * 155 * The 31 bit segmenttable origin of S390 has following format: 156 * 157 * |S-table origin | | STL | 158 * X **GPS 159 * 00000000001111111111222222222233 160 * 01234567890123456789012345678901 161 * 162 * X Space-Switch event: 163 * G Segment-Invalid Bit: * 164 * P Private-Space Bit: Segment is not private (PoP 3-30) 165 * S Storage-Alteration: 166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) 167 * 168 * A 64 bit pagetable entry of S390 has following format: 169 * | PFRA |0IPC| OS | 170 * 0000000000111111111122222222223333333333444444444455555555556666 171 * 0123456789012345678901234567890123456789012345678901234567890123 172 * 173 * I Page-Invalid Bit: Page is not available for address-translation 174 * P Page-Protection Bit: Store access not possible for page 175 * C Change-bit override: HW is not required to set change bit 176 * 177 * A 64 bit segmenttable entry of S390 has following format: 178 * | P-table origin | TT 179 * 0000000000111111111122222222223333333333444444444455555555556666 180 * 0123456789012345678901234567890123456789012345678901234567890123 181 * 182 * I Segment-Invalid Bit: Segment is not available for address-translation 183 * C Common-Segment Bit: Segment is not private (PoP 3-30) 184 * P Page-Protection Bit: Store access not possible for page 185 * TT Type 00 186 * 187 * A 64 bit region table entry of S390 has following format: 188 * | S-table origin | TF TTTL 189 * 0000000000111111111122222222223333333333444444444455555555556666 190 * 0123456789012345678901234567890123456789012345678901234567890123 191 * 192 * I Segment-Invalid Bit: Segment is not available for address-translation 193 * TT Type 01 194 * TF 195 * TL Table length 196 * 197 * The 64 bit regiontable origin of S390 has following format: 198 * | region table origon | DTTL 199 * 0000000000111111111122222222223333333333444444444455555555556666 200 * 0123456789012345678901234567890123456789012345678901234567890123 201 * 202 * X Space-Switch event: 203 * G Segment-Invalid Bit: 204 * P Private-Space Bit: 205 * S Storage-Alteration: 206 * R Real space 207 * TL Table-Length: 208 * 209 * A storage key has the following format: 210 * | ACC |F|R|C|0| 211 * 0 3 4 5 6 7 212 * ACC: access key 213 * F : fetch protection bit 214 * R : referenced bit 215 * C : changed bit 216 */ 217 218 /* Hardware bits in the page table entry */ 219 #define _PAGE_CO 0x100 /* HW Change-bit override */ 220 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 221 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 222 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 223 224 /* Software bits in the page table entry */ 225 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 226 #define _PAGE_TYPE 0x002 /* SW pte type bit */ 227 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 228 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 229 #define _PAGE_READ 0x010 /* SW pte read bit */ 230 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 231 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 232 #define __HAVE_ARCH_PTE_SPECIAL 233 234 /* Set of bits not changed in pte_modify */ 235 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \ 236 _PAGE_DIRTY | _PAGE_YOUNG) 237 238 /* 239 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the 240 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit 241 * is used to distinguish present from not-present ptes. It is changed only 242 * with the page table lock held. 243 * 244 * The following table gives the different possible bit combinations for 245 * the pte hardware and software bits in the last 12 bits of a pte: 246 * 247 * 842100000000 248 * 000084210000 249 * 000000008421 250 * .IR...wrdytp 251 * empty .10...000000 252 * swap .10...xxxx10 253 * file .11...xxxxx0 254 * prot-none, clean, old .11...000001 255 * prot-none, clean, young .11...000101 256 * prot-none, dirty, old .10...001001 257 * prot-none, dirty, young .10...001101 258 * read-only, clean, old .11...010001 259 * read-only, clean, young .01...010101 260 * read-only, dirty, old .11...011001 261 * read-only, dirty, young .01...011101 262 * read-write, clean, old .11...110001 263 * read-write, clean, young .01...110101 264 * read-write, dirty, old .10...111001 265 * read-write, dirty, young .00...111101 266 * 267 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001 268 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400 269 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600 270 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402 271 */ 272 273 #ifndef CONFIG_64BIT 274 275 /* Bits in the segment table address-space-control-element */ 276 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ 277 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ 278 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 279 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 280 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ 281 282 /* Bits in the segment table entry */ 283 #define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */ 284 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ 285 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ 286 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 287 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ 288 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ 289 #define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_PROTECT 290 291 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) 292 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 293 294 /* 295 * Segment table entry encoding (I = invalid, R = read-only bit): 296 * ..R...I..... 297 * prot-none ..1...1..... 298 * read-only ..1...0..... 299 * read-write ..0...0..... 300 * empty ..0...1..... 301 */ 302 303 /* Page status table bits for virtualization */ 304 #define PGSTE_ACC_BITS 0xf0000000UL 305 #define PGSTE_FP_BIT 0x08000000UL 306 #define PGSTE_PCL_BIT 0x00800000UL 307 #define PGSTE_HR_BIT 0x00400000UL 308 #define PGSTE_HC_BIT 0x00200000UL 309 #define PGSTE_GR_BIT 0x00040000UL 310 #define PGSTE_GC_BIT 0x00020000UL 311 #define PGSTE_IN_BIT 0x00008000UL /* IPTE notify bit */ 312 313 #else /* CONFIG_64BIT */ 314 315 /* Bits in the segment/region table address-space-control-element */ 316 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 317 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 318 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 319 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 320 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 321 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 322 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 323 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 324 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 325 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 326 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 327 328 /* Bits in the region table entry */ 329 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 330 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 331 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 332 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 333 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 334 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 335 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 336 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 337 338 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 339 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 340 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 341 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 342 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 343 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 344 345 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ 346 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ 347 #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ 348 349 /* Bits in the segment table entry */ 350 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 351 #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff1ff33UL 352 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 353 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 354 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ 355 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 356 357 #define _SEGMENT_ENTRY (0) 358 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 359 360 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ 361 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ 362 #define _SEGMENT_ENTRY_SPLIT 0x001 /* THP splitting bit */ 363 #define _SEGMENT_ENTRY_YOUNG 0x002 /* SW segment young bit */ 364 #define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_YOUNG 365 366 /* 367 * Segment table entry encoding (R = read-only, I = invalid, y = young bit): 368 * ..R...I...y. 369 * prot-none, old ..0...1...1. 370 * prot-none, young ..1...1...1. 371 * read-only, old ..1...1...0. 372 * read-only, young ..1...0...1. 373 * read-write, old ..0...1...0. 374 * read-write, young ..0...0...1. 375 * The segment table origin is used to distinguish empty (origin==0) from 376 * read-write, old segment table entries (origin!=0) 377 */ 378 379 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ 380 381 /* Set of bits not changed in pmd_modify */ 382 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ 383 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) 384 385 /* Page status table bits for virtualization */ 386 #define PGSTE_ACC_BITS 0xf000000000000000UL 387 #define PGSTE_FP_BIT 0x0800000000000000UL 388 #define PGSTE_PCL_BIT 0x0080000000000000UL 389 #define PGSTE_HR_BIT 0x0040000000000000UL 390 #define PGSTE_HC_BIT 0x0020000000000000UL 391 #define PGSTE_GR_BIT 0x0004000000000000UL 392 #define PGSTE_GC_BIT 0x0002000000000000UL 393 #define PGSTE_IN_BIT 0x0000800000000000UL /* IPTE notify bit */ 394 395 #endif /* CONFIG_64BIT */ 396 397 /* 398 * A user page table pointer has the space-switch-event bit, the 399 * private-space-control bit and the storage-alteration-event-control 400 * bit set. A kernel page table pointer doesn't need them. 401 */ 402 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 403 _ASCE_ALT_EVENT) 404 405 /* 406 * Page protection definitions. 407 */ 408 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) 409 #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 410 _PAGE_INVALID | _PAGE_PROTECT) 411 #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 412 _PAGE_INVALID | _PAGE_PROTECT) 413 414 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 415 _PAGE_YOUNG | _PAGE_DIRTY) 416 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 417 _PAGE_YOUNG | _PAGE_DIRTY) 418 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 419 _PAGE_PROTECT) 420 421 /* 422 * On s390 the page table entry has an invalid bit and a read-only bit. 423 * Read permission implies execute permission and write permission 424 * implies read permission. 425 */ 426 /*xwr*/ 427 #define __P000 PAGE_NONE 428 #define __P001 PAGE_READ 429 #define __P010 PAGE_READ 430 #define __P011 PAGE_READ 431 #define __P100 PAGE_READ 432 #define __P101 PAGE_READ 433 #define __P110 PAGE_READ 434 #define __P111 PAGE_READ 435 436 #define __S000 PAGE_NONE 437 #define __S001 PAGE_READ 438 #define __S010 PAGE_WRITE 439 #define __S011 PAGE_WRITE 440 #define __S100 PAGE_READ 441 #define __S101 PAGE_READ 442 #define __S110 PAGE_WRITE 443 #define __S111 PAGE_WRITE 444 445 /* 446 * Segment entry (large page) protection definitions. 447 */ 448 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 449 _SEGMENT_ENTRY_NONE) 450 #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_INVALID | \ 451 _SEGMENT_ENTRY_PROTECT) 452 #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_INVALID) 453 454 static inline int mm_has_pgste(struct mm_struct *mm) 455 { 456 #ifdef CONFIG_PGSTE 457 if (unlikely(mm->context.has_pgste)) 458 return 1; 459 #endif 460 return 0; 461 } 462 /* 463 * pgd/pmd/pte query functions 464 */ 465 #ifndef CONFIG_64BIT 466 467 static inline int pgd_present(pgd_t pgd) { return 1; } 468 static inline int pgd_none(pgd_t pgd) { return 0; } 469 static inline int pgd_bad(pgd_t pgd) { return 0; } 470 471 static inline int pud_present(pud_t pud) { return 1; } 472 static inline int pud_none(pud_t pud) { return 0; } 473 static inline int pud_large(pud_t pud) { return 0; } 474 static inline int pud_bad(pud_t pud) { return 0; } 475 476 #else /* CONFIG_64BIT */ 477 478 static inline int pgd_present(pgd_t pgd) 479 { 480 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 481 return 1; 482 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 483 } 484 485 static inline int pgd_none(pgd_t pgd) 486 { 487 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 488 return 0; 489 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 490 } 491 492 static inline int pgd_bad(pgd_t pgd) 493 { 494 /* 495 * With dynamic page table levels the pgd can be a region table 496 * entry or a segment table entry. Check for the bit that are 497 * invalid for either table entry. 498 */ 499 unsigned long mask = 500 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & 501 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 502 return (pgd_val(pgd) & mask) != 0; 503 } 504 505 static inline int pud_present(pud_t pud) 506 { 507 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 508 return 1; 509 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 510 } 511 512 static inline int pud_none(pud_t pud) 513 { 514 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 515 return 0; 516 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; 517 } 518 519 static inline int pud_large(pud_t pud) 520 { 521 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 522 return 0; 523 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 524 } 525 526 static inline int pud_bad(pud_t pud) 527 { 528 /* 529 * With dynamic page table levels the pud can be a region table 530 * entry or a segment table entry. Check for the bit that are 531 * invalid for either table entry. 532 */ 533 unsigned long mask = 534 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & 535 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 536 return (pud_val(pud) & mask) != 0; 537 } 538 539 #endif /* CONFIG_64BIT */ 540 541 static inline int pmd_present(pmd_t pmd) 542 { 543 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; 544 } 545 546 static inline int pmd_none(pmd_t pmd) 547 { 548 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; 549 } 550 551 static inline int pmd_large(pmd_t pmd) 552 { 553 #ifdef CONFIG_64BIT 554 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 555 #else 556 return 0; 557 #endif 558 } 559 560 static inline int pmd_prot_none(pmd_t pmd) 561 { 562 return (pmd_val(pmd) & _SEGMENT_ENTRY_INVALID) && 563 (pmd_val(pmd) & _SEGMENT_ENTRY_NONE); 564 } 565 566 static inline int pmd_bad(pmd_t pmd) 567 { 568 #ifdef CONFIG_64BIT 569 if (pmd_large(pmd)) 570 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; 571 #endif 572 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 573 } 574 575 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 576 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 577 unsigned long addr, pmd_t *pmdp); 578 579 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 580 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 581 unsigned long address, pmd_t *pmdp, 582 pmd_t entry, int dirty); 583 584 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 585 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 586 unsigned long address, pmd_t *pmdp); 587 588 #define __HAVE_ARCH_PMD_WRITE 589 static inline int pmd_write(pmd_t pmd) 590 { 591 if (pmd_prot_none(pmd)) 592 return 0; 593 return (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) == 0; 594 } 595 596 static inline int pmd_young(pmd_t pmd) 597 { 598 int young = 0; 599 #ifdef CONFIG_64BIT 600 if (pmd_prot_none(pmd)) 601 young = (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) != 0; 602 else 603 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 604 #endif 605 return young; 606 } 607 608 static inline int pte_present(pte_t pte) 609 { 610 /* Bit pattern: (pte & 0x001) == 0x001 */ 611 return (pte_val(pte) & _PAGE_PRESENT) != 0; 612 } 613 614 static inline int pte_none(pte_t pte) 615 { 616 /* Bit pattern: pte == 0x400 */ 617 return pte_val(pte) == _PAGE_INVALID; 618 } 619 620 static inline int pte_file(pte_t pte) 621 { 622 /* Bit pattern: (pte & 0x601) == 0x600 */ 623 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT)) 624 == (_PAGE_INVALID | _PAGE_PROTECT); 625 } 626 627 static inline int pte_special(pte_t pte) 628 { 629 return (pte_val(pte) & _PAGE_SPECIAL); 630 } 631 632 #define __HAVE_ARCH_PTE_SAME 633 static inline int pte_same(pte_t a, pte_t b) 634 { 635 return pte_val(a) == pte_val(b); 636 } 637 638 static inline pgste_t pgste_get_lock(pte_t *ptep) 639 { 640 unsigned long new = 0; 641 #ifdef CONFIG_PGSTE 642 unsigned long old; 643 644 preempt_disable(); 645 asm( 646 " lg %0,%2\n" 647 "0: lgr %1,%0\n" 648 " nihh %0,0xff7f\n" /* clear PCL bit in old */ 649 " oihh %1,0x0080\n" /* set PCL bit in new */ 650 " csg %0,%1,%2\n" 651 " jl 0b\n" 652 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 653 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); 654 #endif 655 return __pgste(new); 656 } 657 658 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 659 { 660 #ifdef CONFIG_PGSTE 661 asm( 662 " nihh %1,0xff7f\n" /* clear PCL bit */ 663 " stg %1,%0\n" 664 : "=Q" (ptep[PTRS_PER_PTE]) 665 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) 666 : "cc", "memory"); 667 preempt_enable(); 668 #endif 669 } 670 671 static inline pgste_t pgste_get(pte_t *ptep) 672 { 673 unsigned long pgste = 0; 674 #ifdef CONFIG_PGSTE 675 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); 676 #endif 677 return __pgste(pgste); 678 } 679 680 static inline void pgste_set(pte_t *ptep, pgste_t pgste) 681 { 682 #ifdef CONFIG_PGSTE 683 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; 684 #endif 685 } 686 687 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) 688 { 689 #ifdef CONFIG_PGSTE 690 unsigned long address, bits, skey; 691 692 if (pte_val(*ptep) & _PAGE_INVALID) 693 return pgste; 694 address = pte_val(*ptep) & PAGE_MASK; 695 skey = (unsigned long) page_get_storage_key(address); 696 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 697 if (!(pgste_val(pgste) & PGSTE_HC_BIT) && (bits & _PAGE_CHANGED)) { 698 /* Transfer dirty + referenced bit to host bits in pgste */ 699 pgste_val(pgste) |= bits << 52; 700 page_set_storage_key(address, skey ^ bits, 0); 701 } else if (!(pgste_val(pgste) & PGSTE_HR_BIT) && 702 (bits & _PAGE_REFERENCED)) { 703 /* Transfer referenced bit to host bit in pgste */ 704 pgste_val(pgste) |= PGSTE_HR_BIT; 705 page_reset_referenced(address); 706 } 707 /* Transfer page changed & referenced bit to guest bits in pgste */ 708 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ 709 /* Copy page access key and fetch protection bit to pgste */ 710 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); 711 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 712 #endif 713 return pgste; 714 715 } 716 717 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) 718 { 719 #ifdef CONFIG_PGSTE 720 if (pte_val(*ptep) & _PAGE_INVALID) 721 return pgste; 722 /* Get referenced bit from storage key */ 723 if (page_reset_referenced(pte_val(*ptep) & PAGE_MASK)) 724 pgste_val(pgste) |= PGSTE_HR_BIT | PGSTE_GR_BIT; 725 #endif 726 return pgste; 727 } 728 729 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry) 730 { 731 #ifdef CONFIG_PGSTE 732 unsigned long address; 733 unsigned long nkey; 734 735 if (pte_val(entry) & _PAGE_INVALID) 736 return; 737 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); 738 address = pte_val(entry) & PAGE_MASK; 739 /* 740 * Set page access key and fetch protection bit from pgste. 741 * The guest C/R information is still in the PGSTE, set real 742 * key C/R to 0. 743 */ 744 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; 745 page_set_storage_key(address, nkey, 0); 746 #endif 747 } 748 749 static inline void pgste_set_pte(pte_t *ptep, pte_t entry) 750 { 751 if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_WRITE)) { 752 /* 753 * Without enhanced suppression-on-protection force 754 * the dirty bit on for all writable ptes. 755 */ 756 pte_val(entry) |= _PAGE_DIRTY; 757 pte_val(entry) &= ~_PAGE_PROTECT; 758 } 759 *ptep = entry; 760 } 761 762 /** 763 * struct gmap_struct - guest address space 764 * @mm: pointer to the parent mm_struct 765 * @table: pointer to the page directory 766 * @asce: address space control element for gmap page table 767 * @crst_list: list of all crst tables used in the guest address space 768 */ 769 struct gmap { 770 struct list_head list; 771 struct mm_struct *mm; 772 unsigned long *table; 773 unsigned long asce; 774 void *private; 775 struct list_head crst_list; 776 }; 777 778 /** 779 * struct gmap_rmap - reverse mapping for segment table entries 780 * @gmap: pointer to the gmap_struct 781 * @entry: pointer to a segment table entry 782 * @vmaddr: virtual address in the guest address space 783 */ 784 struct gmap_rmap { 785 struct list_head list; 786 struct gmap *gmap; 787 unsigned long *entry; 788 unsigned long vmaddr; 789 }; 790 791 /** 792 * struct gmap_pgtable - gmap information attached to a page table 793 * @vmaddr: address of the 1MB segment in the process virtual memory 794 * @mapper: list of segment table entries mapping a page table 795 */ 796 struct gmap_pgtable { 797 unsigned long vmaddr; 798 struct list_head mapper; 799 }; 800 801 /** 802 * struct gmap_notifier - notify function block for page invalidation 803 * @notifier_call: address of callback function 804 */ 805 struct gmap_notifier { 806 struct list_head list; 807 void (*notifier_call)(struct gmap *gmap, unsigned long address); 808 }; 809 810 struct gmap *gmap_alloc(struct mm_struct *mm); 811 void gmap_free(struct gmap *gmap); 812 void gmap_enable(struct gmap *gmap); 813 void gmap_disable(struct gmap *gmap); 814 int gmap_map_segment(struct gmap *gmap, unsigned long from, 815 unsigned long to, unsigned long len); 816 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 817 unsigned long __gmap_translate(unsigned long address, struct gmap *); 818 unsigned long gmap_translate(unsigned long address, struct gmap *); 819 unsigned long __gmap_fault(unsigned long address, struct gmap *); 820 unsigned long gmap_fault(unsigned long address, struct gmap *); 821 void gmap_discard(unsigned long from, unsigned long to, struct gmap *); 822 823 void gmap_register_ipte_notifier(struct gmap_notifier *); 824 void gmap_unregister_ipte_notifier(struct gmap_notifier *); 825 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); 826 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); 827 828 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, 829 unsigned long addr, 830 pte_t *ptep, pgste_t pgste) 831 { 832 #ifdef CONFIG_PGSTE 833 if (pgste_val(pgste) & PGSTE_IN_BIT) { 834 pgste_val(pgste) &= ~PGSTE_IN_BIT; 835 gmap_do_ipte_notify(mm, addr, ptep); 836 } 837 #endif 838 return pgste; 839 } 840 841 /* 842 * Certain architectures need to do special things when PTEs 843 * within a page table are directly modified. Thus, the following 844 * hook is made available. 845 */ 846 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 847 pte_t *ptep, pte_t entry) 848 { 849 pgste_t pgste; 850 851 if (mm_has_pgste(mm)) { 852 pgste = pgste_get_lock(ptep); 853 pgste_set_key(ptep, pgste, entry); 854 pgste_set_pte(ptep, entry); 855 pgste_set_unlock(ptep, pgste); 856 } else { 857 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) 858 pte_val(entry) |= _PAGE_CO; 859 *ptep = entry; 860 } 861 } 862 863 /* 864 * query functions pte_write/pte_dirty/pte_young only work if 865 * pte_present() is true. Undefined behaviour if not.. 866 */ 867 static inline int pte_write(pte_t pte) 868 { 869 return (pte_val(pte) & _PAGE_WRITE) != 0; 870 } 871 872 static inline int pte_dirty(pte_t pte) 873 { 874 return (pte_val(pte) & _PAGE_DIRTY) != 0; 875 } 876 877 static inline int pte_young(pte_t pte) 878 { 879 return (pte_val(pte) & _PAGE_YOUNG) != 0; 880 } 881 882 /* 883 * pgd/pmd/pte modification functions 884 */ 885 886 static inline void pgd_clear(pgd_t *pgd) 887 { 888 #ifdef CONFIG_64BIT 889 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 890 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 891 #endif 892 } 893 894 static inline void pud_clear(pud_t *pud) 895 { 896 #ifdef CONFIG_64BIT 897 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 898 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 899 #endif 900 } 901 902 static inline void pmd_clear(pmd_t *pmdp) 903 { 904 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; 905 } 906 907 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 908 { 909 pte_val(*ptep) = _PAGE_INVALID; 910 } 911 912 /* 913 * The following pte modification functions only work if 914 * pte_present() is true. Undefined behaviour if not.. 915 */ 916 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 917 { 918 pte_val(pte) &= _PAGE_CHG_MASK; 919 pte_val(pte) |= pgprot_val(newprot); 920 /* 921 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the 922 * invalid bit set, clear it again for readable, young pages 923 */ 924 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 925 pte_val(pte) &= ~_PAGE_INVALID; 926 /* 927 * newprot for PAGE_READ and PAGE_WRITE has the page protection 928 * bit set, clear it again for writable, dirty pages 929 */ 930 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 931 pte_val(pte) &= ~_PAGE_PROTECT; 932 return pte; 933 } 934 935 static inline pte_t pte_wrprotect(pte_t pte) 936 { 937 pte_val(pte) &= ~_PAGE_WRITE; 938 pte_val(pte) |= _PAGE_PROTECT; 939 return pte; 940 } 941 942 static inline pte_t pte_mkwrite(pte_t pte) 943 { 944 pte_val(pte) |= _PAGE_WRITE; 945 if (pte_val(pte) & _PAGE_DIRTY) 946 pte_val(pte) &= ~_PAGE_PROTECT; 947 return pte; 948 } 949 950 static inline pte_t pte_mkclean(pte_t pte) 951 { 952 pte_val(pte) &= ~_PAGE_DIRTY; 953 pte_val(pte) |= _PAGE_PROTECT; 954 return pte; 955 } 956 957 static inline pte_t pte_mkdirty(pte_t pte) 958 { 959 pte_val(pte) |= _PAGE_DIRTY; 960 if (pte_val(pte) & _PAGE_WRITE) 961 pte_val(pte) &= ~_PAGE_PROTECT; 962 return pte; 963 } 964 965 static inline pte_t pte_mkold(pte_t pte) 966 { 967 pte_val(pte) &= ~_PAGE_YOUNG; 968 pte_val(pte) |= _PAGE_INVALID; 969 return pte; 970 } 971 972 static inline pte_t pte_mkyoung(pte_t pte) 973 { 974 pte_val(pte) |= _PAGE_YOUNG; 975 if (pte_val(pte) & _PAGE_READ) 976 pte_val(pte) &= ~_PAGE_INVALID; 977 return pte; 978 } 979 980 static inline pte_t pte_mkspecial(pte_t pte) 981 { 982 pte_val(pte) |= _PAGE_SPECIAL; 983 return pte; 984 } 985 986 #ifdef CONFIG_HUGETLB_PAGE 987 static inline pte_t pte_mkhuge(pte_t pte) 988 { 989 pte_val(pte) |= _PAGE_LARGE; 990 return pte; 991 } 992 #endif 993 994 /* 995 * Get (and clear) the user dirty bit for a pte. 996 */ 997 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 998 pte_t *ptep) 999 { 1000 pgste_t pgste; 1001 int dirty = 0; 1002 1003 if (mm_has_pgste(mm)) { 1004 pgste = pgste_get_lock(ptep); 1005 pgste = pgste_update_all(ptep, pgste); 1006 dirty = !!(pgste_val(pgste) & PGSTE_HC_BIT); 1007 pgste_val(pgste) &= ~PGSTE_HC_BIT; 1008 pgste_set_unlock(ptep, pgste); 1009 return dirty; 1010 } 1011 return dirty; 1012 } 1013 1014 /* 1015 * Get (and clear) the user referenced bit for a pte. 1016 */ 1017 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, 1018 pte_t *ptep) 1019 { 1020 pgste_t pgste; 1021 int young = 0; 1022 1023 if (mm_has_pgste(mm)) { 1024 pgste = pgste_get_lock(ptep); 1025 pgste = pgste_update_young(ptep, pgste); 1026 young = !!(pgste_val(pgste) & PGSTE_HR_BIT); 1027 pgste_val(pgste) &= ~PGSTE_HR_BIT; 1028 pgste_set_unlock(ptep, pgste); 1029 } 1030 return young; 1031 } 1032 1033 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 1034 { 1035 if (!(pte_val(*ptep) & _PAGE_INVALID)) { 1036 #ifndef CONFIG_64BIT 1037 /* pto must point to the start of the segment table */ 1038 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); 1039 #else 1040 /* ipte in zarch mode can do the math */ 1041 pte_t *pto = ptep; 1042 #endif 1043 asm volatile( 1044 " ipte %2,%3" 1045 : "=m" (*ptep) : "m" (*ptep), 1046 "a" (pto), "a" (address)); 1047 } 1048 } 1049 1050 static inline void ptep_flush_lazy(struct mm_struct *mm, 1051 unsigned long address, pte_t *ptep) 1052 { 1053 int active = (mm == current->active_mm) ? 1 : 0; 1054 1055 if (atomic_read(&mm->context.attach_count) > active) 1056 __ptep_ipte(address, ptep); 1057 else 1058 mm->context.flush_mm = 1; 1059 } 1060 1061 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1062 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1063 unsigned long addr, pte_t *ptep) 1064 { 1065 pgste_t pgste; 1066 pte_t pte; 1067 int young; 1068 1069 if (mm_has_pgste(vma->vm_mm)) { 1070 pgste = pgste_get_lock(ptep); 1071 pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste); 1072 } 1073 1074 pte = *ptep; 1075 __ptep_ipte(addr, ptep); 1076 young = pte_young(pte); 1077 pte = pte_mkold(pte); 1078 1079 if (mm_has_pgste(vma->vm_mm)) { 1080 pgste_set_pte(ptep, pte); 1081 pgste_set_unlock(ptep, pgste); 1082 } else 1083 *ptep = pte; 1084 1085 return young; 1086 } 1087 1088 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1089 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1090 unsigned long address, pte_t *ptep) 1091 { 1092 return ptep_test_and_clear_young(vma, address, ptep); 1093 } 1094 1095 /* 1096 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1097 * both clear the TLB for the unmapped pte. The reason is that 1098 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1099 * to modify an active pte. The sequence is 1100 * 1) ptep_get_and_clear 1101 * 2) set_pte_at 1102 * 3) flush_tlb_range 1103 * On s390 the tlb needs to get flushed with the modification of the pte 1104 * if the pte is active. The only way how this can be implemented is to 1105 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1106 * is a nop. 1107 */ 1108 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1109 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1110 unsigned long address, pte_t *ptep) 1111 { 1112 pgste_t pgste; 1113 pte_t pte; 1114 1115 if (mm_has_pgste(mm)) { 1116 pgste = pgste_get_lock(ptep); 1117 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1118 } 1119 1120 pte = *ptep; 1121 ptep_flush_lazy(mm, address, ptep); 1122 pte_val(*ptep) = _PAGE_INVALID; 1123 1124 if (mm_has_pgste(mm)) { 1125 pgste = pgste_update_all(&pte, pgste); 1126 pgste_set_unlock(ptep, pgste); 1127 } 1128 return pte; 1129 } 1130 1131 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1132 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1133 unsigned long address, 1134 pte_t *ptep) 1135 { 1136 pgste_t pgste; 1137 pte_t pte; 1138 1139 if (mm_has_pgste(mm)) { 1140 pgste = pgste_get_lock(ptep); 1141 pgste_ipte_notify(mm, address, ptep, pgste); 1142 } 1143 1144 pte = *ptep; 1145 ptep_flush_lazy(mm, address, ptep); 1146 pte_val(*ptep) |= _PAGE_INVALID; 1147 1148 if (mm_has_pgste(mm)) { 1149 pgste = pgste_update_all(&pte, pgste); 1150 pgste_set(ptep, pgste); 1151 } 1152 return pte; 1153 } 1154 1155 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1156 unsigned long address, 1157 pte_t *ptep, pte_t pte) 1158 { 1159 pgste_t pgste; 1160 1161 if (mm_has_pgste(mm)) { 1162 pgste = pgste_get(ptep); 1163 pgste_set_key(ptep, pgste, pte); 1164 pgste_set_pte(ptep, pte); 1165 pgste_set_unlock(ptep, pgste); 1166 } else 1167 *ptep = pte; 1168 } 1169 1170 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1171 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1172 unsigned long address, pte_t *ptep) 1173 { 1174 pgste_t pgste; 1175 pte_t pte; 1176 1177 if (mm_has_pgste(vma->vm_mm)) { 1178 pgste = pgste_get_lock(ptep); 1179 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); 1180 } 1181 1182 pte = *ptep; 1183 __ptep_ipte(address, ptep); 1184 pte_val(*ptep) = _PAGE_INVALID; 1185 1186 if (mm_has_pgste(vma->vm_mm)) { 1187 pgste = pgste_update_all(&pte, pgste); 1188 pgste_set_unlock(ptep, pgste); 1189 } 1190 return pte; 1191 } 1192 1193 /* 1194 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1195 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1196 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1197 * cannot be accessed while the batched unmap is running. In this case 1198 * full==1 and a simple pte_clear is enough. See tlb.h. 1199 */ 1200 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1201 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1202 unsigned long address, 1203 pte_t *ptep, int full) 1204 { 1205 pgste_t pgste; 1206 pte_t pte; 1207 1208 if (!full && mm_has_pgste(mm)) { 1209 pgste = pgste_get_lock(ptep); 1210 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1211 } 1212 1213 pte = *ptep; 1214 if (!full) 1215 ptep_flush_lazy(mm, address, ptep); 1216 pte_val(*ptep) = _PAGE_INVALID; 1217 1218 if (!full && mm_has_pgste(mm)) { 1219 pgste = pgste_update_all(&pte, pgste); 1220 pgste_set_unlock(ptep, pgste); 1221 } 1222 return pte; 1223 } 1224 1225 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1226 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1227 unsigned long address, pte_t *ptep) 1228 { 1229 pgste_t pgste; 1230 pte_t pte = *ptep; 1231 1232 if (pte_write(pte)) { 1233 if (mm_has_pgste(mm)) { 1234 pgste = pgste_get_lock(ptep); 1235 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1236 } 1237 1238 ptep_flush_lazy(mm, address, ptep); 1239 pte = pte_wrprotect(pte); 1240 1241 if (mm_has_pgste(mm)) { 1242 pgste_set_pte(ptep, pte); 1243 pgste_set_unlock(ptep, pgste); 1244 } else 1245 *ptep = pte; 1246 } 1247 return pte; 1248 } 1249 1250 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1251 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1252 unsigned long address, pte_t *ptep, 1253 pte_t entry, int dirty) 1254 { 1255 pgste_t pgste; 1256 1257 if (pte_same(*ptep, entry)) 1258 return 0; 1259 if (mm_has_pgste(vma->vm_mm)) { 1260 pgste = pgste_get_lock(ptep); 1261 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); 1262 } 1263 1264 __ptep_ipte(address, ptep); 1265 1266 if (mm_has_pgste(vma->vm_mm)) { 1267 pgste_set_pte(ptep, entry); 1268 pgste_set_unlock(ptep, pgste); 1269 } else 1270 *ptep = entry; 1271 return 1; 1272 } 1273 1274 /* 1275 * Conversion functions: convert a page and protection to a page entry, 1276 * and a page entry and page directory to the page they refer to. 1277 */ 1278 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1279 { 1280 pte_t __pte; 1281 pte_val(__pte) = physpage + pgprot_val(pgprot); 1282 return pte_mkyoung(__pte); 1283 } 1284 1285 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1286 { 1287 unsigned long physpage = page_to_phys(page); 1288 pte_t __pte = mk_pte_phys(physpage, pgprot); 1289 1290 if (pte_write(__pte) && PageDirty(page)) 1291 __pte = pte_mkdirty(__pte); 1292 return __pte; 1293 } 1294 1295 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1296 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1297 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1298 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1299 1300 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1301 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1302 1303 #ifndef CONFIG_64BIT 1304 1305 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1306 #define pud_deref(pmd) ({ BUG(); 0UL; }) 1307 #define pgd_deref(pmd) ({ BUG(); 0UL; }) 1308 1309 #define pud_offset(pgd, address) ((pud_t *) pgd) 1310 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) 1311 1312 #else /* CONFIG_64BIT */ 1313 1314 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1315 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1316 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1317 1318 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1319 { 1320 pud_t *pud = (pud_t *) pgd; 1321 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1322 pud = (pud_t *) pgd_deref(*pgd); 1323 return pud + pud_index(address); 1324 } 1325 1326 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1327 { 1328 pmd_t *pmd = (pmd_t *) pud; 1329 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1330 pmd = (pmd_t *) pud_deref(*pud); 1331 return pmd + pmd_index(address); 1332 } 1333 1334 #endif /* CONFIG_64BIT */ 1335 1336 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1337 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1338 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1339 1340 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 1341 1342 /* Find an entry in the lowest level page table.. */ 1343 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1344 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1345 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1346 #define pte_unmap(pte) do { } while (0) 1347 1348 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp) 1349 { 1350 unsigned long sto = (unsigned long) pmdp - 1351 pmd_index(address) * sizeof(pmd_t); 1352 1353 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)) { 1354 asm volatile( 1355 " .insn rrf,0xb98e0000,%2,%3,0,0" 1356 : "=m" (*pmdp) 1357 : "m" (*pmdp), "a" (sto), 1358 "a" ((address & HPAGE_MASK)) 1359 : "cc" 1360 ); 1361 } 1362 } 1363 1364 static inline void __pmd_csp(pmd_t *pmdp) 1365 { 1366 register unsigned long reg2 asm("2") = pmd_val(*pmdp); 1367 register unsigned long reg3 asm("3") = pmd_val(*pmdp) | 1368 _SEGMENT_ENTRY_INVALID; 1369 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; 1370 1371 asm volatile( 1372 " csp %1,%3" 1373 : "=m" (*pmdp) 1374 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); 1375 } 1376 1377 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1378 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1379 { 1380 /* 1381 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) 1382 * Convert to segment table entry format. 1383 */ 1384 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1385 return pgprot_val(SEGMENT_NONE); 1386 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) 1387 return pgprot_val(SEGMENT_READ); 1388 return pgprot_val(SEGMENT_WRITE); 1389 } 1390 1391 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1392 { 1393 #ifdef CONFIG_64BIT 1394 if (pmd_prot_none(pmd)) { 1395 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1396 } else { 1397 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1398 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; 1399 } 1400 #endif 1401 return pmd; 1402 } 1403 1404 static inline pmd_t pmd_mkold(pmd_t pmd) 1405 { 1406 #ifdef CONFIG_64BIT 1407 if (pmd_prot_none(pmd)) { 1408 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1409 } else { 1410 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; 1411 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1412 } 1413 #endif 1414 return pmd; 1415 } 1416 1417 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1418 { 1419 int young; 1420 1421 young = pmd_young(pmd); 1422 pmd_val(pmd) &= _SEGMENT_CHG_MASK; 1423 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1424 if (young) 1425 pmd = pmd_mkyoung(pmd); 1426 return pmd; 1427 } 1428 1429 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1430 { 1431 pmd_t __pmd; 1432 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1433 return pmd_mkyoung(__pmd); 1434 } 1435 1436 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1437 { 1438 /* Do not clobber PROT_NONE segments! */ 1439 if (!pmd_prot_none(pmd)) 1440 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1441 return pmd; 1442 } 1443 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1444 1445 static inline void pmdp_flush_lazy(struct mm_struct *mm, 1446 unsigned long address, pmd_t *pmdp) 1447 { 1448 int active = (mm == current->active_mm) ? 1 : 0; 1449 1450 if ((atomic_read(&mm->context.attach_count) & 0xffff) > active) 1451 __pmd_idte(address, pmdp); 1452 else 1453 mm->context.flush_mm = 1; 1454 } 1455 1456 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1457 1458 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1459 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1460 pgtable_t pgtable); 1461 1462 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1463 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1464 1465 static inline int pmd_trans_splitting(pmd_t pmd) 1466 { 1467 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; 1468 } 1469 1470 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1471 pmd_t *pmdp, pmd_t entry) 1472 { 1473 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INVALID) && MACHINE_HAS_EDAT1) 1474 pmd_val(entry) |= _SEGMENT_ENTRY_CO; 1475 *pmdp = entry; 1476 } 1477 1478 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1479 { 1480 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1481 return pmd; 1482 } 1483 1484 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1485 { 1486 /* Do not clobber PROT_NONE segments! */ 1487 if (!pmd_prot_none(pmd)) 1488 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1489 return pmd; 1490 } 1491 1492 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1493 { 1494 /* No dirty bit in the segment table entry. */ 1495 return pmd; 1496 } 1497 1498 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1499 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1500 unsigned long address, pmd_t *pmdp) 1501 { 1502 pmd_t pmd; 1503 1504 pmd = *pmdp; 1505 __pmd_idte(address, pmdp); 1506 *pmdp = pmd_mkold(pmd); 1507 return pmd_young(pmd); 1508 } 1509 1510 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 1511 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 1512 unsigned long address, pmd_t *pmdp) 1513 { 1514 pmd_t pmd = *pmdp; 1515 1516 __pmd_idte(address, pmdp); 1517 pmd_clear(pmdp); 1518 return pmd; 1519 } 1520 1521 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH 1522 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, 1523 unsigned long address, pmd_t *pmdp) 1524 { 1525 return pmdp_get_and_clear(vma->vm_mm, address, pmdp); 1526 } 1527 1528 #define __HAVE_ARCH_PMDP_INVALIDATE 1529 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1530 unsigned long address, pmd_t *pmdp) 1531 { 1532 __pmd_idte(address, pmdp); 1533 } 1534 1535 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1536 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1537 unsigned long address, pmd_t *pmdp) 1538 { 1539 pmd_t pmd = *pmdp; 1540 1541 if (pmd_write(pmd)) { 1542 __pmd_idte(address, pmdp); 1543 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); 1544 } 1545 } 1546 1547 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1548 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1549 1550 static inline int pmd_trans_huge(pmd_t pmd) 1551 { 1552 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1553 } 1554 1555 static inline int has_transparent_hugepage(void) 1556 { 1557 return MACHINE_HAS_HPAGE ? 1 : 0; 1558 } 1559 1560 static inline unsigned long pmd_pfn(pmd_t pmd) 1561 { 1562 return pmd_val(pmd) >> PAGE_SHIFT; 1563 } 1564 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1565 1566 /* 1567 * 31 bit swap entry format: 1568 * A page-table entry has some bits we have to treat in a special way. 1569 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification 1570 * exception will occur instead of a page translation exception. The 1571 * specifiation exception has the bad habit not to store necessary 1572 * information in the lowcore. 1573 * Bits 21, 22, 30 and 31 are used to indicate the page type. 1574 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402 1575 * This leaves the bits 1-19 and bits 24-29 to store type and offset. 1576 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 1577 * plus 24 for the offset. 1578 * 0| offset |0110|o|type |00| 1579 * 0 0000000001111111111 2222 2 22222 33 1580 * 0 1234567890123456789 0123 4 56789 01 1581 * 1582 * 64 bit swap entry format: 1583 * A page-table entry has some bits we have to treat in a special way. 1584 * Bits 52 and bit 55 have to be zero, otherwise an specification 1585 * exception will occur instead of a page translation exception. The 1586 * specifiation exception has the bad habit not to store necessary 1587 * information in the lowcore. 1588 * Bits 53, 54, 62 and 63 are used to indicate the page type. 1589 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402 1590 * This leaves the bits 0-51 and bits 56-61 to store type and offset. 1591 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 1592 * plus 56 for the offset. 1593 * | offset |0110|o|type |00| 1594 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 1595 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 1596 */ 1597 #ifndef CONFIG_64BIT 1598 #define __SWP_OFFSET_MASK (~0UL >> 12) 1599 #else 1600 #define __SWP_OFFSET_MASK (~0UL >> 11) 1601 #endif 1602 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1603 { 1604 pte_t pte; 1605 offset &= __SWP_OFFSET_MASK; 1606 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) | 1607 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); 1608 return pte; 1609 } 1610 1611 #define __swp_type(entry) (((entry).val >> 2) & 0x1f) 1612 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) 1613 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 1614 1615 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1616 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1617 1618 #ifndef CONFIG_64BIT 1619 # define PTE_FILE_MAX_BITS 26 1620 #else /* CONFIG_64BIT */ 1621 # define PTE_FILE_MAX_BITS 59 1622 #endif /* CONFIG_64BIT */ 1623 1624 #define pte_to_pgoff(__pte) \ 1625 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) 1626 1627 #define pgoff_to_pte(__off) \ 1628 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ 1629 | _PAGE_INVALID | _PAGE_PROTECT }) 1630 1631 #endif /* !__ASSEMBLY__ */ 1632 1633 #define kern_addr_valid(addr) (1) 1634 1635 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1636 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1637 extern int s390_enable_sie(void); 1638 1639 /* 1640 * No page table caches to initialise 1641 */ 1642 static inline void pgtable_cache_init(void) { } 1643 static inline void check_pgt_cache(void) { } 1644 1645 #include <asm-generic/pgtable.h> 1646 1647 #endif /* _S390_PAGE_H */ 1648