1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/bug.h> 22 #include <asm/page.h> 23 #include <asm/uv.h> 24 25 extern pgd_t swapper_pg_dir[]; 26 extern pgd_t invalid_pg_dir[]; 27 extern void paging_init(void); 28 extern unsigned long s390_invalid_asce; 29 30 enum { 31 PG_DIRECT_MAP_4K = 0, 32 PG_DIRECT_MAP_1M, 33 PG_DIRECT_MAP_2G, 34 PG_DIRECT_MAP_MAX 35 }; 36 37 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 38 39 static inline void update_page_count(int level, long count) 40 { 41 if (IS_ENABLED(CONFIG_PROC_FS)) 42 atomic_long_add(count, &direct_pages_count[level]); 43 } 44 45 /* 46 * The S390 doesn't have any external MMU info: the kernel page 47 * tables contain all the necessary information. 48 */ 49 #define update_mmu_cache(vma, address, ptep) do { } while (0) 50 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 51 52 /* 53 * ZERO_PAGE is a global shared page that is always zero; used 54 * for zero-mapped memory areas etc.. 55 */ 56 57 extern unsigned long empty_zero_page; 58 extern unsigned long zero_page_mask; 59 60 #define ZERO_PAGE(vaddr) \ 61 (virt_to_page((void *)(empty_zero_page + \ 62 (((unsigned long)(vaddr)) &zero_page_mask)))) 63 #define __HAVE_COLOR_ZERO_PAGE 64 65 /* TODO: s390 cannot support io_remap_pfn_range... */ 66 67 #define pte_ERROR(e) \ 68 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 69 #define pmd_ERROR(e) \ 70 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 71 #define pud_ERROR(e) \ 72 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 73 #define p4d_ERROR(e) \ 74 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 75 #define pgd_ERROR(e) \ 76 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 77 78 /* 79 * The vmalloc and module area will always be on the topmost area of the 80 * kernel mapping. 512GB are reserved for vmalloc by default. 81 * At the top of the vmalloc area a 2GB area is reserved where modules 82 * will reside. That makes sure that inter module branches always 83 * happen without trampolines and in addition the placement within a 84 * 2GB frame is branch prediction unit friendly. 85 */ 86 extern unsigned long __bootdata_preserved(VMALLOC_START); 87 extern unsigned long __bootdata_preserved(VMALLOC_END); 88 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 89 extern struct page *__bootdata_preserved(vmemmap); 90 extern unsigned long __bootdata_preserved(vmemmap_size); 91 92 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 93 94 extern unsigned long __bootdata_preserved(MODULES_VADDR); 95 extern unsigned long __bootdata_preserved(MODULES_END); 96 #define MODULES_VADDR MODULES_VADDR 97 #define MODULES_END MODULES_END 98 #define MODULES_LEN (1UL << 31) 99 100 static inline int is_module_addr(void *addr) 101 { 102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 103 if (addr < (void *)MODULES_VADDR) 104 return 0; 105 if (addr > (void *)MODULES_END) 106 return 0; 107 return 1; 108 } 109 110 /* 111 * A 64 bit pagetable entry of S390 has following format: 112 * | PFRA |0IPC| OS | 113 * 0000000000111111111122222222223333333333444444444455555555556666 114 * 0123456789012345678901234567890123456789012345678901234567890123 115 * 116 * I Page-Invalid Bit: Page is not available for address-translation 117 * P Page-Protection Bit: Store access not possible for page 118 * C Change-bit override: HW is not required to set change bit 119 * 120 * A 64 bit segmenttable entry of S390 has following format: 121 * | P-table origin | TT 122 * 0000000000111111111122222222223333333333444444444455555555556666 123 * 0123456789012345678901234567890123456789012345678901234567890123 124 * 125 * I Segment-Invalid Bit: Segment is not available for address-translation 126 * C Common-Segment Bit: Segment is not private (PoP 3-30) 127 * P Page-Protection Bit: Store access not possible for page 128 * TT Type 00 129 * 130 * A 64 bit region table entry of S390 has following format: 131 * | S-table origin | TF TTTL 132 * 0000000000111111111122222222223333333333444444444455555555556666 133 * 0123456789012345678901234567890123456789012345678901234567890123 134 * 135 * I Segment-Invalid Bit: Segment is not available for address-translation 136 * TT Type 01 137 * TF 138 * TL Table length 139 * 140 * The 64 bit regiontable origin of S390 has following format: 141 * | region table origon | DTTL 142 * 0000000000111111111122222222223333333333444444444455555555556666 143 * 0123456789012345678901234567890123456789012345678901234567890123 144 * 145 * X Space-Switch event: 146 * G Segment-Invalid Bit: 147 * P Private-Space Bit: 148 * S Storage-Alteration: 149 * R Real space 150 * TL Table-Length: 151 * 152 * A storage key has the following format: 153 * | ACC |F|R|C|0| 154 * 0 3 4 5 6 7 155 * ACC: access key 156 * F : fetch protection bit 157 * R : referenced bit 158 * C : changed bit 159 */ 160 161 /* Hardware bits in the page table entry */ 162 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 163 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 164 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 165 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 166 167 /* Software bits in the page table entry */ 168 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 169 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 170 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 171 #define _PAGE_READ 0x010 /* SW pte read bit */ 172 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 173 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 174 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 175 176 #ifdef CONFIG_MEM_SOFT_DIRTY 177 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 178 #else 179 #define _PAGE_SOFT_DIRTY 0x000 180 #endif 181 182 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 183 184 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 185 186 /* Set of bits not changed in pte_modify */ 187 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 188 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 189 190 /* 191 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 192 * HW bit and all SW bits. 193 */ 194 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 195 196 /* 197 * handle_pte_fault uses pte_present and pte_none to find out the pte type 198 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 199 * distinguish present from not-present ptes. It is changed only with the page 200 * table lock held. 201 * 202 * The following table gives the different possible bit combinations for 203 * the pte hardware and software bits in the last 12 bits of a pte 204 * (. unassigned bit, x don't care, t swap type): 205 * 206 * 842100000000 207 * 000084210000 208 * 000000008421 209 * .IR.uswrdy.p 210 * empty .10.00000000 211 * swap .11..ttttt.0 212 * prot-none, clean, old .11.xx0000.1 213 * prot-none, clean, young .11.xx0001.1 214 * prot-none, dirty, old .11.xx0010.1 215 * prot-none, dirty, young .11.xx0011.1 216 * read-only, clean, old .11.xx0100.1 217 * read-only, clean, young .01.xx0101.1 218 * read-only, dirty, old .11.xx0110.1 219 * read-only, dirty, young .01.xx0111.1 220 * read-write, clean, old .11.xx1100.1 221 * read-write, clean, young .01.xx1101.1 222 * read-write, dirty, old .10.xx1110.1 223 * read-write, dirty, young .00.xx1111.1 224 * HW-bits: R read-only, I invalid 225 * SW-bits: p present, y young, d dirty, r read, w write, s special, 226 * u unused, l large 227 * 228 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 229 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 230 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 231 */ 232 233 /* Bits in the segment/region table address-space-control-element */ 234 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 235 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 236 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 237 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 238 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 239 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 240 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 241 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 242 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 243 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 244 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 245 246 /* Bits in the region table entry */ 247 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 248 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 249 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 250 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 251 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 252 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 253 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 254 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 255 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 256 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 257 258 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 259 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 260 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 261 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 262 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 263 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 264 265 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 266 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 267 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 268 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 269 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 270 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 271 272 #ifdef CONFIG_MEM_SOFT_DIRTY 273 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 274 #else 275 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 276 #endif 277 278 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 279 280 /* Bits in the segment table entry */ 281 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 282 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 283 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 284 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 285 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 286 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 287 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 288 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 289 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 290 291 #define _SEGMENT_ENTRY (0) 292 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 293 294 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 295 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 296 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 297 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 298 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 299 300 #ifdef CONFIG_MEM_SOFT_DIRTY 301 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 302 #else 303 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 304 #endif 305 306 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 307 #define _PAGE_ENTRIES 256 /* number of page table entries */ 308 309 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 310 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 311 312 #define _REGION1_SHIFT 53 313 #define _REGION2_SHIFT 42 314 #define _REGION3_SHIFT 31 315 #define _SEGMENT_SHIFT 20 316 317 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 318 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 319 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 320 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 321 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 322 323 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 324 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 325 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 326 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 327 328 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 329 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 330 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 331 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 332 333 #define PMD_SHIFT _SEGMENT_SHIFT 334 #define PUD_SHIFT _REGION3_SHIFT 335 #define P4D_SHIFT _REGION2_SHIFT 336 #define PGDIR_SHIFT _REGION1_SHIFT 337 338 #define PMD_SIZE _SEGMENT_SIZE 339 #define PUD_SIZE _REGION3_SIZE 340 #define P4D_SIZE _REGION2_SIZE 341 #define PGDIR_SIZE _REGION1_SIZE 342 343 #define PMD_MASK _SEGMENT_MASK 344 #define PUD_MASK _REGION3_MASK 345 #define P4D_MASK _REGION2_MASK 346 #define PGDIR_MASK _REGION1_MASK 347 348 #define PTRS_PER_PTE _PAGE_ENTRIES 349 #define PTRS_PER_PMD _CRST_ENTRIES 350 #define PTRS_PER_PUD _CRST_ENTRIES 351 #define PTRS_PER_P4D _CRST_ENTRIES 352 #define PTRS_PER_PGD _CRST_ENTRIES 353 354 /* 355 * Segment table and region3 table entry encoding 356 * (R = read-only, I = invalid, y = young bit): 357 * dy..R...I...wr 358 * prot-none, clean, old 00..1...1...00 359 * prot-none, clean, young 01..1...1...00 360 * prot-none, dirty, old 10..1...1...00 361 * prot-none, dirty, young 11..1...1...00 362 * read-only, clean, old 00..1...1...01 363 * read-only, clean, young 01..1...0...01 364 * read-only, dirty, old 10..1...1...01 365 * read-only, dirty, young 11..1...0...01 366 * read-write, clean, old 00..1...1...11 367 * read-write, clean, young 01..1...0...11 368 * read-write, dirty, old 10..0...1...11 369 * read-write, dirty, young 11..0...0...11 370 * The segment table origin is used to distinguish empty (origin==0) from 371 * read-write, old segment table entries (origin!=0) 372 * HW-bits: R read-only, I invalid 373 * SW-bits: y young, d dirty, r read, w write 374 */ 375 376 /* Page status table bits for virtualization */ 377 #define PGSTE_ACC_BITS 0xf000000000000000UL 378 #define PGSTE_FP_BIT 0x0800000000000000UL 379 #define PGSTE_PCL_BIT 0x0080000000000000UL 380 #define PGSTE_HR_BIT 0x0040000000000000UL 381 #define PGSTE_HC_BIT 0x0020000000000000UL 382 #define PGSTE_GR_BIT 0x0004000000000000UL 383 #define PGSTE_GC_BIT 0x0002000000000000UL 384 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 385 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 386 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 387 388 /* Guest Page State used for virtualization */ 389 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 390 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 391 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 392 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 393 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 394 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 395 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 396 397 /* 398 * A user page table pointer has the space-switch-event bit, the 399 * private-space-control bit and the storage-alteration-event-control 400 * bit set. A kernel page table pointer doesn't need them. 401 */ 402 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 403 _ASCE_ALT_EVENT) 404 405 /* 406 * Page protection definitions. 407 */ 408 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 409 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 410 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 411 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 412 _PAGE_INVALID | _PAGE_PROTECT) 413 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 414 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 415 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 416 _PAGE_INVALID | _PAGE_PROTECT) 417 418 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 419 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 420 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 421 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 422 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 423 _PAGE_PROTECT | _PAGE_NOEXEC) 424 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 425 _PAGE_YOUNG | _PAGE_DIRTY) 426 427 /* 428 * On s390 the page table entry has an invalid bit and a read-only bit. 429 * Read permission implies execute permission and write permission 430 * implies read permission. 431 */ 432 /*xwr*/ 433 434 /* 435 * Segment entry (large page) protection definitions. 436 */ 437 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 438 _SEGMENT_ENTRY_PROTECT) 439 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 440 _SEGMENT_ENTRY_READ | \ 441 _SEGMENT_ENTRY_NOEXEC) 442 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 443 _SEGMENT_ENTRY_READ) 444 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 445 _SEGMENT_ENTRY_WRITE | \ 446 _SEGMENT_ENTRY_NOEXEC) 447 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 448 _SEGMENT_ENTRY_WRITE) 449 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 450 _SEGMENT_ENTRY_LARGE | \ 451 _SEGMENT_ENTRY_READ | \ 452 _SEGMENT_ENTRY_WRITE | \ 453 _SEGMENT_ENTRY_YOUNG | \ 454 _SEGMENT_ENTRY_DIRTY | \ 455 _SEGMENT_ENTRY_NOEXEC) 456 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 457 _SEGMENT_ENTRY_LARGE | \ 458 _SEGMENT_ENTRY_READ | \ 459 _SEGMENT_ENTRY_YOUNG | \ 460 _SEGMENT_ENTRY_PROTECT | \ 461 _SEGMENT_ENTRY_NOEXEC) 462 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 463 _SEGMENT_ENTRY_LARGE | \ 464 _SEGMENT_ENTRY_READ | \ 465 _SEGMENT_ENTRY_WRITE | \ 466 _SEGMENT_ENTRY_YOUNG | \ 467 _SEGMENT_ENTRY_DIRTY) 468 469 /* 470 * Region3 entry (large page) protection definitions. 471 */ 472 473 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 474 _REGION3_ENTRY_LARGE | \ 475 _REGION3_ENTRY_READ | \ 476 _REGION3_ENTRY_WRITE | \ 477 _REGION3_ENTRY_YOUNG | \ 478 _REGION3_ENTRY_DIRTY | \ 479 _REGION_ENTRY_NOEXEC) 480 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 481 _REGION3_ENTRY_LARGE | \ 482 _REGION3_ENTRY_READ | \ 483 _REGION3_ENTRY_YOUNG | \ 484 _REGION_ENTRY_PROTECT | \ 485 _REGION_ENTRY_NOEXEC) 486 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 487 _REGION3_ENTRY_LARGE | \ 488 _REGION3_ENTRY_READ | \ 489 _REGION3_ENTRY_WRITE | \ 490 _REGION3_ENTRY_YOUNG | \ 491 _REGION3_ENTRY_DIRTY) 492 493 static inline bool mm_p4d_folded(struct mm_struct *mm) 494 { 495 return mm->context.asce_limit <= _REGION1_SIZE; 496 } 497 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 498 499 static inline bool mm_pud_folded(struct mm_struct *mm) 500 { 501 return mm->context.asce_limit <= _REGION2_SIZE; 502 } 503 #define mm_pud_folded(mm) mm_pud_folded(mm) 504 505 static inline bool mm_pmd_folded(struct mm_struct *mm) 506 { 507 return mm->context.asce_limit <= _REGION3_SIZE; 508 } 509 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 510 511 static inline int mm_has_pgste(struct mm_struct *mm) 512 { 513 #ifdef CONFIG_PGSTE 514 if (unlikely(mm->context.has_pgste)) 515 return 1; 516 #endif 517 return 0; 518 } 519 520 static inline int mm_is_protected(struct mm_struct *mm) 521 { 522 #ifdef CONFIG_PGSTE 523 if (unlikely(atomic_read(&mm->context.protected_count))) 524 return 1; 525 #endif 526 return 0; 527 } 528 529 static inline int mm_alloc_pgste(struct mm_struct *mm) 530 { 531 #ifdef CONFIG_PGSTE 532 if (unlikely(mm->context.alloc_pgste)) 533 return 1; 534 #endif 535 return 0; 536 } 537 538 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 539 { 540 return __pte(pte_val(pte) & ~pgprot_val(prot)); 541 } 542 543 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 544 { 545 return __pte(pte_val(pte) | pgprot_val(prot)); 546 } 547 548 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 549 { 550 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 551 } 552 553 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 554 { 555 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 556 } 557 558 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 559 { 560 return __pud(pud_val(pud) & ~pgprot_val(prot)); 561 } 562 563 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 564 { 565 return __pud(pud_val(pud) | pgprot_val(prot)); 566 } 567 568 /* 569 * In the case that a guest uses storage keys 570 * faults should no longer be backed by zero pages 571 */ 572 #define mm_forbids_zeropage mm_has_pgste 573 static inline int mm_uses_skeys(struct mm_struct *mm) 574 { 575 #ifdef CONFIG_PGSTE 576 if (mm->context.uses_skeys) 577 return 1; 578 #endif 579 return 0; 580 } 581 582 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 583 { 584 union register_pair r1 = { .even = old, .odd = new, }; 585 unsigned long address = (unsigned long)ptr | 1; 586 587 asm volatile( 588 " csp %[r1],%[address]" 589 : [r1] "+&d" (r1.pair), "+m" (*ptr) 590 : [address] "d" (address) 591 : "cc"); 592 } 593 594 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 595 { 596 union register_pair r1 = { .even = old, .odd = new, }; 597 unsigned long address = (unsigned long)ptr | 1; 598 599 asm volatile( 600 " cspg %[r1],%[address]" 601 : [r1] "+&d" (r1.pair), "+m" (*ptr) 602 : [address] "d" (address) 603 : "cc"); 604 } 605 606 #define CRDTE_DTT_PAGE 0x00UL 607 #define CRDTE_DTT_SEGMENT 0x10UL 608 #define CRDTE_DTT_REGION3 0x14UL 609 #define CRDTE_DTT_REGION2 0x18UL 610 #define CRDTE_DTT_REGION1 0x1cUL 611 612 static inline void crdte(unsigned long old, unsigned long new, 613 unsigned long *table, unsigned long dtt, 614 unsigned long address, unsigned long asce) 615 { 616 union register_pair r1 = { .even = old, .odd = new, }; 617 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 618 619 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 620 : [r1] "+&d" (r1.pair) 621 : [r2] "d" (r2.pair), [asce] "a" (asce) 622 : "memory", "cc"); 623 } 624 625 /* 626 * pgd/p4d/pud/pmd/pte query functions 627 */ 628 static inline int pgd_folded(pgd_t pgd) 629 { 630 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 631 } 632 633 static inline int pgd_present(pgd_t pgd) 634 { 635 if (pgd_folded(pgd)) 636 return 1; 637 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 638 } 639 640 static inline int pgd_none(pgd_t pgd) 641 { 642 if (pgd_folded(pgd)) 643 return 0; 644 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 645 } 646 647 static inline int pgd_bad(pgd_t pgd) 648 { 649 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 650 return 0; 651 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 652 } 653 654 static inline unsigned long pgd_pfn(pgd_t pgd) 655 { 656 unsigned long origin_mask; 657 658 origin_mask = _REGION_ENTRY_ORIGIN; 659 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 660 } 661 662 static inline int p4d_folded(p4d_t p4d) 663 { 664 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 665 } 666 667 static inline int p4d_present(p4d_t p4d) 668 { 669 if (p4d_folded(p4d)) 670 return 1; 671 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 672 } 673 674 static inline int p4d_none(p4d_t p4d) 675 { 676 if (p4d_folded(p4d)) 677 return 0; 678 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 679 } 680 681 static inline unsigned long p4d_pfn(p4d_t p4d) 682 { 683 unsigned long origin_mask; 684 685 origin_mask = _REGION_ENTRY_ORIGIN; 686 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 687 } 688 689 static inline int pud_folded(pud_t pud) 690 { 691 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 692 } 693 694 static inline int pud_present(pud_t pud) 695 { 696 if (pud_folded(pud)) 697 return 1; 698 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 699 } 700 701 static inline int pud_none(pud_t pud) 702 { 703 if (pud_folded(pud)) 704 return 0; 705 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 706 } 707 708 #define pud_leaf pud_large 709 static inline int pud_large(pud_t pud) 710 { 711 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 712 return 0; 713 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 714 } 715 716 #define pmd_leaf pmd_large 717 static inline int pmd_large(pmd_t pmd) 718 { 719 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 720 } 721 722 static inline int pmd_bad(pmd_t pmd) 723 { 724 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 725 return 1; 726 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 727 } 728 729 static inline int pud_bad(pud_t pud) 730 { 731 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 732 733 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud)) 734 return 1; 735 if (type < _REGION_ENTRY_TYPE_R3) 736 return 0; 737 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 738 } 739 740 static inline int p4d_bad(p4d_t p4d) 741 { 742 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 743 744 if (type > _REGION_ENTRY_TYPE_R2) 745 return 1; 746 if (type < _REGION_ENTRY_TYPE_R2) 747 return 0; 748 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 749 } 750 751 static inline int pmd_present(pmd_t pmd) 752 { 753 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 754 } 755 756 static inline int pmd_none(pmd_t pmd) 757 { 758 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 759 } 760 761 #define pmd_write pmd_write 762 static inline int pmd_write(pmd_t pmd) 763 { 764 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 765 } 766 767 #define pud_write pud_write 768 static inline int pud_write(pud_t pud) 769 { 770 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 771 } 772 773 static inline int pmd_dirty(pmd_t pmd) 774 { 775 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 776 } 777 778 #define pmd_young pmd_young 779 static inline int pmd_young(pmd_t pmd) 780 { 781 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 782 } 783 784 static inline int pte_present(pte_t pte) 785 { 786 /* Bit pattern: (pte & 0x001) == 0x001 */ 787 return (pte_val(pte) & _PAGE_PRESENT) != 0; 788 } 789 790 static inline int pte_none(pte_t pte) 791 { 792 /* Bit pattern: pte == 0x400 */ 793 return pte_val(pte) == _PAGE_INVALID; 794 } 795 796 static inline int pte_swap(pte_t pte) 797 { 798 /* Bit pattern: (pte & 0x201) == 0x200 */ 799 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 800 == _PAGE_PROTECT; 801 } 802 803 static inline int pte_special(pte_t pte) 804 { 805 return (pte_val(pte) & _PAGE_SPECIAL); 806 } 807 808 #define __HAVE_ARCH_PTE_SAME 809 static inline int pte_same(pte_t a, pte_t b) 810 { 811 return pte_val(a) == pte_val(b); 812 } 813 814 #ifdef CONFIG_NUMA_BALANCING 815 static inline int pte_protnone(pte_t pte) 816 { 817 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 818 } 819 820 static inline int pmd_protnone(pmd_t pmd) 821 { 822 /* pmd_large(pmd) implies pmd_present(pmd) */ 823 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 824 } 825 #endif 826 827 static inline int pte_swp_exclusive(pte_t pte) 828 { 829 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 830 } 831 832 static inline pte_t pte_swp_mkexclusive(pte_t pte) 833 { 834 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 835 } 836 837 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 838 { 839 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 840 } 841 842 static inline int pte_soft_dirty(pte_t pte) 843 { 844 return pte_val(pte) & _PAGE_SOFT_DIRTY; 845 } 846 #define pte_swp_soft_dirty pte_soft_dirty 847 848 static inline pte_t pte_mksoft_dirty(pte_t pte) 849 { 850 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 851 } 852 #define pte_swp_mksoft_dirty pte_mksoft_dirty 853 854 static inline pte_t pte_clear_soft_dirty(pte_t pte) 855 { 856 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 857 } 858 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 859 860 static inline int pmd_soft_dirty(pmd_t pmd) 861 { 862 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 863 } 864 865 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 866 { 867 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 868 } 869 870 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 871 { 872 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 873 } 874 875 /* 876 * query functions pte_write/pte_dirty/pte_young only work if 877 * pte_present() is true. Undefined behaviour if not.. 878 */ 879 static inline int pte_write(pte_t pte) 880 { 881 return (pte_val(pte) & _PAGE_WRITE) != 0; 882 } 883 884 static inline int pte_dirty(pte_t pte) 885 { 886 return (pte_val(pte) & _PAGE_DIRTY) != 0; 887 } 888 889 static inline int pte_young(pte_t pte) 890 { 891 return (pte_val(pte) & _PAGE_YOUNG) != 0; 892 } 893 894 #define __HAVE_ARCH_PTE_UNUSED 895 static inline int pte_unused(pte_t pte) 896 { 897 return pte_val(pte) & _PAGE_UNUSED; 898 } 899 900 /* 901 * Extract the pgprot value from the given pte while at the same time making it 902 * usable for kernel address space mappings where fault driven dirty and 903 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 904 * must not be set. 905 */ 906 static inline pgprot_t pte_pgprot(pte_t pte) 907 { 908 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 909 910 if (pte_write(pte)) 911 pte_flags |= pgprot_val(PAGE_KERNEL); 912 else 913 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 914 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 915 916 return __pgprot(pte_flags); 917 } 918 919 /* 920 * pgd/pmd/pte modification functions 921 */ 922 923 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 924 { 925 WRITE_ONCE(*pgdp, pgd); 926 } 927 928 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 929 { 930 WRITE_ONCE(*p4dp, p4d); 931 } 932 933 static inline void set_pud(pud_t *pudp, pud_t pud) 934 { 935 WRITE_ONCE(*pudp, pud); 936 } 937 938 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 939 { 940 WRITE_ONCE(*pmdp, pmd); 941 } 942 943 static inline void set_pte(pte_t *ptep, pte_t pte) 944 { 945 WRITE_ONCE(*ptep, pte); 946 } 947 948 static inline void pgd_clear(pgd_t *pgd) 949 { 950 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 951 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 952 } 953 954 static inline void p4d_clear(p4d_t *p4d) 955 { 956 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 957 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 958 } 959 960 static inline void pud_clear(pud_t *pud) 961 { 962 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 963 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 964 } 965 966 static inline void pmd_clear(pmd_t *pmdp) 967 { 968 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 969 } 970 971 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 972 { 973 set_pte(ptep, __pte(_PAGE_INVALID)); 974 } 975 976 /* 977 * The following pte modification functions only work if 978 * pte_present() is true. Undefined behaviour if not.. 979 */ 980 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 981 { 982 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 983 pte = set_pte_bit(pte, newprot); 984 /* 985 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 986 * has the invalid bit set, clear it again for readable, young pages 987 */ 988 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 989 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 990 /* 991 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 992 * protection bit set, clear it again for writable, dirty pages 993 */ 994 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 995 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 996 return pte; 997 } 998 999 static inline pte_t pte_wrprotect(pte_t pte) 1000 { 1001 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1002 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1003 } 1004 1005 static inline pte_t pte_mkwrite(pte_t pte) 1006 { 1007 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1008 if (pte_val(pte) & _PAGE_DIRTY) 1009 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1010 return pte; 1011 } 1012 1013 static inline pte_t pte_mkclean(pte_t pte) 1014 { 1015 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1016 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1017 } 1018 1019 static inline pte_t pte_mkdirty(pte_t pte) 1020 { 1021 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1022 if (pte_val(pte) & _PAGE_WRITE) 1023 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1024 return pte; 1025 } 1026 1027 static inline pte_t pte_mkold(pte_t pte) 1028 { 1029 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1030 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1031 } 1032 1033 static inline pte_t pte_mkyoung(pte_t pte) 1034 { 1035 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1036 if (pte_val(pte) & _PAGE_READ) 1037 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1038 return pte; 1039 } 1040 1041 static inline pte_t pte_mkspecial(pte_t pte) 1042 { 1043 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1044 } 1045 1046 #ifdef CONFIG_HUGETLB_PAGE 1047 static inline pte_t pte_mkhuge(pte_t pte) 1048 { 1049 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1050 } 1051 #endif 1052 1053 #define IPTE_GLOBAL 0 1054 #define IPTE_LOCAL 1 1055 1056 #define IPTE_NODAT 0x400 1057 #define IPTE_GUEST_ASCE 0x800 1058 1059 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1060 unsigned long opt, unsigned long asce, 1061 int local) 1062 { 1063 unsigned long pto; 1064 1065 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1066 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1067 : "+m" (*ptep) 1068 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1069 [asce] "a" (asce), [m4] "i" (local)); 1070 } 1071 1072 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1073 unsigned long opt, unsigned long asce, 1074 int local) 1075 { 1076 unsigned long pto = __pa(ptep); 1077 1078 if (__builtin_constant_p(opt) && opt == 0) { 1079 /* Invalidation + TLB flush for the pte */ 1080 asm volatile( 1081 " ipte %[r1],%[r2],0,%[m4]" 1082 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1083 [m4] "i" (local)); 1084 return; 1085 } 1086 1087 /* Invalidate ptes with options + TLB flush of the ptes */ 1088 opt = opt | (asce & _ASCE_ORIGIN); 1089 asm volatile( 1090 " ipte %[r1],%[r2],%[r3],%[m4]" 1091 : [r2] "+a" (address), [r3] "+a" (opt) 1092 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1093 } 1094 1095 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1096 pte_t *ptep, int local) 1097 { 1098 unsigned long pto = __pa(ptep); 1099 1100 /* Invalidate a range of ptes + TLB flush of the ptes */ 1101 do { 1102 asm volatile( 1103 " ipte %[r1],%[r2],%[r3],%[m4]" 1104 : [r2] "+a" (address), [r3] "+a" (nr) 1105 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1106 } while (nr != 255); 1107 } 1108 1109 /* 1110 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1111 * both clear the TLB for the unmapped pte. The reason is that 1112 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1113 * to modify an active pte. The sequence is 1114 * 1) ptep_get_and_clear 1115 * 2) set_pte_at 1116 * 3) flush_tlb_range 1117 * On s390 the tlb needs to get flushed with the modification of the pte 1118 * if the pte is active. The only way how this can be implemented is to 1119 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1120 * is a nop. 1121 */ 1122 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1123 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1124 1125 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1126 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1127 unsigned long addr, pte_t *ptep) 1128 { 1129 pte_t pte = *ptep; 1130 1131 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1132 return pte_young(pte); 1133 } 1134 1135 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1136 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1137 unsigned long address, pte_t *ptep) 1138 { 1139 return ptep_test_and_clear_young(vma, address, ptep); 1140 } 1141 1142 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1143 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1144 unsigned long addr, pte_t *ptep) 1145 { 1146 pte_t res; 1147 1148 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1149 /* At this point the reference through the mapping is still present */ 1150 if (mm_is_protected(mm) && pte_present(res)) 1151 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1152 return res; 1153 } 1154 1155 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1156 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1157 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1158 pte_t *, pte_t, pte_t); 1159 1160 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1161 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1162 unsigned long addr, pte_t *ptep) 1163 { 1164 pte_t res; 1165 1166 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1167 /* At this point the reference through the mapping is still present */ 1168 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1169 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1170 return res; 1171 } 1172 1173 /* 1174 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1175 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1176 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1177 * cannot be accessed while the batched unmap is running. In this case 1178 * full==1 and a simple pte_clear is enough. See tlb.h. 1179 */ 1180 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1181 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1182 unsigned long addr, 1183 pte_t *ptep, int full) 1184 { 1185 pte_t res; 1186 1187 if (full) { 1188 res = *ptep; 1189 set_pte(ptep, __pte(_PAGE_INVALID)); 1190 } else { 1191 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1192 } 1193 /* Nothing to do */ 1194 if (!mm_is_protected(mm) || !pte_present(res)) 1195 return res; 1196 /* 1197 * At this point the reference through the mapping is still present. 1198 * The notifier should have destroyed all protected vCPUs at this 1199 * point, so the destroy should be successful. 1200 */ 1201 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1202 return res; 1203 /* 1204 * If something went wrong and the page could not be destroyed, or 1205 * if this is not a mm teardown, the slower export is used as 1206 * fallback instead. 1207 */ 1208 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1209 return res; 1210 } 1211 1212 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1213 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1214 unsigned long addr, pte_t *ptep) 1215 { 1216 pte_t pte = *ptep; 1217 1218 if (pte_write(pte)) 1219 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1220 } 1221 1222 /* 1223 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1224 * bits in the comparison. Those might change e.g. because of dirty and young 1225 * tracking. 1226 */ 1227 static inline int pte_allow_rdp(pte_t old, pte_t new) 1228 { 1229 /* 1230 * Only allow changes from RO to RW 1231 */ 1232 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1233 return 0; 1234 1235 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1236 } 1237 1238 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1239 unsigned long address, 1240 pte_t *ptep) 1241 { 1242 /* 1243 * RDP might not have propagated the PTE protection reset to all CPUs, 1244 * so there could be spurious TLB protection faults. 1245 * NOTE: This will also be called when a racing pagetable update on 1246 * another thread already installed the correct PTE. Both cases cannot 1247 * really be distinguished. 1248 * Therefore, only do the local TLB flush when RDP can be used, and the 1249 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1250 * A local RDP can be used to do the flush. 1251 */ 1252 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1253 __ptep_rdp(address, ptep, 0, 0, 1); 1254 } 1255 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1256 1257 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1258 pte_t new); 1259 1260 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1261 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1262 unsigned long addr, pte_t *ptep, 1263 pte_t entry, int dirty) 1264 { 1265 if (pte_same(*ptep, entry)) 1266 return 0; 1267 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1268 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1269 else 1270 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1271 return 1; 1272 } 1273 1274 /* 1275 * Additional functions to handle KVM guest page tables 1276 */ 1277 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1278 pte_t *ptep, pte_t entry); 1279 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1280 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1281 pte_t *ptep, unsigned long bits); 1282 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1283 pte_t *ptep, int prot, unsigned long bit); 1284 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1285 pte_t *ptep , int reset); 1286 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1287 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1288 pte_t *sptep, pte_t *tptep, pte_t pte); 1289 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1290 1291 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1292 pte_t *ptep); 1293 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1294 unsigned char key, bool nq); 1295 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1296 unsigned char key, unsigned char *oldkey, 1297 bool nq, bool mr, bool mc); 1298 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1299 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1300 unsigned char *key); 1301 1302 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1303 unsigned long bits, unsigned long value); 1304 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1305 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1306 unsigned long *oldpte, unsigned long *oldpgste); 1307 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1308 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1309 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1310 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1311 1312 #define pgprot_writecombine pgprot_writecombine 1313 pgprot_t pgprot_writecombine(pgprot_t prot); 1314 1315 #define pgprot_writethrough pgprot_writethrough 1316 pgprot_t pgprot_writethrough(pgprot_t prot); 1317 1318 /* 1319 * Certain architectures need to do special things when PTEs 1320 * within a page table are directly modified. Thus, the following 1321 * hook is made available. 1322 */ 1323 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 1324 pte_t *ptep, pte_t entry) 1325 { 1326 if (pte_present(entry)) 1327 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1328 if (mm_has_pgste(mm)) 1329 ptep_set_pte_at(mm, addr, ptep, entry); 1330 else 1331 set_pte(ptep, entry); 1332 } 1333 1334 /* 1335 * Conversion functions: convert a page and protection to a page entry, 1336 * and a page entry and page directory to the page they refer to. 1337 */ 1338 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1339 { 1340 pte_t __pte; 1341 1342 __pte = __pte(physpage | pgprot_val(pgprot)); 1343 if (!MACHINE_HAS_NX) 1344 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1345 return pte_mkyoung(__pte); 1346 } 1347 1348 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1349 { 1350 unsigned long physpage = page_to_phys(page); 1351 pte_t __pte = mk_pte_phys(physpage, pgprot); 1352 1353 if (pte_write(__pte) && PageDirty(page)) 1354 __pte = pte_mkdirty(__pte); 1355 return __pte; 1356 } 1357 1358 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1359 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1360 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1361 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1362 1363 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1364 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1365 1366 static inline unsigned long pmd_deref(pmd_t pmd) 1367 { 1368 unsigned long origin_mask; 1369 1370 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1371 if (pmd_large(pmd)) 1372 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1373 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1374 } 1375 1376 static inline unsigned long pmd_pfn(pmd_t pmd) 1377 { 1378 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1379 } 1380 1381 static inline unsigned long pud_deref(pud_t pud) 1382 { 1383 unsigned long origin_mask; 1384 1385 origin_mask = _REGION_ENTRY_ORIGIN; 1386 if (pud_large(pud)) 1387 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1388 return (unsigned long)__va(pud_val(pud) & origin_mask); 1389 } 1390 1391 static inline unsigned long pud_pfn(pud_t pud) 1392 { 1393 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1394 } 1395 1396 /* 1397 * The pgd_offset function *always* adds the index for the top-level 1398 * region/segment table. This is done to get a sequence like the 1399 * following to work: 1400 * pgdp = pgd_offset(current->mm, addr); 1401 * pgd = READ_ONCE(*pgdp); 1402 * p4dp = p4d_offset(&pgd, addr); 1403 * ... 1404 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1405 * only add an index if they dereferenced the pointer. 1406 */ 1407 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1408 { 1409 unsigned long rste; 1410 unsigned int shift; 1411 1412 /* Get the first entry of the top level table */ 1413 rste = pgd_val(*pgd); 1414 /* Pick up the shift from the table type of the first entry */ 1415 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1416 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1417 } 1418 1419 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1420 1421 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1422 { 1423 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1424 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1425 return (p4d_t *) pgdp; 1426 } 1427 #define p4d_offset_lockless p4d_offset_lockless 1428 1429 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1430 { 1431 return p4d_offset_lockless(pgdp, *pgdp, address); 1432 } 1433 1434 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1435 { 1436 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1437 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1438 return (pud_t *) p4dp; 1439 } 1440 #define pud_offset_lockless pud_offset_lockless 1441 1442 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1443 { 1444 return pud_offset_lockless(p4dp, *p4dp, address); 1445 } 1446 #define pud_offset pud_offset 1447 1448 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1449 { 1450 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1451 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1452 return (pmd_t *) pudp; 1453 } 1454 #define pmd_offset_lockless pmd_offset_lockless 1455 1456 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1457 { 1458 return pmd_offset_lockless(pudp, *pudp, address); 1459 } 1460 #define pmd_offset pmd_offset 1461 1462 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1463 { 1464 return (unsigned long) pmd_deref(pmd); 1465 } 1466 1467 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1468 { 1469 return end <= current->mm->context.asce_limit; 1470 } 1471 #define gup_fast_permitted gup_fast_permitted 1472 1473 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1474 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1475 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1476 1477 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1478 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1479 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1480 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1481 1482 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1483 { 1484 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1485 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1486 } 1487 1488 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1489 { 1490 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1491 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1492 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1493 return pmd; 1494 } 1495 1496 static inline pmd_t pmd_mkclean(pmd_t pmd) 1497 { 1498 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1499 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1500 } 1501 1502 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1503 { 1504 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1505 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1506 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1507 return pmd; 1508 } 1509 1510 static inline pud_t pud_wrprotect(pud_t pud) 1511 { 1512 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1513 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1514 } 1515 1516 static inline pud_t pud_mkwrite(pud_t pud) 1517 { 1518 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1519 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1520 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1521 return pud; 1522 } 1523 1524 static inline pud_t pud_mkclean(pud_t pud) 1525 { 1526 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1527 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1528 } 1529 1530 static inline pud_t pud_mkdirty(pud_t pud) 1531 { 1532 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1533 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1534 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1535 return pud; 1536 } 1537 1538 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1539 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1540 { 1541 /* 1542 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1543 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1544 */ 1545 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1546 return pgprot_val(SEGMENT_NONE); 1547 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1548 return pgprot_val(SEGMENT_RO); 1549 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1550 return pgprot_val(SEGMENT_RX); 1551 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1552 return pgprot_val(SEGMENT_RW); 1553 return pgprot_val(SEGMENT_RWX); 1554 } 1555 1556 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1557 { 1558 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1559 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1560 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1561 return pmd; 1562 } 1563 1564 static inline pmd_t pmd_mkold(pmd_t pmd) 1565 { 1566 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1567 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1568 } 1569 1570 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1571 { 1572 unsigned long mask; 1573 1574 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1575 mask |= _SEGMENT_ENTRY_DIRTY; 1576 mask |= _SEGMENT_ENTRY_YOUNG; 1577 mask |= _SEGMENT_ENTRY_LARGE; 1578 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1579 pmd = __pmd(pmd_val(pmd) & mask); 1580 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1581 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1582 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1583 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1584 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1585 return pmd; 1586 } 1587 1588 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1589 { 1590 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1591 } 1592 1593 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1594 1595 static inline void __pmdp_csp(pmd_t *pmdp) 1596 { 1597 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1598 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1599 } 1600 1601 #define IDTE_GLOBAL 0 1602 #define IDTE_LOCAL 1 1603 1604 #define IDTE_PTOA 0x0800 1605 #define IDTE_NODAT 0x1000 1606 #define IDTE_GUEST_ASCE 0x2000 1607 1608 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1609 unsigned long opt, unsigned long asce, 1610 int local) 1611 { 1612 unsigned long sto; 1613 1614 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1615 if (__builtin_constant_p(opt) && opt == 0) { 1616 /* flush without guest asce */ 1617 asm volatile( 1618 " idte %[r1],0,%[r2],%[m4]" 1619 : "+m" (*pmdp) 1620 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1621 [m4] "i" (local) 1622 : "cc" ); 1623 } else { 1624 /* flush with guest asce */ 1625 asm volatile( 1626 " idte %[r1],%[r3],%[r2],%[m4]" 1627 : "+m" (*pmdp) 1628 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1629 [r3] "a" (asce), [m4] "i" (local) 1630 : "cc" ); 1631 } 1632 } 1633 1634 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1635 unsigned long opt, unsigned long asce, 1636 int local) 1637 { 1638 unsigned long r3o; 1639 1640 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1641 r3o |= _ASCE_TYPE_REGION3; 1642 if (__builtin_constant_p(opt) && opt == 0) { 1643 /* flush without guest asce */ 1644 asm volatile( 1645 " idte %[r1],0,%[r2],%[m4]" 1646 : "+m" (*pudp) 1647 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1648 [m4] "i" (local) 1649 : "cc"); 1650 } else { 1651 /* flush with guest asce */ 1652 asm volatile( 1653 " idte %[r1],%[r3],%[r2],%[m4]" 1654 : "+m" (*pudp) 1655 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1656 [r3] "a" (asce), [m4] "i" (local) 1657 : "cc" ); 1658 } 1659 } 1660 1661 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1662 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1663 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1664 1665 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1666 1667 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1668 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1669 pgtable_t pgtable); 1670 1671 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1672 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1673 1674 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1675 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1676 unsigned long addr, pmd_t *pmdp, 1677 pmd_t entry, int dirty) 1678 { 1679 VM_BUG_ON(addr & ~HPAGE_MASK); 1680 1681 entry = pmd_mkyoung(entry); 1682 if (dirty) 1683 entry = pmd_mkdirty(entry); 1684 if (pmd_val(*pmdp) == pmd_val(entry)) 1685 return 0; 1686 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1687 return 1; 1688 } 1689 1690 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1691 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1692 unsigned long addr, pmd_t *pmdp) 1693 { 1694 pmd_t pmd = *pmdp; 1695 1696 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1697 return pmd_young(pmd); 1698 } 1699 1700 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1701 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1702 unsigned long addr, pmd_t *pmdp) 1703 { 1704 VM_BUG_ON(addr & ~HPAGE_MASK); 1705 return pmdp_test_and_clear_young(vma, addr, pmdp); 1706 } 1707 1708 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1709 pmd_t *pmdp, pmd_t entry) 1710 { 1711 if (!MACHINE_HAS_NX) 1712 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1713 set_pmd(pmdp, entry); 1714 } 1715 1716 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1717 { 1718 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1719 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1720 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1721 } 1722 1723 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1724 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1725 unsigned long addr, pmd_t *pmdp) 1726 { 1727 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1728 } 1729 1730 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1731 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1732 unsigned long addr, 1733 pmd_t *pmdp, int full) 1734 { 1735 if (full) { 1736 pmd_t pmd = *pmdp; 1737 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1738 return pmd; 1739 } 1740 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1741 } 1742 1743 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1744 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1745 unsigned long addr, pmd_t *pmdp) 1746 { 1747 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1748 } 1749 1750 #define __HAVE_ARCH_PMDP_INVALIDATE 1751 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1752 unsigned long addr, pmd_t *pmdp) 1753 { 1754 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1755 1756 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1757 } 1758 1759 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1760 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1761 unsigned long addr, pmd_t *pmdp) 1762 { 1763 pmd_t pmd = *pmdp; 1764 1765 if (pmd_write(pmd)) 1766 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1767 } 1768 1769 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1770 unsigned long address, 1771 pmd_t *pmdp) 1772 { 1773 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1774 } 1775 #define pmdp_collapse_flush pmdp_collapse_flush 1776 1777 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1778 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1779 1780 static inline int pmd_trans_huge(pmd_t pmd) 1781 { 1782 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1783 } 1784 1785 #define has_transparent_hugepage has_transparent_hugepage 1786 static inline int has_transparent_hugepage(void) 1787 { 1788 return MACHINE_HAS_EDAT1 ? 1 : 0; 1789 } 1790 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1791 1792 /* 1793 * 64 bit swap entry format: 1794 * A page-table entry has some bits we have to treat in a special way. 1795 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1796 * as invalid. 1797 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1798 * | offset |E11XX|type |S0| 1799 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1800 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1801 * 1802 * Bits 0-51 store the offset. 1803 * Bit 52 (E) is used to remember PG_anon_exclusive. 1804 * Bits 57-61 store the type. 1805 * Bit 62 (S) is used for softdirty tracking. 1806 * Bits 55 and 56 (X) are unused. 1807 */ 1808 1809 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1810 #define __SWP_OFFSET_SHIFT 12 1811 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1812 #define __SWP_TYPE_SHIFT 2 1813 1814 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1815 { 1816 unsigned long pteval; 1817 1818 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1819 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1820 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1821 return __pte(pteval); 1822 } 1823 1824 static inline unsigned long __swp_type(swp_entry_t entry) 1825 { 1826 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1827 } 1828 1829 static inline unsigned long __swp_offset(swp_entry_t entry) 1830 { 1831 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1832 } 1833 1834 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1835 { 1836 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1837 } 1838 1839 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1840 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1841 1842 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1843 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1844 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1845 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1846 extern void vmem_unmap_4k_page(unsigned long addr); 1847 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1848 extern int s390_enable_sie(void); 1849 extern int s390_enable_skey(void); 1850 extern void s390_reset_cmma(struct mm_struct *mm); 1851 1852 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1853 #define HAVE_ARCH_UNMAPPED_AREA 1854 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1855 1856 #define pmd_pgtable(pmd) \ 1857 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1858 1859 #endif /* _S390_PAGE_H */ 1860