1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. For 16 * s390 31 bit we "fold" the mid level into the top-level page table, so 17 * that we physically have the same two-level page table as the s390 mmu 18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels 19 * the hardware provides (region first and region second tables are not 20 * used). 21 * 22 * The "pgd_xxx()" functions are trivial for a folded two-level 23 * setup: the pgd is never bad, and a pmd always exists (as it's folded 24 * into the pgd entry) 25 * 26 * This file contains the functions and defines necessary to modify and use 27 * the S390 page table tree. 28 */ 29 #ifndef __ASSEMBLY__ 30 #include <linux/sched.h> 31 #include <linux/mm_types.h> 32 #include <linux/page-flags.h> 33 #include <asm/bug.h> 34 #include <asm/page.h> 35 36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 37 extern void paging_init(void); 38 extern void vmem_map_init(void); 39 40 /* 41 * The S390 doesn't have any external MMU info: the kernel page 42 * tables contain all the necessary information. 43 */ 44 #define update_mmu_cache(vma, address, ptep) do { } while (0) 45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 46 47 /* 48 * ZERO_PAGE is a global shared page that is always zero; used 49 * for zero-mapped memory areas etc.. 50 */ 51 52 extern unsigned long empty_zero_page; 53 extern unsigned long zero_page_mask; 54 55 #define ZERO_PAGE(vaddr) \ 56 (virt_to_page((void *)(empty_zero_page + \ 57 (((unsigned long)(vaddr)) &zero_page_mask)))) 58 #define __HAVE_COLOR_ZERO_PAGE 59 60 /* TODO: s390 cannot support io_remap_pfn_range... */ 61 #endif /* !__ASSEMBLY__ */ 62 63 /* 64 * PMD_SHIFT determines the size of the area a second-level page 65 * table can map 66 * PGDIR_SHIFT determines what a third-level page table entry can map 67 */ 68 #ifndef CONFIG_64BIT 69 # define PMD_SHIFT 20 70 # define PUD_SHIFT 20 71 # define PGDIR_SHIFT 20 72 #else /* CONFIG_64BIT */ 73 # define PMD_SHIFT 20 74 # define PUD_SHIFT 31 75 # define PGDIR_SHIFT 42 76 #endif /* CONFIG_64BIT */ 77 78 #define PMD_SIZE (1UL << PMD_SHIFT) 79 #define PMD_MASK (~(PMD_SIZE-1)) 80 #define PUD_SIZE (1UL << PUD_SHIFT) 81 #define PUD_MASK (~(PUD_SIZE-1)) 82 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 83 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 84 85 /* 86 * entries per page directory level: the S390 is two-level, so 87 * we don't really have any PMD directory physically. 88 * for S390 segment-table entries are combined to one PGD 89 * that leads to 1024 pte per pgd 90 */ 91 #define PTRS_PER_PTE 256 92 #ifndef CONFIG_64BIT 93 #define PTRS_PER_PMD 1 94 #define PTRS_PER_PUD 1 95 #else /* CONFIG_64BIT */ 96 #define PTRS_PER_PMD 2048 97 #define PTRS_PER_PUD 2048 98 #endif /* CONFIG_64BIT */ 99 #define PTRS_PER_PGD 2048 100 101 #define FIRST_USER_ADDRESS 0 102 103 #define pte_ERROR(e) \ 104 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 105 #define pmd_ERROR(e) \ 106 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 107 #define pud_ERROR(e) \ 108 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 109 #define pgd_ERROR(e) \ 110 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 111 112 #ifndef __ASSEMBLY__ 113 /* 114 * The vmalloc and module area will always be on the topmost area of the kernel 115 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. 116 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 117 * modules will reside. That makes sure that inter module branches always 118 * happen without trampolines and in addition the placement within a 2GB frame 119 * is branch prediction unit friendly. 120 */ 121 extern unsigned long VMALLOC_START; 122 extern unsigned long VMALLOC_END; 123 extern struct page *vmemmap; 124 125 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 126 127 #ifdef CONFIG_64BIT 128 extern unsigned long MODULES_VADDR; 129 extern unsigned long MODULES_END; 130 #define MODULES_VADDR MODULES_VADDR 131 #define MODULES_END MODULES_END 132 #define MODULES_LEN (1UL << 31) 133 #endif 134 135 /* 136 * A 31 bit pagetable entry of S390 has following format: 137 * | PFRA | | OS | 138 * 0 0IP0 139 * 00000000001111111111222222222233 140 * 01234567890123456789012345678901 141 * 142 * I Page-Invalid Bit: Page is not available for address-translation 143 * P Page-Protection Bit: Store access not possible for page 144 * 145 * A 31 bit segmenttable entry of S390 has following format: 146 * | P-table origin | |PTL 147 * 0 IC 148 * 00000000001111111111222222222233 149 * 01234567890123456789012345678901 150 * 151 * I Segment-Invalid Bit: Segment is not available for address-translation 152 * C Common-Segment Bit: Segment is not private (PoP 3-30) 153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) 154 * 155 * The 31 bit segmenttable origin of S390 has following format: 156 * 157 * |S-table origin | | STL | 158 * X **GPS 159 * 00000000001111111111222222222233 160 * 01234567890123456789012345678901 161 * 162 * X Space-Switch event: 163 * G Segment-Invalid Bit: * 164 * P Private-Space Bit: Segment is not private (PoP 3-30) 165 * S Storage-Alteration: 166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) 167 * 168 * A 64 bit pagetable entry of S390 has following format: 169 * | PFRA |0IPC| OS | 170 * 0000000000111111111122222222223333333333444444444455555555556666 171 * 0123456789012345678901234567890123456789012345678901234567890123 172 * 173 * I Page-Invalid Bit: Page is not available for address-translation 174 * P Page-Protection Bit: Store access not possible for page 175 * C Change-bit override: HW is not required to set change bit 176 * 177 * A 64 bit segmenttable entry of S390 has following format: 178 * | P-table origin | TT 179 * 0000000000111111111122222222223333333333444444444455555555556666 180 * 0123456789012345678901234567890123456789012345678901234567890123 181 * 182 * I Segment-Invalid Bit: Segment is not available for address-translation 183 * C Common-Segment Bit: Segment is not private (PoP 3-30) 184 * P Page-Protection Bit: Store access not possible for page 185 * TT Type 00 186 * 187 * A 64 bit region table entry of S390 has following format: 188 * | S-table origin | TF TTTL 189 * 0000000000111111111122222222223333333333444444444455555555556666 190 * 0123456789012345678901234567890123456789012345678901234567890123 191 * 192 * I Segment-Invalid Bit: Segment is not available for address-translation 193 * TT Type 01 194 * TF 195 * TL Table length 196 * 197 * The 64 bit regiontable origin of S390 has following format: 198 * | region table origon | DTTL 199 * 0000000000111111111122222222223333333333444444444455555555556666 200 * 0123456789012345678901234567890123456789012345678901234567890123 201 * 202 * X Space-Switch event: 203 * G Segment-Invalid Bit: 204 * P Private-Space Bit: 205 * S Storage-Alteration: 206 * R Real space 207 * TL Table-Length: 208 * 209 * A storage key has the following format: 210 * | ACC |F|R|C|0| 211 * 0 3 4 5 6 7 212 * ACC: access key 213 * F : fetch protection bit 214 * R : referenced bit 215 * C : changed bit 216 */ 217 218 /* Hardware bits in the page table entry */ 219 #define _PAGE_CO 0x100 /* HW Change-bit override */ 220 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 221 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 222 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 223 224 /* Software bits in the page table entry */ 225 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 226 #define _PAGE_TYPE 0x002 /* SW pte type bit */ 227 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 228 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 229 #define _PAGE_READ 0x010 /* SW pte read bit */ 230 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 231 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 232 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 233 #define __HAVE_ARCH_PTE_SPECIAL 234 235 /* Set of bits not changed in pte_modify */ 236 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \ 237 _PAGE_DIRTY | _PAGE_YOUNG) 238 239 /* 240 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the 241 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit 242 * is used to distinguish present from not-present ptes. It is changed only 243 * with the page table lock held. 244 * 245 * The following table gives the different possible bit combinations for 246 * the pte hardware and software bits in the last 12 bits of a pte: 247 * 248 * 842100000000 249 * 000084210000 250 * 000000008421 251 * .IR...wrdytp 252 * empty .10...000000 253 * swap .10...xxxx10 254 * file .11...xxxxx0 255 * prot-none, clean, old .11...000001 256 * prot-none, clean, young .11...000101 257 * prot-none, dirty, old .10...001001 258 * prot-none, dirty, young .10...001101 259 * read-only, clean, old .11...010001 260 * read-only, clean, young .01...010101 261 * read-only, dirty, old .11...011001 262 * read-only, dirty, young .01...011101 263 * read-write, clean, old .11...110001 264 * read-write, clean, young .01...110101 265 * read-write, dirty, old .10...111001 266 * read-write, dirty, young .00...111101 267 * 268 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001 269 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400 270 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600 271 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402 272 */ 273 274 #ifndef CONFIG_64BIT 275 276 /* Bits in the segment table address-space-control-element */ 277 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ 278 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ 279 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 280 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 281 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ 282 283 /* Bits in the segment table entry */ 284 #define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */ 285 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ 286 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ 287 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 288 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ 289 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ 290 #define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_PROTECT 291 292 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) 293 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 294 295 /* 296 * Segment table entry encoding (I = invalid, R = read-only bit): 297 * ..R...I..... 298 * prot-none ..1...1..... 299 * read-only ..1...0..... 300 * read-write ..0...0..... 301 * empty ..0...1..... 302 */ 303 304 /* Page status table bits for virtualization */ 305 #define PGSTE_ACC_BITS 0xf0000000UL 306 #define PGSTE_FP_BIT 0x08000000UL 307 #define PGSTE_PCL_BIT 0x00800000UL 308 #define PGSTE_HR_BIT 0x00400000UL 309 #define PGSTE_HC_BIT 0x00200000UL 310 #define PGSTE_GR_BIT 0x00040000UL 311 #define PGSTE_GC_BIT 0x00020000UL 312 #define PGSTE_UC_BIT 0x00008000UL /* user dirty (migration) */ 313 #define PGSTE_IN_BIT 0x00004000UL /* IPTE notify bit */ 314 315 #else /* CONFIG_64BIT */ 316 317 /* Bits in the segment/region table address-space-control-element */ 318 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 319 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 320 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 321 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 322 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 323 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 324 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 325 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 326 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 327 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 328 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 329 330 /* Bits in the region table entry */ 331 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 332 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 333 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 334 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 335 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 336 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 337 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 338 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 339 340 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 341 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 342 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 343 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 344 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 345 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 346 347 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ 348 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ 349 #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ 350 351 /* Bits in the segment table entry */ 352 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 353 #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff1ff33UL 354 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 355 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 356 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ 357 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 358 359 #define _SEGMENT_ENTRY (0) 360 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 361 362 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ 363 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ 364 #define _SEGMENT_ENTRY_SPLIT 0x001 /* THP splitting bit */ 365 #define _SEGMENT_ENTRY_YOUNG 0x002 /* SW segment young bit */ 366 #define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_YOUNG 367 368 /* 369 * Segment table entry encoding (R = read-only, I = invalid, y = young bit): 370 * ..R...I...y. 371 * prot-none, old ..0...1...1. 372 * prot-none, young ..1...1...1. 373 * read-only, old ..1...1...0. 374 * read-only, young ..1...0...1. 375 * read-write, old ..0...1...0. 376 * read-write, young ..0...0...1. 377 * The segment table origin is used to distinguish empty (origin==0) from 378 * read-write, old segment table entries (origin!=0) 379 */ 380 381 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ 382 383 /* Set of bits not changed in pmd_modify */ 384 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ 385 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) 386 387 /* Page status table bits for virtualization */ 388 #define PGSTE_ACC_BITS 0xf000000000000000UL 389 #define PGSTE_FP_BIT 0x0800000000000000UL 390 #define PGSTE_PCL_BIT 0x0080000000000000UL 391 #define PGSTE_HR_BIT 0x0040000000000000UL 392 #define PGSTE_HC_BIT 0x0020000000000000UL 393 #define PGSTE_GR_BIT 0x0004000000000000UL 394 #define PGSTE_GC_BIT 0x0002000000000000UL 395 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 396 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 397 398 #endif /* CONFIG_64BIT */ 399 400 /* Guest Page State used for virtualization */ 401 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 402 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 403 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 404 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 405 406 /* 407 * A user page table pointer has the space-switch-event bit, the 408 * private-space-control bit and the storage-alteration-event-control 409 * bit set. A kernel page table pointer doesn't need them. 410 */ 411 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 412 _ASCE_ALT_EVENT) 413 414 /* 415 * Page protection definitions. 416 */ 417 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) 418 #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 419 _PAGE_INVALID | _PAGE_PROTECT) 420 #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 421 _PAGE_INVALID | _PAGE_PROTECT) 422 423 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 424 _PAGE_YOUNG | _PAGE_DIRTY) 425 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 426 _PAGE_YOUNG | _PAGE_DIRTY) 427 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 428 _PAGE_PROTECT) 429 430 /* 431 * On s390 the page table entry has an invalid bit and a read-only bit. 432 * Read permission implies execute permission and write permission 433 * implies read permission. 434 */ 435 /*xwr*/ 436 #define __P000 PAGE_NONE 437 #define __P001 PAGE_READ 438 #define __P010 PAGE_READ 439 #define __P011 PAGE_READ 440 #define __P100 PAGE_READ 441 #define __P101 PAGE_READ 442 #define __P110 PAGE_READ 443 #define __P111 PAGE_READ 444 445 #define __S000 PAGE_NONE 446 #define __S001 PAGE_READ 447 #define __S010 PAGE_WRITE 448 #define __S011 PAGE_WRITE 449 #define __S100 PAGE_READ 450 #define __S101 PAGE_READ 451 #define __S110 PAGE_WRITE 452 #define __S111 PAGE_WRITE 453 454 /* 455 * Segment entry (large page) protection definitions. 456 */ 457 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 458 _SEGMENT_ENTRY_NONE) 459 #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_INVALID | \ 460 _SEGMENT_ENTRY_PROTECT) 461 #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_INVALID) 462 463 static inline int mm_has_pgste(struct mm_struct *mm) 464 { 465 #ifdef CONFIG_PGSTE 466 if (unlikely(mm->context.has_pgste)) 467 return 1; 468 #endif 469 return 0; 470 } 471 472 static inline int mm_use_skey(struct mm_struct *mm) 473 { 474 #ifdef CONFIG_PGSTE 475 if (mm->context.use_skey) 476 return 1; 477 #endif 478 return 0; 479 } 480 481 /* 482 * pgd/pmd/pte query functions 483 */ 484 #ifndef CONFIG_64BIT 485 486 static inline int pgd_present(pgd_t pgd) { return 1; } 487 static inline int pgd_none(pgd_t pgd) { return 0; } 488 static inline int pgd_bad(pgd_t pgd) { return 0; } 489 490 static inline int pud_present(pud_t pud) { return 1; } 491 static inline int pud_none(pud_t pud) { return 0; } 492 static inline int pud_large(pud_t pud) { return 0; } 493 static inline int pud_bad(pud_t pud) { return 0; } 494 495 #else /* CONFIG_64BIT */ 496 497 static inline int pgd_present(pgd_t pgd) 498 { 499 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 500 return 1; 501 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 502 } 503 504 static inline int pgd_none(pgd_t pgd) 505 { 506 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 507 return 0; 508 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 509 } 510 511 static inline int pgd_bad(pgd_t pgd) 512 { 513 /* 514 * With dynamic page table levels the pgd can be a region table 515 * entry or a segment table entry. Check for the bit that are 516 * invalid for either table entry. 517 */ 518 unsigned long mask = 519 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & 520 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 521 return (pgd_val(pgd) & mask) != 0; 522 } 523 524 static inline int pud_present(pud_t pud) 525 { 526 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 527 return 1; 528 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 529 } 530 531 static inline int pud_none(pud_t pud) 532 { 533 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 534 return 0; 535 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; 536 } 537 538 static inline int pud_large(pud_t pud) 539 { 540 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 541 return 0; 542 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 543 } 544 545 static inline int pud_bad(pud_t pud) 546 { 547 /* 548 * With dynamic page table levels the pud can be a region table 549 * entry or a segment table entry. Check for the bit that are 550 * invalid for either table entry. 551 */ 552 unsigned long mask = 553 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & 554 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 555 return (pud_val(pud) & mask) != 0; 556 } 557 558 #endif /* CONFIG_64BIT */ 559 560 static inline int pmd_present(pmd_t pmd) 561 { 562 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; 563 } 564 565 static inline int pmd_none(pmd_t pmd) 566 { 567 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; 568 } 569 570 static inline int pmd_large(pmd_t pmd) 571 { 572 #ifdef CONFIG_64BIT 573 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 574 #else 575 return 0; 576 #endif 577 } 578 579 static inline int pmd_prot_none(pmd_t pmd) 580 { 581 return (pmd_val(pmd) & _SEGMENT_ENTRY_INVALID) && 582 (pmd_val(pmd) & _SEGMENT_ENTRY_NONE); 583 } 584 585 static inline int pmd_bad(pmd_t pmd) 586 { 587 #ifdef CONFIG_64BIT 588 if (pmd_large(pmd)) 589 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; 590 #endif 591 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 592 } 593 594 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 595 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 596 unsigned long addr, pmd_t *pmdp); 597 598 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 599 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 600 unsigned long address, pmd_t *pmdp, 601 pmd_t entry, int dirty); 602 603 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 604 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 605 unsigned long address, pmd_t *pmdp); 606 607 #define __HAVE_ARCH_PMD_WRITE 608 static inline int pmd_write(pmd_t pmd) 609 { 610 if (pmd_prot_none(pmd)) 611 return 0; 612 return (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) == 0; 613 } 614 615 static inline int pmd_young(pmd_t pmd) 616 { 617 int young = 0; 618 #ifdef CONFIG_64BIT 619 if (pmd_prot_none(pmd)) 620 young = (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) != 0; 621 else 622 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 623 #endif 624 return young; 625 } 626 627 static inline int pte_present(pte_t pte) 628 { 629 /* Bit pattern: (pte & 0x001) == 0x001 */ 630 return (pte_val(pte) & _PAGE_PRESENT) != 0; 631 } 632 633 static inline int pte_none(pte_t pte) 634 { 635 /* Bit pattern: pte == 0x400 */ 636 return pte_val(pte) == _PAGE_INVALID; 637 } 638 639 static inline int pte_swap(pte_t pte) 640 { 641 /* Bit pattern: (pte & 0x603) == 0x402 */ 642 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | 643 _PAGE_TYPE | _PAGE_PRESENT)) 644 == (_PAGE_INVALID | _PAGE_TYPE); 645 } 646 647 static inline int pte_file(pte_t pte) 648 { 649 /* Bit pattern: (pte & 0x601) == 0x600 */ 650 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT)) 651 == (_PAGE_INVALID | _PAGE_PROTECT); 652 } 653 654 static inline int pte_special(pte_t pte) 655 { 656 return (pte_val(pte) & _PAGE_SPECIAL); 657 } 658 659 #define __HAVE_ARCH_PTE_SAME 660 static inline int pte_same(pte_t a, pte_t b) 661 { 662 return pte_val(a) == pte_val(b); 663 } 664 665 static inline pgste_t pgste_get_lock(pte_t *ptep) 666 { 667 unsigned long new = 0; 668 #ifdef CONFIG_PGSTE 669 unsigned long old; 670 671 preempt_disable(); 672 asm( 673 " lg %0,%2\n" 674 "0: lgr %1,%0\n" 675 " nihh %0,0xff7f\n" /* clear PCL bit in old */ 676 " oihh %1,0x0080\n" /* set PCL bit in new */ 677 " csg %0,%1,%2\n" 678 " jl 0b\n" 679 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 680 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); 681 #endif 682 return __pgste(new); 683 } 684 685 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 686 { 687 #ifdef CONFIG_PGSTE 688 asm( 689 " nihh %1,0xff7f\n" /* clear PCL bit */ 690 " stg %1,%0\n" 691 : "=Q" (ptep[PTRS_PER_PTE]) 692 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) 693 : "cc", "memory"); 694 preempt_enable(); 695 #endif 696 } 697 698 static inline pgste_t pgste_get(pte_t *ptep) 699 { 700 unsigned long pgste = 0; 701 #ifdef CONFIG_PGSTE 702 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); 703 #endif 704 return __pgste(pgste); 705 } 706 707 static inline void pgste_set(pte_t *ptep, pgste_t pgste) 708 { 709 #ifdef CONFIG_PGSTE 710 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; 711 #endif 712 } 713 714 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, 715 struct mm_struct *mm) 716 { 717 #ifdef CONFIG_PGSTE 718 unsigned long address, bits, skey; 719 720 if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) 721 return pgste; 722 address = pte_val(*ptep) & PAGE_MASK; 723 skey = (unsigned long) page_get_storage_key(address); 724 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 725 /* Transfer page changed & referenced bit to guest bits in pgste */ 726 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ 727 /* Copy page access key and fetch protection bit to pgste */ 728 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); 729 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 730 #endif 731 return pgste; 732 733 } 734 735 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, 736 struct mm_struct *mm) 737 { 738 #ifdef CONFIG_PGSTE 739 unsigned long address; 740 unsigned long nkey; 741 742 if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) 743 return; 744 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); 745 address = pte_val(entry) & PAGE_MASK; 746 /* 747 * Set page access key and fetch protection bit from pgste. 748 * The guest C/R information is still in the PGSTE, set real 749 * key C/R to 0. 750 */ 751 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; 752 nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; 753 page_set_storage_key(address, nkey, 0); 754 #endif 755 } 756 757 static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) 758 { 759 if ((pte_val(entry) & _PAGE_PRESENT) && 760 (pte_val(entry) & _PAGE_WRITE) && 761 !(pte_val(entry) & _PAGE_INVALID)) { 762 if (!MACHINE_HAS_ESOP) { 763 /* 764 * Without enhanced suppression-on-protection force 765 * the dirty bit on for all writable ptes. 766 */ 767 pte_val(entry) |= _PAGE_DIRTY; 768 pte_val(entry) &= ~_PAGE_PROTECT; 769 } 770 if (!(pte_val(entry) & _PAGE_PROTECT)) 771 /* This pte allows write access, set user-dirty */ 772 pgste_val(pgste) |= PGSTE_UC_BIT; 773 } 774 *ptep = entry; 775 return pgste; 776 } 777 778 /** 779 * struct gmap_struct - guest address space 780 * @mm: pointer to the parent mm_struct 781 * @table: pointer to the page directory 782 * @asce: address space control element for gmap page table 783 * @crst_list: list of all crst tables used in the guest address space 784 * @pfault_enabled: defines if pfaults are applicable for the guest 785 */ 786 struct gmap { 787 struct list_head list; 788 struct mm_struct *mm; 789 unsigned long *table; 790 unsigned long asce; 791 void *private; 792 struct list_head crst_list; 793 bool pfault_enabled; 794 }; 795 796 /** 797 * struct gmap_rmap - reverse mapping for segment table entries 798 * @gmap: pointer to the gmap_struct 799 * @entry: pointer to a segment table entry 800 * @vmaddr: virtual address in the guest address space 801 */ 802 struct gmap_rmap { 803 struct list_head list; 804 struct gmap *gmap; 805 unsigned long *entry; 806 unsigned long vmaddr; 807 }; 808 809 /** 810 * struct gmap_pgtable - gmap information attached to a page table 811 * @vmaddr: address of the 1MB segment in the process virtual memory 812 * @mapper: list of segment table entries mapping a page table 813 */ 814 struct gmap_pgtable { 815 unsigned long vmaddr; 816 struct list_head mapper; 817 }; 818 819 /** 820 * struct gmap_notifier - notify function block for page invalidation 821 * @notifier_call: address of callback function 822 */ 823 struct gmap_notifier { 824 struct list_head list; 825 void (*notifier_call)(struct gmap *gmap, unsigned long address); 826 }; 827 828 struct gmap *gmap_alloc(struct mm_struct *mm); 829 void gmap_free(struct gmap *gmap); 830 void gmap_enable(struct gmap *gmap); 831 void gmap_disable(struct gmap *gmap); 832 int gmap_map_segment(struct gmap *gmap, unsigned long from, 833 unsigned long to, unsigned long len); 834 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 835 unsigned long __gmap_translate(unsigned long address, struct gmap *); 836 unsigned long gmap_translate(unsigned long address, struct gmap *); 837 unsigned long __gmap_fault(unsigned long address, struct gmap *); 838 unsigned long gmap_fault(unsigned long address, struct gmap *); 839 void gmap_discard(unsigned long from, unsigned long to, struct gmap *); 840 void __gmap_zap(unsigned long address, struct gmap *); 841 bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); 842 843 844 void gmap_register_ipte_notifier(struct gmap_notifier *); 845 void gmap_unregister_ipte_notifier(struct gmap_notifier *); 846 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); 847 void gmap_do_ipte_notify(struct mm_struct *, pte_t *); 848 849 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, 850 pte_t *ptep, pgste_t pgste) 851 { 852 #ifdef CONFIG_PGSTE 853 if (pgste_val(pgste) & PGSTE_IN_BIT) { 854 pgste_val(pgste) &= ~PGSTE_IN_BIT; 855 gmap_do_ipte_notify(mm, ptep); 856 } 857 #endif 858 return pgste; 859 } 860 861 /* 862 * Certain architectures need to do special things when PTEs 863 * within a page table are directly modified. Thus, the following 864 * hook is made available. 865 */ 866 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 867 pte_t *ptep, pte_t entry) 868 { 869 pgste_t pgste; 870 871 if (mm_has_pgste(mm)) { 872 pgste = pgste_get_lock(ptep); 873 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; 874 pgste_set_key(ptep, pgste, entry, mm); 875 pgste = pgste_set_pte(ptep, pgste, entry); 876 pgste_set_unlock(ptep, pgste); 877 } else { 878 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) 879 pte_val(entry) |= _PAGE_CO; 880 *ptep = entry; 881 } 882 } 883 884 /* 885 * query functions pte_write/pte_dirty/pte_young only work if 886 * pte_present() is true. Undefined behaviour if not.. 887 */ 888 static inline int pte_write(pte_t pte) 889 { 890 return (pte_val(pte) & _PAGE_WRITE) != 0; 891 } 892 893 static inline int pte_dirty(pte_t pte) 894 { 895 return (pte_val(pte) & _PAGE_DIRTY) != 0; 896 } 897 898 static inline int pte_young(pte_t pte) 899 { 900 return (pte_val(pte) & _PAGE_YOUNG) != 0; 901 } 902 903 #define __HAVE_ARCH_PTE_UNUSED 904 static inline int pte_unused(pte_t pte) 905 { 906 return pte_val(pte) & _PAGE_UNUSED; 907 } 908 909 /* 910 * pgd/pmd/pte modification functions 911 */ 912 913 static inline void pgd_clear(pgd_t *pgd) 914 { 915 #ifdef CONFIG_64BIT 916 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 917 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 918 #endif 919 } 920 921 static inline void pud_clear(pud_t *pud) 922 { 923 #ifdef CONFIG_64BIT 924 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 925 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 926 #endif 927 } 928 929 static inline void pmd_clear(pmd_t *pmdp) 930 { 931 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; 932 } 933 934 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 935 { 936 pte_val(*ptep) = _PAGE_INVALID; 937 } 938 939 /* 940 * The following pte modification functions only work if 941 * pte_present() is true. Undefined behaviour if not.. 942 */ 943 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 944 { 945 pte_val(pte) &= _PAGE_CHG_MASK; 946 pte_val(pte) |= pgprot_val(newprot); 947 /* 948 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the 949 * invalid bit set, clear it again for readable, young pages 950 */ 951 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 952 pte_val(pte) &= ~_PAGE_INVALID; 953 /* 954 * newprot for PAGE_READ and PAGE_WRITE has the page protection 955 * bit set, clear it again for writable, dirty pages 956 */ 957 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 958 pte_val(pte) &= ~_PAGE_PROTECT; 959 return pte; 960 } 961 962 static inline pte_t pte_wrprotect(pte_t pte) 963 { 964 pte_val(pte) &= ~_PAGE_WRITE; 965 pte_val(pte) |= _PAGE_PROTECT; 966 return pte; 967 } 968 969 static inline pte_t pte_mkwrite(pte_t pte) 970 { 971 pte_val(pte) |= _PAGE_WRITE; 972 if (pte_val(pte) & _PAGE_DIRTY) 973 pte_val(pte) &= ~_PAGE_PROTECT; 974 return pte; 975 } 976 977 static inline pte_t pte_mkclean(pte_t pte) 978 { 979 pte_val(pte) &= ~_PAGE_DIRTY; 980 pte_val(pte) |= _PAGE_PROTECT; 981 return pte; 982 } 983 984 static inline pte_t pte_mkdirty(pte_t pte) 985 { 986 pte_val(pte) |= _PAGE_DIRTY; 987 if (pte_val(pte) & _PAGE_WRITE) 988 pte_val(pte) &= ~_PAGE_PROTECT; 989 return pte; 990 } 991 992 static inline pte_t pte_mkold(pte_t pte) 993 { 994 pte_val(pte) &= ~_PAGE_YOUNG; 995 pte_val(pte) |= _PAGE_INVALID; 996 return pte; 997 } 998 999 static inline pte_t pte_mkyoung(pte_t pte) 1000 { 1001 pte_val(pte) |= _PAGE_YOUNG; 1002 if (pte_val(pte) & _PAGE_READ) 1003 pte_val(pte) &= ~_PAGE_INVALID; 1004 return pte; 1005 } 1006 1007 static inline pte_t pte_mkspecial(pte_t pte) 1008 { 1009 pte_val(pte) |= _PAGE_SPECIAL; 1010 return pte; 1011 } 1012 1013 #ifdef CONFIG_HUGETLB_PAGE 1014 static inline pte_t pte_mkhuge(pte_t pte) 1015 { 1016 pte_val(pte) |= _PAGE_LARGE; 1017 return pte; 1018 } 1019 #endif 1020 1021 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 1022 { 1023 unsigned long pto = (unsigned long) ptep; 1024 1025 #ifndef CONFIG_64BIT 1026 /* pto in ESA mode must point to the start of the segment table */ 1027 pto &= 0x7ffffc00; 1028 #endif 1029 /* Invalidation + global TLB flush for the pte */ 1030 asm volatile( 1031 " ipte %2,%3" 1032 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); 1033 } 1034 1035 static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) 1036 { 1037 unsigned long pto = (unsigned long) ptep; 1038 1039 #ifndef CONFIG_64BIT 1040 /* pto in ESA mode must point to the start of the segment table */ 1041 pto &= 0x7ffffc00; 1042 #endif 1043 /* Invalidation + local TLB flush for the pte */ 1044 asm volatile( 1045 " .insn rrf,0xb2210000,%2,%3,0,1" 1046 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); 1047 } 1048 1049 static inline void ptep_flush_direct(struct mm_struct *mm, 1050 unsigned long address, pte_t *ptep) 1051 { 1052 int active, count; 1053 1054 if (pte_val(*ptep) & _PAGE_INVALID) 1055 return; 1056 active = (mm == current->active_mm) ? 1 : 0; 1057 count = atomic_add_return(0x10000, &mm->context.attach_count); 1058 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && 1059 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) 1060 __ptep_ipte_local(address, ptep); 1061 else 1062 __ptep_ipte(address, ptep); 1063 atomic_sub(0x10000, &mm->context.attach_count); 1064 } 1065 1066 static inline void ptep_flush_lazy(struct mm_struct *mm, 1067 unsigned long address, pte_t *ptep) 1068 { 1069 int active, count; 1070 1071 if (pte_val(*ptep) & _PAGE_INVALID) 1072 return; 1073 active = (mm == current->active_mm) ? 1 : 0; 1074 count = atomic_add_return(0x10000, &mm->context.attach_count); 1075 if ((count & 0xffff) <= active) { 1076 pte_val(*ptep) |= _PAGE_INVALID; 1077 mm->context.flush_mm = 1; 1078 } else 1079 __ptep_ipte(address, ptep); 1080 atomic_sub(0x10000, &mm->context.attach_count); 1081 } 1082 1083 /* 1084 * Get (and clear) the user dirty bit for a pte. 1085 */ 1086 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 1087 unsigned long addr, 1088 pte_t *ptep) 1089 { 1090 pgste_t pgste; 1091 pte_t pte; 1092 int dirty; 1093 1094 if (!mm_has_pgste(mm)) 1095 return 0; 1096 pgste = pgste_get_lock(ptep); 1097 dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); 1098 pgste_val(pgste) &= ~PGSTE_UC_BIT; 1099 pte = *ptep; 1100 if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { 1101 pgste = pgste_ipte_notify(mm, ptep, pgste); 1102 __ptep_ipte(addr, ptep); 1103 if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) 1104 pte_val(pte) |= _PAGE_PROTECT; 1105 else 1106 pte_val(pte) |= _PAGE_INVALID; 1107 *ptep = pte; 1108 } 1109 pgste_set_unlock(ptep, pgste); 1110 return dirty; 1111 } 1112 1113 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1114 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1115 unsigned long addr, pte_t *ptep) 1116 { 1117 pgste_t pgste; 1118 pte_t pte; 1119 int young; 1120 1121 if (mm_has_pgste(vma->vm_mm)) { 1122 pgste = pgste_get_lock(ptep); 1123 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste); 1124 } 1125 1126 pte = *ptep; 1127 ptep_flush_direct(vma->vm_mm, addr, ptep); 1128 young = pte_young(pte); 1129 pte = pte_mkold(pte); 1130 1131 if (mm_has_pgste(vma->vm_mm)) { 1132 pgste = pgste_set_pte(ptep, pgste, pte); 1133 pgste_set_unlock(ptep, pgste); 1134 } else 1135 *ptep = pte; 1136 1137 return young; 1138 } 1139 1140 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1141 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1142 unsigned long address, pte_t *ptep) 1143 { 1144 return ptep_test_and_clear_young(vma, address, ptep); 1145 } 1146 1147 /* 1148 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1149 * both clear the TLB for the unmapped pte. The reason is that 1150 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1151 * to modify an active pte. The sequence is 1152 * 1) ptep_get_and_clear 1153 * 2) set_pte_at 1154 * 3) flush_tlb_range 1155 * On s390 the tlb needs to get flushed with the modification of the pte 1156 * if the pte is active. The only way how this can be implemented is to 1157 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1158 * is a nop. 1159 */ 1160 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1161 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1162 unsigned long address, pte_t *ptep) 1163 { 1164 pgste_t pgste; 1165 pte_t pte; 1166 1167 if (mm_has_pgste(mm)) { 1168 pgste = pgste_get_lock(ptep); 1169 pgste = pgste_ipte_notify(mm, ptep, pgste); 1170 } 1171 1172 pte = *ptep; 1173 ptep_flush_lazy(mm, address, ptep); 1174 pte_val(*ptep) = _PAGE_INVALID; 1175 1176 if (mm_has_pgste(mm)) { 1177 pgste = pgste_update_all(&pte, pgste, mm); 1178 pgste_set_unlock(ptep, pgste); 1179 } 1180 return pte; 1181 } 1182 1183 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1184 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1185 unsigned long address, 1186 pte_t *ptep) 1187 { 1188 pgste_t pgste; 1189 pte_t pte; 1190 1191 if (mm_has_pgste(mm)) { 1192 pgste = pgste_get_lock(ptep); 1193 pgste_ipte_notify(mm, ptep, pgste); 1194 } 1195 1196 pte = *ptep; 1197 ptep_flush_lazy(mm, address, ptep); 1198 1199 if (mm_has_pgste(mm)) { 1200 pgste = pgste_update_all(&pte, pgste, mm); 1201 pgste_set(ptep, pgste); 1202 } 1203 return pte; 1204 } 1205 1206 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1207 unsigned long address, 1208 pte_t *ptep, pte_t pte) 1209 { 1210 pgste_t pgste; 1211 1212 if (mm_has_pgste(mm)) { 1213 pgste = pgste_get(ptep); 1214 pgste_set_key(ptep, pgste, pte, mm); 1215 pgste = pgste_set_pte(ptep, pgste, pte); 1216 pgste_set_unlock(ptep, pgste); 1217 } else 1218 *ptep = pte; 1219 } 1220 1221 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1222 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1223 unsigned long address, pte_t *ptep) 1224 { 1225 pgste_t pgste; 1226 pte_t pte; 1227 1228 if (mm_has_pgste(vma->vm_mm)) { 1229 pgste = pgste_get_lock(ptep); 1230 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste); 1231 } 1232 1233 pte = *ptep; 1234 ptep_flush_direct(vma->vm_mm, address, ptep); 1235 pte_val(*ptep) = _PAGE_INVALID; 1236 1237 if (mm_has_pgste(vma->vm_mm)) { 1238 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == 1239 _PGSTE_GPS_USAGE_UNUSED) 1240 pte_val(pte) |= _PAGE_UNUSED; 1241 pgste = pgste_update_all(&pte, pgste, vma->vm_mm); 1242 pgste_set_unlock(ptep, pgste); 1243 } 1244 return pte; 1245 } 1246 1247 /* 1248 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1249 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1250 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1251 * cannot be accessed while the batched unmap is running. In this case 1252 * full==1 and a simple pte_clear is enough. See tlb.h. 1253 */ 1254 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1255 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1256 unsigned long address, 1257 pte_t *ptep, int full) 1258 { 1259 pgste_t pgste; 1260 pte_t pte; 1261 1262 if (!full && mm_has_pgste(mm)) { 1263 pgste = pgste_get_lock(ptep); 1264 pgste = pgste_ipte_notify(mm, ptep, pgste); 1265 } 1266 1267 pte = *ptep; 1268 if (!full) 1269 ptep_flush_lazy(mm, address, ptep); 1270 pte_val(*ptep) = _PAGE_INVALID; 1271 1272 if (!full && mm_has_pgste(mm)) { 1273 pgste = pgste_update_all(&pte, pgste, mm); 1274 pgste_set_unlock(ptep, pgste); 1275 } 1276 return pte; 1277 } 1278 1279 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1280 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1281 unsigned long address, pte_t *ptep) 1282 { 1283 pgste_t pgste; 1284 pte_t pte = *ptep; 1285 1286 if (pte_write(pte)) { 1287 if (mm_has_pgste(mm)) { 1288 pgste = pgste_get_lock(ptep); 1289 pgste = pgste_ipte_notify(mm, ptep, pgste); 1290 } 1291 1292 ptep_flush_lazy(mm, address, ptep); 1293 pte = pte_wrprotect(pte); 1294 1295 if (mm_has_pgste(mm)) { 1296 pgste = pgste_set_pte(ptep, pgste, pte); 1297 pgste_set_unlock(ptep, pgste); 1298 } else 1299 *ptep = pte; 1300 } 1301 return pte; 1302 } 1303 1304 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1305 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1306 unsigned long address, pte_t *ptep, 1307 pte_t entry, int dirty) 1308 { 1309 pgste_t pgste; 1310 1311 if (pte_same(*ptep, entry)) 1312 return 0; 1313 if (mm_has_pgste(vma->vm_mm)) { 1314 pgste = pgste_get_lock(ptep); 1315 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste); 1316 } 1317 1318 ptep_flush_direct(vma->vm_mm, address, ptep); 1319 1320 if (mm_has_pgste(vma->vm_mm)) { 1321 pgste = pgste_set_pte(ptep, pgste, entry); 1322 pgste_set_unlock(ptep, pgste); 1323 } else 1324 *ptep = entry; 1325 return 1; 1326 } 1327 1328 /* 1329 * Conversion functions: convert a page and protection to a page entry, 1330 * and a page entry and page directory to the page they refer to. 1331 */ 1332 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1333 { 1334 pte_t __pte; 1335 pte_val(__pte) = physpage + pgprot_val(pgprot); 1336 return pte_mkyoung(__pte); 1337 } 1338 1339 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1340 { 1341 unsigned long physpage = page_to_phys(page); 1342 pte_t __pte = mk_pte_phys(physpage, pgprot); 1343 1344 if (pte_write(__pte) && PageDirty(page)) 1345 __pte = pte_mkdirty(__pte); 1346 return __pte; 1347 } 1348 1349 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1350 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1351 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1352 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1353 1354 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1355 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1356 1357 #ifndef CONFIG_64BIT 1358 1359 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1360 #define pud_deref(pmd) ({ BUG(); 0UL; }) 1361 #define pgd_deref(pmd) ({ BUG(); 0UL; }) 1362 1363 #define pud_offset(pgd, address) ((pud_t *) pgd) 1364 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) 1365 1366 #else /* CONFIG_64BIT */ 1367 1368 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1369 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1370 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1371 1372 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1373 { 1374 pud_t *pud = (pud_t *) pgd; 1375 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1376 pud = (pud_t *) pgd_deref(*pgd); 1377 return pud + pud_index(address); 1378 } 1379 1380 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1381 { 1382 pmd_t *pmd = (pmd_t *) pud; 1383 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1384 pmd = (pmd_t *) pud_deref(*pud); 1385 return pmd + pmd_index(address); 1386 } 1387 1388 #endif /* CONFIG_64BIT */ 1389 1390 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1391 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1392 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1393 1394 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 1395 1396 /* Find an entry in the lowest level page table.. */ 1397 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1398 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1399 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1400 #define pte_unmap(pte) do { } while (0) 1401 1402 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1403 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1404 { 1405 /* 1406 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) 1407 * Convert to segment table entry format. 1408 */ 1409 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1410 return pgprot_val(SEGMENT_NONE); 1411 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) 1412 return pgprot_val(SEGMENT_READ); 1413 return pgprot_val(SEGMENT_WRITE); 1414 } 1415 1416 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1417 { 1418 #ifdef CONFIG_64BIT 1419 if (pmd_prot_none(pmd)) { 1420 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1421 } else { 1422 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1423 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; 1424 } 1425 #endif 1426 return pmd; 1427 } 1428 1429 static inline pmd_t pmd_mkold(pmd_t pmd) 1430 { 1431 #ifdef CONFIG_64BIT 1432 if (pmd_prot_none(pmd)) { 1433 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1434 } else { 1435 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; 1436 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1437 } 1438 #endif 1439 return pmd; 1440 } 1441 1442 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1443 { 1444 int young; 1445 1446 young = pmd_young(pmd); 1447 pmd_val(pmd) &= _SEGMENT_CHG_MASK; 1448 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1449 if (young) 1450 pmd = pmd_mkyoung(pmd); 1451 return pmd; 1452 } 1453 1454 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1455 { 1456 pmd_t __pmd; 1457 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1458 return pmd_mkyoung(__pmd); 1459 } 1460 1461 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1462 { 1463 /* Do not clobber PROT_NONE segments! */ 1464 if (!pmd_prot_none(pmd)) 1465 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1466 return pmd; 1467 } 1468 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1469 1470 static inline void __pmdp_csp(pmd_t *pmdp) 1471 { 1472 register unsigned long reg2 asm("2") = pmd_val(*pmdp); 1473 register unsigned long reg3 asm("3") = pmd_val(*pmdp) | 1474 _SEGMENT_ENTRY_INVALID; 1475 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; 1476 1477 asm volatile( 1478 " csp %1,%3" 1479 : "=m" (*pmdp) 1480 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); 1481 } 1482 1483 static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) 1484 { 1485 unsigned long sto; 1486 1487 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); 1488 asm volatile( 1489 " .insn rrf,0xb98e0000,%2,%3,0,0" 1490 : "=m" (*pmdp) 1491 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) 1492 : "cc" ); 1493 } 1494 1495 static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) 1496 { 1497 unsigned long sto; 1498 1499 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); 1500 asm volatile( 1501 " .insn rrf,0xb98e0000,%2,%3,0,1" 1502 : "=m" (*pmdp) 1503 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) 1504 : "cc" ); 1505 } 1506 1507 static inline void pmdp_flush_direct(struct mm_struct *mm, 1508 unsigned long address, pmd_t *pmdp) 1509 { 1510 int active, count; 1511 1512 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) 1513 return; 1514 if (!MACHINE_HAS_IDTE) { 1515 __pmdp_csp(pmdp); 1516 return; 1517 } 1518 active = (mm == current->active_mm) ? 1 : 0; 1519 count = atomic_add_return(0x10000, &mm->context.attach_count); 1520 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && 1521 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) 1522 __pmdp_idte_local(address, pmdp); 1523 else 1524 __pmdp_idte(address, pmdp); 1525 atomic_sub(0x10000, &mm->context.attach_count); 1526 } 1527 1528 static inline void pmdp_flush_lazy(struct mm_struct *mm, 1529 unsigned long address, pmd_t *pmdp) 1530 { 1531 int active, count; 1532 1533 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) 1534 return; 1535 active = (mm == current->active_mm) ? 1 : 0; 1536 count = atomic_add_return(0x10000, &mm->context.attach_count); 1537 if ((count & 0xffff) <= active) { 1538 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID; 1539 mm->context.flush_mm = 1; 1540 } else if (MACHINE_HAS_IDTE) 1541 __pmdp_idte(address, pmdp); 1542 else 1543 __pmdp_csp(pmdp); 1544 atomic_sub(0x10000, &mm->context.attach_count); 1545 } 1546 1547 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1548 1549 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1550 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1551 pgtable_t pgtable); 1552 1553 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1554 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1555 1556 static inline int pmd_trans_splitting(pmd_t pmd) 1557 { 1558 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; 1559 } 1560 1561 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1562 pmd_t *pmdp, pmd_t entry) 1563 { 1564 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INVALID) && MACHINE_HAS_EDAT1) 1565 pmd_val(entry) |= _SEGMENT_ENTRY_CO; 1566 *pmdp = entry; 1567 } 1568 1569 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1570 { 1571 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1572 return pmd; 1573 } 1574 1575 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1576 { 1577 /* Do not clobber PROT_NONE segments! */ 1578 if (!pmd_prot_none(pmd)) 1579 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1580 return pmd; 1581 } 1582 1583 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1584 { 1585 /* No dirty bit in the segment table entry. */ 1586 return pmd; 1587 } 1588 1589 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1590 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1591 unsigned long address, pmd_t *pmdp) 1592 { 1593 pmd_t pmd; 1594 1595 pmd = *pmdp; 1596 pmdp_flush_direct(vma->vm_mm, address, pmdp); 1597 *pmdp = pmd_mkold(pmd); 1598 return pmd_young(pmd); 1599 } 1600 1601 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 1602 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 1603 unsigned long address, pmd_t *pmdp) 1604 { 1605 pmd_t pmd = *pmdp; 1606 1607 pmdp_flush_direct(mm, address, pmdp); 1608 pmd_clear(pmdp); 1609 return pmd; 1610 } 1611 1612 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH 1613 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, 1614 unsigned long address, pmd_t *pmdp) 1615 { 1616 return pmdp_get_and_clear(vma->vm_mm, address, pmdp); 1617 } 1618 1619 #define __HAVE_ARCH_PMDP_INVALIDATE 1620 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1621 unsigned long address, pmd_t *pmdp) 1622 { 1623 pmdp_flush_direct(vma->vm_mm, address, pmdp); 1624 } 1625 1626 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1627 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1628 unsigned long address, pmd_t *pmdp) 1629 { 1630 pmd_t pmd = *pmdp; 1631 1632 if (pmd_write(pmd)) { 1633 pmdp_flush_direct(mm, address, pmdp); 1634 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); 1635 } 1636 } 1637 1638 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1639 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1640 1641 static inline int pmd_trans_huge(pmd_t pmd) 1642 { 1643 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1644 } 1645 1646 static inline int has_transparent_hugepage(void) 1647 { 1648 return MACHINE_HAS_HPAGE ? 1 : 0; 1649 } 1650 1651 static inline unsigned long pmd_pfn(pmd_t pmd) 1652 { 1653 return pmd_val(pmd) >> PAGE_SHIFT; 1654 } 1655 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1656 1657 /* 1658 * 31 bit swap entry format: 1659 * A page-table entry has some bits we have to treat in a special way. 1660 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification 1661 * exception will occur instead of a page translation exception. The 1662 * specifiation exception has the bad habit not to store necessary 1663 * information in the lowcore. 1664 * Bits 21, 22, 30 and 31 are used to indicate the page type. 1665 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402 1666 * This leaves the bits 1-19 and bits 24-29 to store type and offset. 1667 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 1668 * plus 24 for the offset. 1669 * 0| offset |0110|o|type |00| 1670 * 0 0000000001111111111 2222 2 22222 33 1671 * 0 1234567890123456789 0123 4 56789 01 1672 * 1673 * 64 bit swap entry format: 1674 * A page-table entry has some bits we have to treat in a special way. 1675 * Bits 52 and bit 55 have to be zero, otherwise an specification 1676 * exception will occur instead of a page translation exception. The 1677 * specifiation exception has the bad habit not to store necessary 1678 * information in the lowcore. 1679 * Bits 53, 54, 62 and 63 are used to indicate the page type. 1680 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402 1681 * This leaves the bits 0-51 and bits 56-61 to store type and offset. 1682 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 1683 * plus 56 for the offset. 1684 * | offset |0110|o|type |00| 1685 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 1686 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 1687 */ 1688 #ifndef CONFIG_64BIT 1689 #define __SWP_OFFSET_MASK (~0UL >> 12) 1690 #else 1691 #define __SWP_OFFSET_MASK (~0UL >> 11) 1692 #endif 1693 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1694 { 1695 pte_t pte; 1696 offset &= __SWP_OFFSET_MASK; 1697 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) | 1698 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); 1699 return pte; 1700 } 1701 1702 #define __swp_type(entry) (((entry).val >> 2) & 0x1f) 1703 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) 1704 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 1705 1706 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1707 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1708 1709 #ifndef CONFIG_64BIT 1710 # define PTE_FILE_MAX_BITS 26 1711 #else /* CONFIG_64BIT */ 1712 # define PTE_FILE_MAX_BITS 59 1713 #endif /* CONFIG_64BIT */ 1714 1715 #define pte_to_pgoff(__pte) \ 1716 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) 1717 1718 #define pgoff_to_pte(__off) \ 1719 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ 1720 | _PAGE_INVALID | _PAGE_PROTECT }) 1721 1722 #endif /* !__ASSEMBLY__ */ 1723 1724 #define kern_addr_valid(addr) (1) 1725 1726 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1727 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1728 extern int s390_enable_sie(void); 1729 extern void s390_enable_skey(void); 1730 1731 /* 1732 * No page table caches to initialise 1733 */ 1734 static inline void pgtable_cache_init(void) { } 1735 static inline void check_pgt_cache(void) { } 1736 1737 #include <asm-generic/pgtable.h> 1738 1739 #endif /* _S390_PAGE_H */ 1740