1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. 16 * For s390 64 bit we use up to four of the five levels the hardware 17 * provides (region first tables are not used). 18 * 19 * The "pgd_xxx()" functions are trivial for a folded two-level 20 * setup: the pgd is never bad, and a pmd always exists (as it's folded 21 * into the pgd entry) 22 * 23 * This file contains the functions and defines necessary to modify and use 24 * the S390 page table tree. 25 */ 26 #ifndef __ASSEMBLY__ 27 #include <linux/sched.h> 28 #include <linux/mm_types.h> 29 #include <linux/page-flags.h> 30 #include <linux/radix-tree.h> 31 #include <asm/bug.h> 32 #include <asm/page.h> 33 34 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 35 extern void paging_init(void); 36 extern void vmem_map_init(void); 37 38 /* 39 * The S390 doesn't have any external MMU info: the kernel page 40 * tables contain all the necessary information. 41 */ 42 #define update_mmu_cache(vma, address, ptep) do { } while (0) 43 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 44 45 /* 46 * ZERO_PAGE is a global shared page that is always zero; used 47 * for zero-mapped memory areas etc.. 48 */ 49 50 extern unsigned long empty_zero_page; 51 extern unsigned long zero_page_mask; 52 53 #define ZERO_PAGE(vaddr) \ 54 (virt_to_page((void *)(empty_zero_page + \ 55 (((unsigned long)(vaddr)) &zero_page_mask)))) 56 #define __HAVE_COLOR_ZERO_PAGE 57 58 /* TODO: s390 cannot support io_remap_pfn_range... */ 59 #endif /* !__ASSEMBLY__ */ 60 61 /* 62 * PMD_SHIFT determines the size of the area a second-level page 63 * table can map 64 * PGDIR_SHIFT determines what a third-level page table entry can map 65 */ 66 #define PMD_SHIFT 20 67 #define PUD_SHIFT 31 68 #define PGDIR_SHIFT 42 69 70 #define PMD_SIZE (1UL << PMD_SHIFT) 71 #define PMD_MASK (~(PMD_SIZE-1)) 72 #define PUD_SIZE (1UL << PUD_SHIFT) 73 #define PUD_MASK (~(PUD_SIZE-1)) 74 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 75 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 76 77 /* 78 * entries per page directory level: the S390 is two-level, so 79 * we don't really have any PMD directory physically. 80 * for S390 segment-table entries are combined to one PGD 81 * that leads to 1024 pte per pgd 82 */ 83 #define PTRS_PER_PTE 256 84 #define PTRS_PER_PMD 2048 85 #define PTRS_PER_PUD 2048 86 #define PTRS_PER_PGD 2048 87 88 #define FIRST_USER_ADDRESS 0UL 89 90 #define pte_ERROR(e) \ 91 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 92 #define pmd_ERROR(e) \ 93 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 94 #define pud_ERROR(e) \ 95 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 96 #define pgd_ERROR(e) \ 97 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 98 99 #ifndef __ASSEMBLY__ 100 /* 101 * The vmalloc and module area will always be on the topmost area of the 102 * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. 103 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 104 * modules will reside. That makes sure that inter module branches always 105 * happen without trampolines and in addition the placement within a 2GB frame 106 * is branch prediction unit friendly. 107 */ 108 extern unsigned long VMALLOC_START; 109 extern unsigned long VMALLOC_END; 110 extern struct page *vmemmap; 111 112 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 113 114 extern unsigned long MODULES_VADDR; 115 extern unsigned long MODULES_END; 116 #define MODULES_VADDR MODULES_VADDR 117 #define MODULES_END MODULES_END 118 #define MODULES_LEN (1UL << 31) 119 120 static inline int is_module_addr(void *addr) 121 { 122 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 123 if (addr < (void *)MODULES_VADDR) 124 return 0; 125 if (addr > (void *)MODULES_END) 126 return 0; 127 return 1; 128 } 129 130 /* 131 * A 64 bit pagetable entry of S390 has following format: 132 * | PFRA |0IPC| OS | 133 * 0000000000111111111122222222223333333333444444444455555555556666 134 * 0123456789012345678901234567890123456789012345678901234567890123 135 * 136 * I Page-Invalid Bit: Page is not available for address-translation 137 * P Page-Protection Bit: Store access not possible for page 138 * C Change-bit override: HW is not required to set change bit 139 * 140 * A 64 bit segmenttable entry of S390 has following format: 141 * | P-table origin | TT 142 * 0000000000111111111122222222223333333333444444444455555555556666 143 * 0123456789012345678901234567890123456789012345678901234567890123 144 * 145 * I Segment-Invalid Bit: Segment is not available for address-translation 146 * C Common-Segment Bit: Segment is not private (PoP 3-30) 147 * P Page-Protection Bit: Store access not possible for page 148 * TT Type 00 149 * 150 * A 64 bit region table entry of S390 has following format: 151 * | S-table origin | TF TTTL 152 * 0000000000111111111122222222223333333333444444444455555555556666 153 * 0123456789012345678901234567890123456789012345678901234567890123 154 * 155 * I Segment-Invalid Bit: Segment is not available for address-translation 156 * TT Type 01 157 * TF 158 * TL Table length 159 * 160 * The 64 bit regiontable origin of S390 has following format: 161 * | region table origon | DTTL 162 * 0000000000111111111122222222223333333333444444444455555555556666 163 * 0123456789012345678901234567890123456789012345678901234567890123 164 * 165 * X Space-Switch event: 166 * G Segment-Invalid Bit: 167 * P Private-Space Bit: 168 * S Storage-Alteration: 169 * R Real space 170 * TL Table-Length: 171 * 172 * A storage key has the following format: 173 * | ACC |F|R|C|0| 174 * 0 3 4 5 6 7 175 * ACC: access key 176 * F : fetch protection bit 177 * R : referenced bit 178 * C : changed bit 179 */ 180 181 /* Hardware bits in the page table entry */ 182 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 183 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 184 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 185 186 /* Software bits in the page table entry */ 187 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 188 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 189 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 190 #define _PAGE_READ 0x010 /* SW pte read bit */ 191 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 192 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 193 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 194 #define __HAVE_ARCH_PTE_SPECIAL 195 196 /* Set of bits not changed in pte_modify */ 197 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 198 _PAGE_YOUNG) 199 200 /* 201 * handle_pte_fault uses pte_present and pte_none to find out the pte type 202 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 203 * distinguish present from not-present ptes. It is changed only with the page 204 * table lock held. 205 * 206 * The following table gives the different possible bit combinations for 207 * the pte hardware and software bits in the last 12 bits of a pte 208 * (. unassigned bit, x don't care, t swap type): 209 * 210 * 842100000000 211 * 000084210000 212 * 000000008421 213 * .IR.uswrdy.p 214 * empty .10.00000000 215 * swap .11..ttttt.0 216 * prot-none, clean, old .11.xx0000.1 217 * prot-none, clean, young .11.xx0001.1 218 * prot-none, dirty, old .10.xx0010.1 219 * prot-none, dirty, young .10.xx0011.1 220 * read-only, clean, old .11.xx0100.1 221 * read-only, clean, young .01.xx0101.1 222 * read-only, dirty, old .11.xx0110.1 223 * read-only, dirty, young .01.xx0111.1 224 * read-write, clean, old .11.xx1100.1 225 * read-write, clean, young .01.xx1101.1 226 * read-write, dirty, old .10.xx1110.1 227 * read-write, dirty, young .00.xx1111.1 228 * HW-bits: R read-only, I invalid 229 * SW-bits: p present, y young, d dirty, r read, w write, s special, 230 * u unused, l large 231 * 232 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 233 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 234 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 235 */ 236 237 /* Bits in the segment/region table address-space-control-element */ 238 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 239 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 240 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 241 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 242 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 243 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 244 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 245 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 246 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 247 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 248 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 249 250 /* Bits in the region table entry */ 251 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 252 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 253 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 254 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 255 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 256 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 257 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 258 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 259 260 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 261 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 262 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 263 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 264 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 265 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 266 267 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ 268 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ 269 270 /* Bits in the segment table entry */ 271 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 272 #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL 273 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 274 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 275 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ 276 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 277 278 #define _SEGMENT_ENTRY (0) 279 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 280 281 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 282 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 283 #define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */ 284 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 285 #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */ 286 #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */ 287 288 /* 289 * Segment table entry encoding (R = read-only, I = invalid, y = young bit): 290 * dy..R...I...wr 291 * prot-none, clean, old 00..1...1...00 292 * prot-none, clean, young 01..1...1...00 293 * prot-none, dirty, old 10..1...1...00 294 * prot-none, dirty, young 11..1...1...00 295 * read-only, clean, old 00..1...1...01 296 * read-only, clean, young 01..1...0...01 297 * read-only, dirty, old 10..1...1...01 298 * read-only, dirty, young 11..1...0...01 299 * read-write, clean, old 00..1...1...11 300 * read-write, clean, young 01..1...0...11 301 * read-write, dirty, old 10..0...1...11 302 * read-write, dirty, young 11..0...0...11 303 * The segment table origin is used to distinguish empty (origin==0) from 304 * read-write, old segment table entries (origin!=0) 305 * HW-bits: R read-only, I invalid 306 * SW-bits: y young, d dirty, r read, w write 307 */ 308 309 #define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */ 310 311 /* Page status table bits for virtualization */ 312 #define PGSTE_ACC_BITS 0xf000000000000000UL 313 #define PGSTE_FP_BIT 0x0800000000000000UL 314 #define PGSTE_PCL_BIT 0x0080000000000000UL 315 #define PGSTE_HR_BIT 0x0040000000000000UL 316 #define PGSTE_HC_BIT 0x0020000000000000UL 317 #define PGSTE_GR_BIT 0x0004000000000000UL 318 #define PGSTE_GC_BIT 0x0002000000000000UL 319 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 320 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 321 322 /* Guest Page State used for virtualization */ 323 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 324 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 325 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 326 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 327 328 /* 329 * A user page table pointer has the space-switch-event bit, the 330 * private-space-control bit and the storage-alteration-event-control 331 * bit set. A kernel page table pointer doesn't need them. 332 */ 333 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 334 _ASCE_ALT_EVENT) 335 336 /* 337 * Page protection definitions. 338 */ 339 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) 340 #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 341 _PAGE_INVALID | _PAGE_PROTECT) 342 #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 343 _PAGE_INVALID | _PAGE_PROTECT) 344 345 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 346 _PAGE_YOUNG | _PAGE_DIRTY) 347 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 348 _PAGE_YOUNG | _PAGE_DIRTY) 349 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 350 _PAGE_PROTECT) 351 352 /* 353 * On s390 the page table entry has an invalid bit and a read-only bit. 354 * Read permission implies execute permission and write permission 355 * implies read permission. 356 */ 357 /*xwr*/ 358 #define __P000 PAGE_NONE 359 #define __P001 PAGE_READ 360 #define __P010 PAGE_READ 361 #define __P011 PAGE_READ 362 #define __P100 PAGE_READ 363 #define __P101 PAGE_READ 364 #define __P110 PAGE_READ 365 #define __P111 PAGE_READ 366 367 #define __S000 PAGE_NONE 368 #define __S001 PAGE_READ 369 #define __S010 PAGE_WRITE 370 #define __S011 PAGE_WRITE 371 #define __S100 PAGE_READ 372 #define __S101 PAGE_READ 373 #define __S110 PAGE_WRITE 374 #define __S111 PAGE_WRITE 375 376 /* 377 * Segment entry (large page) protection definitions. 378 */ 379 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 380 _SEGMENT_ENTRY_PROTECT) 381 #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \ 382 _SEGMENT_ENTRY_READ) 383 #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \ 384 _SEGMENT_ENTRY_WRITE) 385 386 static inline int mm_has_pgste(struct mm_struct *mm) 387 { 388 #ifdef CONFIG_PGSTE 389 if (unlikely(mm->context.has_pgste)) 390 return 1; 391 #endif 392 return 0; 393 } 394 395 static inline int mm_alloc_pgste(struct mm_struct *mm) 396 { 397 #ifdef CONFIG_PGSTE 398 if (unlikely(mm->context.alloc_pgste)) 399 return 1; 400 #endif 401 return 0; 402 } 403 404 /* 405 * In the case that a guest uses storage keys 406 * faults should no longer be backed by zero pages 407 */ 408 #define mm_forbids_zeropage mm_use_skey 409 static inline int mm_use_skey(struct mm_struct *mm) 410 { 411 #ifdef CONFIG_PGSTE 412 if (mm->context.use_skey) 413 return 1; 414 #endif 415 return 0; 416 } 417 418 /* 419 * pgd/pmd/pte query functions 420 */ 421 static inline int pgd_present(pgd_t pgd) 422 { 423 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 424 return 1; 425 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 426 } 427 428 static inline int pgd_none(pgd_t pgd) 429 { 430 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 431 return 0; 432 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 433 } 434 435 static inline int pgd_bad(pgd_t pgd) 436 { 437 /* 438 * With dynamic page table levels the pgd can be a region table 439 * entry or a segment table entry. Check for the bit that are 440 * invalid for either table entry. 441 */ 442 unsigned long mask = 443 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & 444 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 445 return (pgd_val(pgd) & mask) != 0; 446 } 447 448 static inline int pud_present(pud_t pud) 449 { 450 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 451 return 1; 452 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 453 } 454 455 static inline int pud_none(pud_t pud) 456 { 457 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 458 return 0; 459 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; 460 } 461 462 static inline int pud_large(pud_t pud) 463 { 464 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 465 return 0; 466 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 467 } 468 469 static inline int pud_bad(pud_t pud) 470 { 471 /* 472 * With dynamic page table levels the pud can be a region table 473 * entry or a segment table entry. Check for the bit that are 474 * invalid for either table entry. 475 */ 476 unsigned long mask = 477 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & 478 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 479 return (pud_val(pud) & mask) != 0; 480 } 481 482 static inline int pmd_present(pmd_t pmd) 483 { 484 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; 485 } 486 487 static inline int pmd_none(pmd_t pmd) 488 { 489 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; 490 } 491 492 static inline int pmd_large(pmd_t pmd) 493 { 494 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 495 } 496 497 static inline unsigned long pmd_pfn(pmd_t pmd) 498 { 499 unsigned long origin_mask; 500 501 origin_mask = _SEGMENT_ENTRY_ORIGIN; 502 if (pmd_large(pmd)) 503 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 504 return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; 505 } 506 507 static inline int pmd_bad(pmd_t pmd) 508 { 509 if (pmd_large(pmd)) 510 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; 511 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 512 } 513 514 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 515 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 516 unsigned long addr, pmd_t *pmdp); 517 518 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 519 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 520 unsigned long address, pmd_t *pmdp, 521 pmd_t entry, int dirty); 522 523 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 524 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 525 unsigned long address, pmd_t *pmdp); 526 527 #define __HAVE_ARCH_PMD_WRITE 528 static inline int pmd_write(pmd_t pmd) 529 { 530 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 531 } 532 533 static inline int pmd_dirty(pmd_t pmd) 534 { 535 int dirty = 1; 536 if (pmd_large(pmd)) 537 dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 538 return dirty; 539 } 540 541 static inline int pmd_young(pmd_t pmd) 542 { 543 int young = 1; 544 if (pmd_large(pmd)) 545 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 546 return young; 547 } 548 549 static inline int pte_present(pte_t pte) 550 { 551 /* Bit pattern: (pte & 0x001) == 0x001 */ 552 return (pte_val(pte) & _PAGE_PRESENT) != 0; 553 } 554 555 static inline int pte_none(pte_t pte) 556 { 557 /* Bit pattern: pte == 0x400 */ 558 return pte_val(pte) == _PAGE_INVALID; 559 } 560 561 static inline int pte_swap(pte_t pte) 562 { 563 /* Bit pattern: (pte & 0x201) == 0x200 */ 564 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 565 == _PAGE_PROTECT; 566 } 567 568 static inline int pte_special(pte_t pte) 569 { 570 return (pte_val(pte) & _PAGE_SPECIAL); 571 } 572 573 #define __HAVE_ARCH_PTE_SAME 574 static inline int pte_same(pte_t a, pte_t b) 575 { 576 return pte_val(a) == pte_val(b); 577 } 578 579 #ifdef CONFIG_NUMA_BALANCING 580 static inline int pte_protnone(pte_t pte) 581 { 582 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 583 } 584 585 static inline int pmd_protnone(pmd_t pmd) 586 { 587 /* pmd_large(pmd) implies pmd_present(pmd) */ 588 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 589 } 590 #endif 591 592 static inline pgste_t pgste_get_lock(pte_t *ptep) 593 { 594 unsigned long new = 0; 595 #ifdef CONFIG_PGSTE 596 unsigned long old; 597 598 preempt_disable(); 599 asm( 600 " lg %0,%2\n" 601 "0: lgr %1,%0\n" 602 " nihh %0,0xff7f\n" /* clear PCL bit in old */ 603 " oihh %1,0x0080\n" /* set PCL bit in new */ 604 " csg %0,%1,%2\n" 605 " jl 0b\n" 606 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 607 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); 608 #endif 609 return __pgste(new); 610 } 611 612 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 613 { 614 #ifdef CONFIG_PGSTE 615 asm( 616 " nihh %1,0xff7f\n" /* clear PCL bit */ 617 " stg %1,%0\n" 618 : "=Q" (ptep[PTRS_PER_PTE]) 619 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) 620 : "cc", "memory"); 621 preempt_enable(); 622 #endif 623 } 624 625 static inline pgste_t pgste_get(pte_t *ptep) 626 { 627 unsigned long pgste = 0; 628 #ifdef CONFIG_PGSTE 629 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); 630 #endif 631 return __pgste(pgste); 632 } 633 634 static inline void pgste_set(pte_t *ptep, pgste_t pgste) 635 { 636 #ifdef CONFIG_PGSTE 637 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; 638 #endif 639 } 640 641 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, 642 struct mm_struct *mm) 643 { 644 #ifdef CONFIG_PGSTE 645 unsigned long address, bits, skey; 646 647 if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) 648 return pgste; 649 address = pte_val(*ptep) & PAGE_MASK; 650 skey = (unsigned long) page_get_storage_key(address); 651 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 652 /* Transfer page changed & referenced bit to guest bits in pgste */ 653 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ 654 /* Copy page access key and fetch protection bit to pgste */ 655 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); 656 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 657 #endif 658 return pgste; 659 660 } 661 662 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, 663 struct mm_struct *mm) 664 { 665 #ifdef CONFIG_PGSTE 666 unsigned long address; 667 unsigned long nkey; 668 669 if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) 670 return; 671 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); 672 address = pte_val(entry) & PAGE_MASK; 673 /* 674 * Set page access key and fetch protection bit from pgste. 675 * The guest C/R information is still in the PGSTE, set real 676 * key C/R to 0. 677 */ 678 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; 679 nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; 680 page_set_storage_key(address, nkey, 0); 681 #endif 682 } 683 684 static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) 685 { 686 if ((pte_val(entry) & _PAGE_PRESENT) && 687 (pte_val(entry) & _PAGE_WRITE) && 688 !(pte_val(entry) & _PAGE_INVALID)) { 689 if (!MACHINE_HAS_ESOP) { 690 /* 691 * Without enhanced suppression-on-protection force 692 * the dirty bit on for all writable ptes. 693 */ 694 pte_val(entry) |= _PAGE_DIRTY; 695 pte_val(entry) &= ~_PAGE_PROTECT; 696 } 697 if (!(pte_val(entry) & _PAGE_PROTECT)) 698 /* This pte allows write access, set user-dirty */ 699 pgste_val(pgste) |= PGSTE_UC_BIT; 700 } 701 *ptep = entry; 702 return pgste; 703 } 704 705 /** 706 * struct gmap_struct - guest address space 707 * @crst_list: list of all crst tables used in the guest address space 708 * @mm: pointer to the parent mm_struct 709 * @guest_to_host: radix tree with guest to host address translation 710 * @host_to_guest: radix tree with pointer to segment table entries 711 * @guest_table_lock: spinlock to protect all entries in the guest page table 712 * @table: pointer to the page directory 713 * @asce: address space control element for gmap page table 714 * @pfault_enabled: defines if pfaults are applicable for the guest 715 */ 716 struct gmap { 717 struct list_head list; 718 struct list_head crst_list; 719 struct mm_struct *mm; 720 struct radix_tree_root guest_to_host; 721 struct radix_tree_root host_to_guest; 722 spinlock_t guest_table_lock; 723 unsigned long *table; 724 unsigned long asce; 725 unsigned long asce_end; 726 void *private; 727 bool pfault_enabled; 728 }; 729 730 /** 731 * struct gmap_notifier - notify function block for page invalidation 732 * @notifier_call: address of callback function 733 */ 734 struct gmap_notifier { 735 struct list_head list; 736 void (*notifier_call)(struct gmap *gmap, unsigned long gaddr); 737 }; 738 739 struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit); 740 void gmap_free(struct gmap *gmap); 741 void gmap_enable(struct gmap *gmap); 742 void gmap_disable(struct gmap *gmap); 743 int gmap_map_segment(struct gmap *gmap, unsigned long from, 744 unsigned long to, unsigned long len); 745 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 746 unsigned long __gmap_translate(struct gmap *, unsigned long gaddr); 747 unsigned long gmap_translate(struct gmap *, unsigned long gaddr); 748 int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr); 749 int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags); 750 void gmap_discard(struct gmap *, unsigned long from, unsigned long to); 751 void __gmap_zap(struct gmap *, unsigned long gaddr); 752 bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); 753 754 755 void gmap_register_ipte_notifier(struct gmap_notifier *); 756 void gmap_unregister_ipte_notifier(struct gmap_notifier *); 757 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); 758 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); 759 760 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, 761 unsigned long addr, 762 pte_t *ptep, pgste_t pgste) 763 { 764 #ifdef CONFIG_PGSTE 765 if (pgste_val(pgste) & PGSTE_IN_BIT) { 766 pgste_val(pgste) &= ~PGSTE_IN_BIT; 767 gmap_do_ipte_notify(mm, addr, ptep); 768 } 769 #endif 770 return pgste; 771 } 772 773 /* 774 * Certain architectures need to do special things when PTEs 775 * within a page table are directly modified. Thus, the following 776 * hook is made available. 777 */ 778 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 779 pte_t *ptep, pte_t entry) 780 { 781 pgste_t pgste; 782 783 if (mm_has_pgste(mm)) { 784 pgste = pgste_get_lock(ptep); 785 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; 786 pgste_set_key(ptep, pgste, entry, mm); 787 pgste = pgste_set_pte(ptep, pgste, entry); 788 pgste_set_unlock(ptep, pgste); 789 } else { 790 *ptep = entry; 791 } 792 } 793 794 /* 795 * query functions pte_write/pte_dirty/pte_young only work if 796 * pte_present() is true. Undefined behaviour if not.. 797 */ 798 static inline int pte_write(pte_t pte) 799 { 800 return (pte_val(pte) & _PAGE_WRITE) != 0; 801 } 802 803 static inline int pte_dirty(pte_t pte) 804 { 805 return (pte_val(pte) & _PAGE_DIRTY) != 0; 806 } 807 808 static inline int pte_young(pte_t pte) 809 { 810 return (pte_val(pte) & _PAGE_YOUNG) != 0; 811 } 812 813 #define __HAVE_ARCH_PTE_UNUSED 814 static inline int pte_unused(pte_t pte) 815 { 816 return pte_val(pte) & _PAGE_UNUSED; 817 } 818 819 /* 820 * pgd/pmd/pte modification functions 821 */ 822 823 static inline void pgd_clear(pgd_t *pgd) 824 { 825 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 826 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 827 } 828 829 static inline void pud_clear(pud_t *pud) 830 { 831 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 832 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 833 } 834 835 static inline void pmd_clear(pmd_t *pmdp) 836 { 837 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; 838 } 839 840 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 841 { 842 pte_val(*ptep) = _PAGE_INVALID; 843 } 844 845 /* 846 * The following pte modification functions only work if 847 * pte_present() is true. Undefined behaviour if not.. 848 */ 849 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 850 { 851 pte_val(pte) &= _PAGE_CHG_MASK; 852 pte_val(pte) |= pgprot_val(newprot); 853 /* 854 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the 855 * invalid bit set, clear it again for readable, young pages 856 */ 857 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 858 pte_val(pte) &= ~_PAGE_INVALID; 859 /* 860 * newprot for PAGE_READ and PAGE_WRITE has the page protection 861 * bit set, clear it again for writable, dirty pages 862 */ 863 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 864 pte_val(pte) &= ~_PAGE_PROTECT; 865 return pte; 866 } 867 868 static inline pte_t pte_wrprotect(pte_t pte) 869 { 870 pte_val(pte) &= ~_PAGE_WRITE; 871 pte_val(pte) |= _PAGE_PROTECT; 872 return pte; 873 } 874 875 static inline pte_t pte_mkwrite(pte_t pte) 876 { 877 pte_val(pte) |= _PAGE_WRITE; 878 if (pte_val(pte) & _PAGE_DIRTY) 879 pte_val(pte) &= ~_PAGE_PROTECT; 880 return pte; 881 } 882 883 static inline pte_t pte_mkclean(pte_t pte) 884 { 885 pte_val(pte) &= ~_PAGE_DIRTY; 886 pte_val(pte) |= _PAGE_PROTECT; 887 return pte; 888 } 889 890 static inline pte_t pte_mkdirty(pte_t pte) 891 { 892 pte_val(pte) |= _PAGE_DIRTY; 893 if (pte_val(pte) & _PAGE_WRITE) 894 pte_val(pte) &= ~_PAGE_PROTECT; 895 return pte; 896 } 897 898 static inline pte_t pte_mkold(pte_t pte) 899 { 900 pte_val(pte) &= ~_PAGE_YOUNG; 901 pte_val(pte) |= _PAGE_INVALID; 902 return pte; 903 } 904 905 static inline pte_t pte_mkyoung(pte_t pte) 906 { 907 pte_val(pte) |= _PAGE_YOUNG; 908 if (pte_val(pte) & _PAGE_READ) 909 pte_val(pte) &= ~_PAGE_INVALID; 910 return pte; 911 } 912 913 static inline pte_t pte_mkspecial(pte_t pte) 914 { 915 pte_val(pte) |= _PAGE_SPECIAL; 916 return pte; 917 } 918 919 #ifdef CONFIG_HUGETLB_PAGE 920 static inline pte_t pte_mkhuge(pte_t pte) 921 { 922 pte_val(pte) |= _PAGE_LARGE; 923 return pte; 924 } 925 #endif 926 927 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 928 { 929 unsigned long pto = (unsigned long) ptep; 930 931 /* Invalidation + global TLB flush for the pte */ 932 asm volatile( 933 " ipte %2,%3" 934 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); 935 } 936 937 static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) 938 { 939 unsigned long pto = (unsigned long) ptep; 940 941 /* Invalidation + local TLB flush for the pte */ 942 asm volatile( 943 " .insn rrf,0xb2210000,%2,%3,0,1" 944 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); 945 } 946 947 static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep) 948 { 949 unsigned long pto = (unsigned long) ptep; 950 951 /* Invalidate a range of ptes + global TLB flush of the ptes */ 952 do { 953 asm volatile( 954 " .insn rrf,0xb2210000,%2,%0,%1,0" 955 : "+a" (address), "+a" (nr) : "a" (pto) : "memory"); 956 } while (nr != 255); 957 } 958 959 static inline void ptep_flush_direct(struct mm_struct *mm, 960 unsigned long address, pte_t *ptep) 961 { 962 int active, count; 963 964 if (pte_val(*ptep) & _PAGE_INVALID) 965 return; 966 active = (mm == current->active_mm) ? 1 : 0; 967 count = atomic_add_return(0x10000, &mm->context.attach_count); 968 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && 969 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) 970 __ptep_ipte_local(address, ptep); 971 else 972 __ptep_ipte(address, ptep); 973 atomic_sub(0x10000, &mm->context.attach_count); 974 } 975 976 static inline void ptep_flush_lazy(struct mm_struct *mm, 977 unsigned long address, pte_t *ptep) 978 { 979 int active, count; 980 981 if (pte_val(*ptep) & _PAGE_INVALID) 982 return; 983 active = (mm == current->active_mm) ? 1 : 0; 984 count = atomic_add_return(0x10000, &mm->context.attach_count); 985 if ((count & 0xffff) <= active) { 986 pte_val(*ptep) |= _PAGE_INVALID; 987 mm->context.flush_mm = 1; 988 } else 989 __ptep_ipte(address, ptep); 990 atomic_sub(0x10000, &mm->context.attach_count); 991 } 992 993 /* 994 * Get (and clear) the user dirty bit for a pte. 995 */ 996 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 997 unsigned long addr, 998 pte_t *ptep) 999 { 1000 pgste_t pgste; 1001 pte_t pte; 1002 int dirty; 1003 1004 if (!mm_has_pgste(mm)) 1005 return 0; 1006 pgste = pgste_get_lock(ptep); 1007 dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); 1008 pgste_val(pgste) &= ~PGSTE_UC_BIT; 1009 pte = *ptep; 1010 if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { 1011 pgste = pgste_ipte_notify(mm, addr, ptep, pgste); 1012 __ptep_ipte(addr, ptep); 1013 if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) 1014 pte_val(pte) |= _PAGE_PROTECT; 1015 else 1016 pte_val(pte) |= _PAGE_INVALID; 1017 *ptep = pte; 1018 } 1019 pgste_set_unlock(ptep, pgste); 1020 return dirty; 1021 } 1022 1023 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1024 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1025 unsigned long addr, pte_t *ptep) 1026 { 1027 pgste_t pgste; 1028 pte_t pte, oldpte; 1029 int young; 1030 1031 if (mm_has_pgste(vma->vm_mm)) { 1032 pgste = pgste_get_lock(ptep); 1033 pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste); 1034 } 1035 1036 oldpte = pte = *ptep; 1037 ptep_flush_direct(vma->vm_mm, addr, ptep); 1038 young = pte_young(pte); 1039 pte = pte_mkold(pte); 1040 1041 if (mm_has_pgste(vma->vm_mm)) { 1042 pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm); 1043 pgste = pgste_set_pte(ptep, pgste, pte); 1044 pgste_set_unlock(ptep, pgste); 1045 } else 1046 *ptep = pte; 1047 1048 return young; 1049 } 1050 1051 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1052 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1053 unsigned long address, pte_t *ptep) 1054 { 1055 return ptep_test_and_clear_young(vma, address, ptep); 1056 } 1057 1058 /* 1059 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1060 * both clear the TLB for the unmapped pte. The reason is that 1061 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1062 * to modify an active pte. The sequence is 1063 * 1) ptep_get_and_clear 1064 * 2) set_pte_at 1065 * 3) flush_tlb_range 1066 * On s390 the tlb needs to get flushed with the modification of the pte 1067 * if the pte is active. The only way how this can be implemented is to 1068 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1069 * is a nop. 1070 */ 1071 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1072 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1073 unsigned long address, pte_t *ptep) 1074 { 1075 pgste_t pgste; 1076 pte_t pte; 1077 1078 if (mm_has_pgste(mm)) { 1079 pgste = pgste_get_lock(ptep); 1080 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1081 } 1082 1083 pte = *ptep; 1084 ptep_flush_lazy(mm, address, ptep); 1085 pte_val(*ptep) = _PAGE_INVALID; 1086 1087 if (mm_has_pgste(mm)) { 1088 pgste = pgste_update_all(&pte, pgste, mm); 1089 pgste_set_unlock(ptep, pgste); 1090 } 1091 return pte; 1092 } 1093 1094 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1095 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1096 unsigned long address, 1097 pte_t *ptep) 1098 { 1099 pgste_t pgste; 1100 pte_t pte; 1101 1102 if (mm_has_pgste(mm)) { 1103 pgste = pgste_get_lock(ptep); 1104 pgste_ipte_notify(mm, address, ptep, pgste); 1105 } 1106 1107 pte = *ptep; 1108 ptep_flush_lazy(mm, address, ptep); 1109 1110 if (mm_has_pgste(mm)) { 1111 pgste = pgste_update_all(&pte, pgste, mm); 1112 pgste_set(ptep, pgste); 1113 } 1114 return pte; 1115 } 1116 1117 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1118 unsigned long address, 1119 pte_t *ptep, pte_t pte) 1120 { 1121 pgste_t pgste; 1122 1123 if (mm_has_pgste(mm)) { 1124 pgste = pgste_get(ptep); 1125 pgste_set_key(ptep, pgste, pte, mm); 1126 pgste = pgste_set_pte(ptep, pgste, pte); 1127 pgste_set_unlock(ptep, pgste); 1128 } else 1129 *ptep = pte; 1130 } 1131 1132 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1133 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1134 unsigned long address, pte_t *ptep) 1135 { 1136 pgste_t pgste; 1137 pte_t pte; 1138 1139 if (mm_has_pgste(vma->vm_mm)) { 1140 pgste = pgste_get_lock(ptep); 1141 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); 1142 } 1143 1144 pte = *ptep; 1145 ptep_flush_direct(vma->vm_mm, address, ptep); 1146 pte_val(*ptep) = _PAGE_INVALID; 1147 1148 if (mm_has_pgste(vma->vm_mm)) { 1149 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == 1150 _PGSTE_GPS_USAGE_UNUSED) 1151 pte_val(pte) |= _PAGE_UNUSED; 1152 pgste = pgste_update_all(&pte, pgste, vma->vm_mm); 1153 pgste_set_unlock(ptep, pgste); 1154 } 1155 return pte; 1156 } 1157 1158 /* 1159 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1160 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1161 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1162 * cannot be accessed while the batched unmap is running. In this case 1163 * full==1 and a simple pte_clear is enough. See tlb.h. 1164 */ 1165 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1166 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1167 unsigned long address, 1168 pte_t *ptep, int full) 1169 { 1170 pgste_t pgste; 1171 pte_t pte; 1172 1173 if (!full && mm_has_pgste(mm)) { 1174 pgste = pgste_get_lock(ptep); 1175 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1176 } 1177 1178 pte = *ptep; 1179 if (!full) 1180 ptep_flush_lazy(mm, address, ptep); 1181 pte_val(*ptep) = _PAGE_INVALID; 1182 1183 if (!full && mm_has_pgste(mm)) { 1184 pgste = pgste_update_all(&pte, pgste, mm); 1185 pgste_set_unlock(ptep, pgste); 1186 } 1187 return pte; 1188 } 1189 1190 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1191 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1192 unsigned long address, pte_t *ptep) 1193 { 1194 pgste_t pgste; 1195 pte_t pte = *ptep; 1196 1197 if (pte_write(pte)) { 1198 if (mm_has_pgste(mm)) { 1199 pgste = pgste_get_lock(ptep); 1200 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1201 } 1202 1203 ptep_flush_lazy(mm, address, ptep); 1204 pte = pte_wrprotect(pte); 1205 1206 if (mm_has_pgste(mm)) { 1207 pgste = pgste_set_pte(ptep, pgste, pte); 1208 pgste_set_unlock(ptep, pgste); 1209 } else 1210 *ptep = pte; 1211 } 1212 return pte; 1213 } 1214 1215 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1216 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1217 unsigned long address, pte_t *ptep, 1218 pte_t entry, int dirty) 1219 { 1220 pgste_t pgste; 1221 1222 if (pte_same(*ptep, entry)) 1223 return 0; 1224 if (mm_has_pgste(vma->vm_mm)) { 1225 pgste = pgste_get_lock(ptep); 1226 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); 1227 } 1228 1229 ptep_flush_direct(vma->vm_mm, address, ptep); 1230 1231 if (mm_has_pgste(vma->vm_mm)) { 1232 pgste_set_key(ptep, pgste, entry, vma->vm_mm); 1233 pgste = pgste_set_pte(ptep, pgste, entry); 1234 pgste_set_unlock(ptep, pgste); 1235 } else 1236 *ptep = entry; 1237 return 1; 1238 } 1239 1240 /* 1241 * Conversion functions: convert a page and protection to a page entry, 1242 * and a page entry and page directory to the page they refer to. 1243 */ 1244 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1245 { 1246 pte_t __pte; 1247 pte_val(__pte) = physpage + pgprot_val(pgprot); 1248 return pte_mkyoung(__pte); 1249 } 1250 1251 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1252 { 1253 unsigned long physpage = page_to_phys(page); 1254 pte_t __pte = mk_pte_phys(physpage, pgprot); 1255 1256 if (pte_write(__pte) && PageDirty(page)) 1257 __pte = pte_mkdirty(__pte); 1258 return __pte; 1259 } 1260 1261 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1262 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1263 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1264 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1265 1266 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1267 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1268 1269 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1270 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1271 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1272 1273 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1274 { 1275 pud_t *pud = (pud_t *) pgd; 1276 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1277 pud = (pud_t *) pgd_deref(*pgd); 1278 return pud + pud_index(address); 1279 } 1280 1281 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1282 { 1283 pmd_t *pmd = (pmd_t *) pud; 1284 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1285 pmd = (pmd_t *) pud_deref(*pud); 1286 return pmd + pmd_index(address); 1287 } 1288 1289 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1290 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1291 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1292 1293 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1294 1295 /* Find an entry in the lowest level page table.. */ 1296 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1297 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1298 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1299 #define pte_unmap(pte) do { } while (0) 1300 1301 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1302 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1303 { 1304 /* 1305 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) 1306 * Convert to segment table entry format. 1307 */ 1308 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1309 return pgprot_val(SEGMENT_NONE); 1310 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) 1311 return pgprot_val(SEGMENT_READ); 1312 return pgprot_val(SEGMENT_WRITE); 1313 } 1314 1315 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1316 { 1317 pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; 1318 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1319 return pmd; 1320 } 1321 1322 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1323 { 1324 pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; 1325 if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1326 return pmd; 1327 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1328 return pmd; 1329 } 1330 1331 static inline pmd_t pmd_mkclean(pmd_t pmd) 1332 { 1333 if (pmd_large(pmd)) { 1334 pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; 1335 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1336 } 1337 return pmd; 1338 } 1339 1340 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1341 { 1342 if (pmd_large(pmd)) { 1343 pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY; 1344 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1345 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1346 } 1347 return pmd; 1348 } 1349 1350 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1351 { 1352 if (pmd_large(pmd)) { 1353 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1354 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1355 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; 1356 } 1357 return pmd; 1358 } 1359 1360 static inline pmd_t pmd_mkold(pmd_t pmd) 1361 { 1362 if (pmd_large(pmd)) { 1363 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; 1364 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1365 } 1366 return pmd; 1367 } 1368 1369 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1370 { 1371 if (pmd_large(pmd)) { 1372 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | 1373 _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | 1374 _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT; 1375 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1376 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1377 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1378 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1379 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1380 return pmd; 1381 } 1382 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; 1383 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1384 return pmd; 1385 } 1386 1387 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1388 { 1389 pmd_t __pmd; 1390 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1391 return __pmd; 1392 } 1393 1394 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1395 1396 static inline void __pmdp_csp(pmd_t *pmdp) 1397 { 1398 register unsigned long reg2 asm("2") = pmd_val(*pmdp); 1399 register unsigned long reg3 asm("3") = pmd_val(*pmdp) | 1400 _SEGMENT_ENTRY_INVALID; 1401 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; 1402 1403 asm volatile( 1404 " csp %1,%3" 1405 : "=m" (*pmdp) 1406 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); 1407 } 1408 1409 static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) 1410 { 1411 unsigned long sto; 1412 1413 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); 1414 asm volatile( 1415 " .insn rrf,0xb98e0000,%2,%3,0,0" 1416 : "=m" (*pmdp) 1417 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) 1418 : "cc" ); 1419 } 1420 1421 static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) 1422 { 1423 unsigned long sto; 1424 1425 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); 1426 asm volatile( 1427 " .insn rrf,0xb98e0000,%2,%3,0,1" 1428 : "=m" (*pmdp) 1429 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) 1430 : "cc" ); 1431 } 1432 1433 static inline void pmdp_flush_direct(struct mm_struct *mm, 1434 unsigned long address, pmd_t *pmdp) 1435 { 1436 int active, count; 1437 1438 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) 1439 return; 1440 if (!MACHINE_HAS_IDTE) { 1441 __pmdp_csp(pmdp); 1442 return; 1443 } 1444 active = (mm == current->active_mm) ? 1 : 0; 1445 count = atomic_add_return(0x10000, &mm->context.attach_count); 1446 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && 1447 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) 1448 __pmdp_idte_local(address, pmdp); 1449 else 1450 __pmdp_idte(address, pmdp); 1451 atomic_sub(0x10000, &mm->context.attach_count); 1452 } 1453 1454 static inline void pmdp_flush_lazy(struct mm_struct *mm, 1455 unsigned long address, pmd_t *pmdp) 1456 { 1457 int active, count; 1458 1459 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) 1460 return; 1461 active = (mm == current->active_mm) ? 1 : 0; 1462 count = atomic_add_return(0x10000, &mm->context.attach_count); 1463 if ((count & 0xffff) <= active) { 1464 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID; 1465 mm->context.flush_mm = 1; 1466 } else if (MACHINE_HAS_IDTE) 1467 __pmdp_idte(address, pmdp); 1468 else 1469 __pmdp_csp(pmdp); 1470 atomic_sub(0x10000, &mm->context.attach_count); 1471 } 1472 1473 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1474 1475 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1476 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1477 pgtable_t pgtable); 1478 1479 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1480 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1481 1482 static inline int pmd_trans_splitting(pmd_t pmd) 1483 { 1484 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) && 1485 (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT); 1486 } 1487 1488 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1489 pmd_t *pmdp, pmd_t entry) 1490 { 1491 *pmdp = entry; 1492 } 1493 1494 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1495 { 1496 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1497 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1498 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1499 return pmd; 1500 } 1501 1502 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1503 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1504 unsigned long address, pmd_t *pmdp) 1505 { 1506 pmd_t pmd; 1507 1508 pmd = *pmdp; 1509 pmdp_flush_direct(vma->vm_mm, address, pmdp); 1510 *pmdp = pmd_mkold(pmd); 1511 return pmd_young(pmd); 1512 } 1513 1514 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1515 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1516 unsigned long address, pmd_t *pmdp) 1517 { 1518 pmd_t pmd = *pmdp; 1519 1520 pmdp_flush_direct(mm, address, pmdp); 1521 pmd_clear(pmdp); 1522 return pmd; 1523 } 1524 1525 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1526 static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, 1527 unsigned long address, 1528 pmd_t *pmdp, int full) 1529 { 1530 pmd_t pmd = *pmdp; 1531 1532 if (!full) 1533 pmdp_flush_lazy(mm, address, pmdp); 1534 pmd_clear(pmdp); 1535 return pmd; 1536 } 1537 1538 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1539 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1540 unsigned long address, pmd_t *pmdp) 1541 { 1542 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1543 } 1544 1545 #define __HAVE_ARCH_PMDP_INVALIDATE 1546 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1547 unsigned long address, pmd_t *pmdp) 1548 { 1549 pmdp_flush_direct(vma->vm_mm, address, pmdp); 1550 } 1551 1552 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1553 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1554 unsigned long address, pmd_t *pmdp) 1555 { 1556 pmd_t pmd = *pmdp; 1557 1558 if (pmd_write(pmd)) { 1559 pmdp_flush_direct(mm, address, pmdp); 1560 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); 1561 } 1562 } 1563 1564 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1565 unsigned long address, 1566 pmd_t *pmdp) 1567 { 1568 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1569 } 1570 #define pmdp_collapse_flush pmdp_collapse_flush 1571 1572 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1573 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1574 1575 static inline int pmd_trans_huge(pmd_t pmd) 1576 { 1577 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1578 } 1579 1580 static inline int has_transparent_hugepage(void) 1581 { 1582 return MACHINE_HAS_HPAGE ? 1 : 0; 1583 } 1584 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1585 1586 /* 1587 * 64 bit swap entry format: 1588 * A page-table entry has some bits we have to treat in a special way. 1589 * Bits 52 and bit 55 have to be zero, otherwise a specification 1590 * exception will occur instead of a page translation exception. The 1591 * specification exception has the bad habit not to store necessary 1592 * information in the lowcore. 1593 * Bits 54 and 63 are used to indicate the page type. 1594 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1595 * This leaves the bits 0-51 and bits 56-62 to store type and offset. 1596 * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 1597 * for the offset. 1598 * | offset |01100|type |00| 1599 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1600 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1601 */ 1602 1603 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1604 #define __SWP_OFFSET_SHIFT 12 1605 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1606 #define __SWP_TYPE_SHIFT 2 1607 1608 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1609 { 1610 pte_t pte; 1611 1612 pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; 1613 pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1614 pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1615 return pte; 1616 } 1617 1618 static inline unsigned long __swp_type(swp_entry_t entry) 1619 { 1620 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1621 } 1622 1623 static inline unsigned long __swp_offset(swp_entry_t entry) 1624 { 1625 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1626 } 1627 1628 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1629 { 1630 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1631 } 1632 1633 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1634 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1635 1636 #endif /* !__ASSEMBLY__ */ 1637 1638 #define kern_addr_valid(addr) (1) 1639 1640 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1641 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1642 extern int s390_enable_sie(void); 1643 extern int s390_enable_skey(void); 1644 extern void s390_reset_cmma(struct mm_struct *mm); 1645 1646 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1647 #define HAVE_ARCH_UNMAPPED_AREA 1648 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1649 1650 /* 1651 * No page table caches to initialise 1652 */ 1653 static inline void pgtable_cache_init(void) { } 1654 static inline void check_pgt_cache(void) { } 1655 1656 #include <asm-generic/pgtable.h> 1657 1658 #endif /* _S390_PAGE_H */ 1659