1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/bug.h> 22 #include <asm/page.h> 23 #include <asm/uv.h> 24 25 extern pgd_t swapper_pg_dir[]; 26 extern pgd_t invalid_pg_dir[]; 27 extern void paging_init(void); 28 extern unsigned long s390_invalid_asce; 29 30 enum { 31 PG_DIRECT_MAP_4K = 0, 32 PG_DIRECT_MAP_1M, 33 PG_DIRECT_MAP_2G, 34 PG_DIRECT_MAP_MAX 35 }; 36 37 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 38 39 static inline void update_page_count(int level, long count) 40 { 41 if (IS_ENABLED(CONFIG_PROC_FS)) 42 atomic_long_add(count, &direct_pages_count[level]); 43 } 44 45 /* 46 * The S390 doesn't have any external MMU info: the kernel page 47 * tables contain all the necessary information. 48 */ 49 #define update_mmu_cache(vma, address, ptep) do { } while (0) 50 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 51 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 52 53 /* 54 * ZERO_PAGE is a global shared page that is always zero; used 55 * for zero-mapped memory areas etc.. 56 */ 57 58 extern unsigned long empty_zero_page; 59 extern unsigned long zero_page_mask; 60 61 #define ZERO_PAGE(vaddr) \ 62 (virt_to_page((void *)(empty_zero_page + \ 63 (((unsigned long)(vaddr)) &zero_page_mask)))) 64 #define __HAVE_COLOR_ZERO_PAGE 65 66 /* TODO: s390 cannot support io_remap_pfn_range... */ 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 70 #define pmd_ERROR(e) \ 71 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 72 #define pud_ERROR(e) \ 73 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 74 #define p4d_ERROR(e) \ 75 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 76 #define pgd_ERROR(e) \ 77 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 78 79 /* 80 * The vmalloc and module area will always be on the topmost area of the 81 * kernel mapping. 512GB are reserved for vmalloc by default. 82 * At the top of the vmalloc area a 2GB area is reserved where modules 83 * will reside. That makes sure that inter module branches always 84 * happen without trampolines and in addition the placement within a 85 * 2GB frame is branch prediction unit friendly. 86 */ 87 extern unsigned long __bootdata_preserved(VMALLOC_START); 88 extern unsigned long __bootdata_preserved(VMALLOC_END); 89 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 90 extern struct page *__bootdata_preserved(vmemmap); 91 extern unsigned long __bootdata_preserved(vmemmap_size); 92 93 extern unsigned long __bootdata_preserved(MODULES_VADDR); 94 extern unsigned long __bootdata_preserved(MODULES_END); 95 #define MODULES_VADDR MODULES_VADDR 96 #define MODULES_END MODULES_END 97 #define MODULES_LEN (1UL << 31) 98 99 static inline int is_module_addr(void *addr) 100 { 101 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 102 if (addr < (void *)MODULES_VADDR) 103 return 0; 104 if (addr > (void *)MODULES_END) 105 return 0; 106 return 1; 107 } 108 109 /* 110 * A 64 bit pagetable entry of S390 has following format: 111 * | PFRA |0IPC| OS | 112 * 0000000000111111111122222222223333333333444444444455555555556666 113 * 0123456789012345678901234567890123456789012345678901234567890123 114 * 115 * I Page-Invalid Bit: Page is not available for address-translation 116 * P Page-Protection Bit: Store access not possible for page 117 * C Change-bit override: HW is not required to set change bit 118 * 119 * A 64 bit segmenttable entry of S390 has following format: 120 * | P-table origin | TT 121 * 0000000000111111111122222222223333333333444444444455555555556666 122 * 0123456789012345678901234567890123456789012345678901234567890123 123 * 124 * I Segment-Invalid Bit: Segment is not available for address-translation 125 * C Common-Segment Bit: Segment is not private (PoP 3-30) 126 * P Page-Protection Bit: Store access not possible for page 127 * TT Type 00 128 * 129 * A 64 bit region table entry of S390 has following format: 130 * | S-table origin | TF TTTL 131 * 0000000000111111111122222222223333333333444444444455555555556666 132 * 0123456789012345678901234567890123456789012345678901234567890123 133 * 134 * I Segment-Invalid Bit: Segment is not available for address-translation 135 * TT Type 01 136 * TF 137 * TL Table length 138 * 139 * The 64 bit regiontable origin of S390 has following format: 140 * | region table origon | DTTL 141 * 0000000000111111111122222222223333333333444444444455555555556666 142 * 0123456789012345678901234567890123456789012345678901234567890123 143 * 144 * X Space-Switch event: 145 * G Segment-Invalid Bit: 146 * P Private-Space Bit: 147 * S Storage-Alteration: 148 * R Real space 149 * TL Table-Length: 150 * 151 * A storage key has the following format: 152 * | ACC |F|R|C|0| 153 * 0 3 4 5 6 7 154 * ACC: access key 155 * F : fetch protection bit 156 * R : referenced bit 157 * C : changed bit 158 */ 159 160 /* Hardware bits in the page table entry */ 161 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 162 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 163 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 164 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 165 166 /* Software bits in the page table entry */ 167 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 168 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 169 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 170 #define _PAGE_READ 0x010 /* SW pte read bit */ 171 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 172 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 173 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 174 175 #ifdef CONFIG_MEM_SOFT_DIRTY 176 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 177 #else 178 #define _PAGE_SOFT_DIRTY 0x000 179 #endif 180 181 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 182 183 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 184 185 /* Set of bits not changed in pte_modify */ 186 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 187 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 188 189 /* 190 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 191 * HW bit and all SW bits. 192 */ 193 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 194 195 /* 196 * handle_pte_fault uses pte_present and pte_none to find out the pte type 197 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 198 * distinguish present from not-present ptes. It is changed only with the page 199 * table lock held. 200 * 201 * The following table gives the different possible bit combinations for 202 * the pte hardware and software bits in the last 12 bits of a pte 203 * (. unassigned bit, x don't care, t swap type): 204 * 205 * 842100000000 206 * 000084210000 207 * 000000008421 208 * .IR.uswrdy.p 209 * empty .10.00000000 210 * swap .11..ttttt.0 211 * prot-none, clean, old .11.xx0000.1 212 * prot-none, clean, young .11.xx0001.1 213 * prot-none, dirty, old .11.xx0010.1 214 * prot-none, dirty, young .11.xx0011.1 215 * read-only, clean, old .11.xx0100.1 216 * read-only, clean, young .01.xx0101.1 217 * read-only, dirty, old .11.xx0110.1 218 * read-only, dirty, young .01.xx0111.1 219 * read-write, clean, old .11.xx1100.1 220 * read-write, clean, young .01.xx1101.1 221 * read-write, dirty, old .10.xx1110.1 222 * read-write, dirty, young .00.xx1111.1 223 * HW-bits: R read-only, I invalid 224 * SW-bits: p present, y young, d dirty, r read, w write, s special, 225 * u unused, l large 226 * 227 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 228 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 229 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 230 */ 231 232 /* Bits in the segment/region table address-space-control-element */ 233 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 234 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 235 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 236 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 237 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 238 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 239 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 240 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 241 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 242 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 243 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 244 245 /* Bits in the region table entry */ 246 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 247 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 248 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 249 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 250 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 251 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 252 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 253 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 254 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 255 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 256 257 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 258 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 259 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 260 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 261 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 262 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 263 264 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 265 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 266 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 267 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 268 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 269 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 270 271 #ifdef CONFIG_MEM_SOFT_DIRTY 272 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 273 #else 274 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 275 #endif 276 277 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 278 279 /* Bits in the segment table entry */ 280 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 281 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 282 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 283 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 284 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 285 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 286 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 287 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 288 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 289 290 #define _SEGMENT_ENTRY (0) 291 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 292 293 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 294 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 295 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 296 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 297 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 298 299 #ifdef CONFIG_MEM_SOFT_DIRTY 300 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 301 #else 302 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 303 #endif 304 305 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 306 #define _PAGE_ENTRIES 256 /* number of page table entries */ 307 308 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 309 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 310 311 #define _REGION1_SHIFT 53 312 #define _REGION2_SHIFT 42 313 #define _REGION3_SHIFT 31 314 #define _SEGMENT_SHIFT 20 315 316 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 317 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 318 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 319 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 320 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 321 322 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 323 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 324 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 325 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 326 327 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 328 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 329 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 330 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 331 332 #define PMD_SHIFT _SEGMENT_SHIFT 333 #define PUD_SHIFT _REGION3_SHIFT 334 #define P4D_SHIFT _REGION2_SHIFT 335 #define PGDIR_SHIFT _REGION1_SHIFT 336 337 #define PMD_SIZE _SEGMENT_SIZE 338 #define PUD_SIZE _REGION3_SIZE 339 #define P4D_SIZE _REGION2_SIZE 340 #define PGDIR_SIZE _REGION1_SIZE 341 342 #define PMD_MASK _SEGMENT_MASK 343 #define PUD_MASK _REGION3_MASK 344 #define P4D_MASK _REGION2_MASK 345 #define PGDIR_MASK _REGION1_MASK 346 347 #define PTRS_PER_PTE _PAGE_ENTRIES 348 #define PTRS_PER_PMD _CRST_ENTRIES 349 #define PTRS_PER_PUD _CRST_ENTRIES 350 #define PTRS_PER_P4D _CRST_ENTRIES 351 #define PTRS_PER_PGD _CRST_ENTRIES 352 353 /* 354 * Segment table and region3 table entry encoding 355 * (R = read-only, I = invalid, y = young bit): 356 * dy..R...I...wr 357 * prot-none, clean, old 00..1...1...00 358 * prot-none, clean, young 01..1...1...00 359 * prot-none, dirty, old 10..1...1...00 360 * prot-none, dirty, young 11..1...1...00 361 * read-only, clean, old 00..1...1...01 362 * read-only, clean, young 01..1...0...01 363 * read-only, dirty, old 10..1...1...01 364 * read-only, dirty, young 11..1...0...01 365 * read-write, clean, old 00..1...1...11 366 * read-write, clean, young 01..1...0...11 367 * read-write, dirty, old 10..0...1...11 368 * read-write, dirty, young 11..0...0...11 369 * The segment table origin is used to distinguish empty (origin==0) from 370 * read-write, old segment table entries (origin!=0) 371 * HW-bits: R read-only, I invalid 372 * SW-bits: y young, d dirty, r read, w write 373 */ 374 375 /* Page status table bits for virtualization */ 376 #define PGSTE_ACC_BITS 0xf000000000000000UL 377 #define PGSTE_FP_BIT 0x0800000000000000UL 378 #define PGSTE_PCL_BIT 0x0080000000000000UL 379 #define PGSTE_HR_BIT 0x0040000000000000UL 380 #define PGSTE_HC_BIT 0x0020000000000000UL 381 #define PGSTE_GR_BIT 0x0004000000000000UL 382 #define PGSTE_GC_BIT 0x0002000000000000UL 383 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 384 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 385 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 386 387 /* Guest Page State used for virtualization */ 388 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 389 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 390 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 391 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 392 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 393 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 394 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 395 396 /* 397 * A user page table pointer has the space-switch-event bit, the 398 * private-space-control bit and the storage-alteration-event-control 399 * bit set. A kernel page table pointer doesn't need them. 400 */ 401 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 402 _ASCE_ALT_EVENT) 403 404 /* 405 * Page protection definitions. 406 */ 407 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 408 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 409 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 410 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 411 _PAGE_INVALID | _PAGE_PROTECT) 412 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 413 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 414 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 415 _PAGE_INVALID | _PAGE_PROTECT) 416 417 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 418 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 419 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 420 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 421 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 422 _PAGE_PROTECT | _PAGE_NOEXEC) 423 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 424 _PAGE_YOUNG | _PAGE_DIRTY) 425 426 /* 427 * On s390 the page table entry has an invalid bit and a read-only bit. 428 * Read permission implies execute permission and write permission 429 * implies read permission. 430 */ 431 /*xwr*/ 432 433 /* 434 * Segment entry (large page) protection definitions. 435 */ 436 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 437 _SEGMENT_ENTRY_PROTECT) 438 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 439 _SEGMENT_ENTRY_READ | \ 440 _SEGMENT_ENTRY_NOEXEC) 441 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 442 _SEGMENT_ENTRY_READ) 443 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 444 _SEGMENT_ENTRY_WRITE | \ 445 _SEGMENT_ENTRY_NOEXEC) 446 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 447 _SEGMENT_ENTRY_WRITE) 448 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 449 _SEGMENT_ENTRY_LARGE | \ 450 _SEGMENT_ENTRY_READ | \ 451 _SEGMENT_ENTRY_WRITE | \ 452 _SEGMENT_ENTRY_YOUNG | \ 453 _SEGMENT_ENTRY_DIRTY | \ 454 _SEGMENT_ENTRY_NOEXEC) 455 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 456 _SEGMENT_ENTRY_LARGE | \ 457 _SEGMENT_ENTRY_READ | \ 458 _SEGMENT_ENTRY_YOUNG | \ 459 _SEGMENT_ENTRY_PROTECT | \ 460 _SEGMENT_ENTRY_NOEXEC) 461 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 462 _SEGMENT_ENTRY_LARGE | \ 463 _SEGMENT_ENTRY_READ | \ 464 _SEGMENT_ENTRY_WRITE | \ 465 _SEGMENT_ENTRY_YOUNG | \ 466 _SEGMENT_ENTRY_DIRTY) 467 468 /* 469 * Region3 entry (large page) protection definitions. 470 */ 471 472 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 473 _REGION3_ENTRY_LARGE | \ 474 _REGION3_ENTRY_READ | \ 475 _REGION3_ENTRY_WRITE | \ 476 _REGION3_ENTRY_YOUNG | \ 477 _REGION3_ENTRY_DIRTY | \ 478 _REGION_ENTRY_NOEXEC) 479 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 480 _REGION3_ENTRY_LARGE | \ 481 _REGION3_ENTRY_READ | \ 482 _REGION3_ENTRY_YOUNG | \ 483 _REGION_ENTRY_PROTECT | \ 484 _REGION_ENTRY_NOEXEC) 485 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 486 _REGION3_ENTRY_LARGE | \ 487 _REGION3_ENTRY_READ | \ 488 _REGION3_ENTRY_WRITE | \ 489 _REGION3_ENTRY_YOUNG | \ 490 _REGION3_ENTRY_DIRTY) 491 492 static inline bool mm_p4d_folded(struct mm_struct *mm) 493 { 494 return mm->context.asce_limit <= _REGION1_SIZE; 495 } 496 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 497 498 static inline bool mm_pud_folded(struct mm_struct *mm) 499 { 500 return mm->context.asce_limit <= _REGION2_SIZE; 501 } 502 #define mm_pud_folded(mm) mm_pud_folded(mm) 503 504 static inline bool mm_pmd_folded(struct mm_struct *mm) 505 { 506 return mm->context.asce_limit <= _REGION3_SIZE; 507 } 508 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 509 510 static inline int mm_has_pgste(struct mm_struct *mm) 511 { 512 #ifdef CONFIG_PGSTE 513 if (unlikely(mm->context.has_pgste)) 514 return 1; 515 #endif 516 return 0; 517 } 518 519 static inline int mm_is_protected(struct mm_struct *mm) 520 { 521 #ifdef CONFIG_PGSTE 522 if (unlikely(atomic_read(&mm->context.protected_count))) 523 return 1; 524 #endif 525 return 0; 526 } 527 528 static inline int mm_alloc_pgste(struct mm_struct *mm) 529 { 530 #ifdef CONFIG_PGSTE 531 if (unlikely(mm->context.alloc_pgste)) 532 return 1; 533 #endif 534 return 0; 535 } 536 537 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 538 { 539 return __pte(pte_val(pte) & ~pgprot_val(prot)); 540 } 541 542 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 543 { 544 return __pte(pte_val(pte) | pgprot_val(prot)); 545 } 546 547 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 548 { 549 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 550 } 551 552 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 553 { 554 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 555 } 556 557 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 558 { 559 return __pud(pud_val(pud) & ~pgprot_val(prot)); 560 } 561 562 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 563 { 564 return __pud(pud_val(pud) | pgprot_val(prot)); 565 } 566 567 /* 568 * As soon as the guest uses storage keys or enables PV, we deduplicate all 569 * mapped shared zeropages and prevent new shared zeropages from getting 570 * mapped. 571 */ 572 #define mm_forbids_zeropage mm_forbids_zeropage 573 static inline int mm_forbids_zeropage(struct mm_struct *mm) 574 { 575 #ifdef CONFIG_PGSTE 576 if (!mm->context.allow_cow_sharing) 577 return 1; 578 #endif 579 return 0; 580 } 581 582 static inline int mm_uses_skeys(struct mm_struct *mm) 583 { 584 #ifdef CONFIG_PGSTE 585 if (mm->context.uses_skeys) 586 return 1; 587 #endif 588 return 0; 589 } 590 591 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 592 { 593 union register_pair r1 = { .even = old, .odd = new, }; 594 unsigned long address = (unsigned long)ptr | 1; 595 596 asm volatile( 597 " csp %[r1],%[address]" 598 : [r1] "+&d" (r1.pair), "+m" (*ptr) 599 : [address] "d" (address) 600 : "cc"); 601 } 602 603 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 604 { 605 union register_pair r1 = { .even = old, .odd = new, }; 606 unsigned long address = (unsigned long)ptr | 1; 607 608 asm volatile( 609 " cspg %[r1],%[address]" 610 : [r1] "+&d" (r1.pair), "+m" (*ptr) 611 : [address] "d" (address) 612 : "cc"); 613 } 614 615 #define CRDTE_DTT_PAGE 0x00UL 616 #define CRDTE_DTT_SEGMENT 0x10UL 617 #define CRDTE_DTT_REGION3 0x14UL 618 #define CRDTE_DTT_REGION2 0x18UL 619 #define CRDTE_DTT_REGION1 0x1cUL 620 621 static inline void crdte(unsigned long old, unsigned long new, 622 unsigned long *table, unsigned long dtt, 623 unsigned long address, unsigned long asce) 624 { 625 union register_pair r1 = { .even = old, .odd = new, }; 626 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 627 628 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 629 : [r1] "+&d" (r1.pair) 630 : [r2] "d" (r2.pair), [asce] "a" (asce) 631 : "memory", "cc"); 632 } 633 634 /* 635 * pgd/p4d/pud/pmd/pte query functions 636 */ 637 static inline int pgd_folded(pgd_t pgd) 638 { 639 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 640 } 641 642 static inline int pgd_present(pgd_t pgd) 643 { 644 if (pgd_folded(pgd)) 645 return 1; 646 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 647 } 648 649 static inline int pgd_none(pgd_t pgd) 650 { 651 if (pgd_folded(pgd)) 652 return 0; 653 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 654 } 655 656 static inline int pgd_bad(pgd_t pgd) 657 { 658 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 659 return 0; 660 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 661 } 662 663 static inline unsigned long pgd_pfn(pgd_t pgd) 664 { 665 unsigned long origin_mask; 666 667 origin_mask = _REGION_ENTRY_ORIGIN; 668 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 669 } 670 671 static inline int p4d_folded(p4d_t p4d) 672 { 673 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 674 } 675 676 static inline int p4d_present(p4d_t p4d) 677 { 678 if (p4d_folded(p4d)) 679 return 1; 680 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 681 } 682 683 static inline int p4d_none(p4d_t p4d) 684 { 685 if (p4d_folded(p4d)) 686 return 0; 687 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 688 } 689 690 static inline unsigned long p4d_pfn(p4d_t p4d) 691 { 692 unsigned long origin_mask; 693 694 origin_mask = _REGION_ENTRY_ORIGIN; 695 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 696 } 697 698 static inline int pud_folded(pud_t pud) 699 { 700 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 701 } 702 703 static inline int pud_present(pud_t pud) 704 { 705 if (pud_folded(pud)) 706 return 1; 707 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 708 } 709 710 static inline int pud_none(pud_t pud) 711 { 712 if (pud_folded(pud)) 713 return 0; 714 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 715 } 716 717 #define pud_leaf pud_large 718 static inline int pud_large(pud_t pud) 719 { 720 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 721 return 0; 722 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 723 } 724 725 #define pmd_leaf pmd_large 726 static inline int pmd_large(pmd_t pmd) 727 { 728 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 729 } 730 731 static inline int pmd_bad(pmd_t pmd) 732 { 733 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 734 return 1; 735 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 736 } 737 738 static inline int pud_bad(pud_t pud) 739 { 740 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 741 742 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 743 return 1; 744 if (type < _REGION_ENTRY_TYPE_R3) 745 return 0; 746 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 747 } 748 749 static inline int p4d_bad(p4d_t p4d) 750 { 751 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 752 753 if (type > _REGION_ENTRY_TYPE_R2) 754 return 1; 755 if (type < _REGION_ENTRY_TYPE_R2) 756 return 0; 757 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 758 } 759 760 static inline int pmd_present(pmd_t pmd) 761 { 762 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 763 } 764 765 static inline int pmd_none(pmd_t pmd) 766 { 767 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 768 } 769 770 #define pmd_write pmd_write 771 static inline int pmd_write(pmd_t pmd) 772 { 773 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 774 } 775 776 #define pud_write pud_write 777 static inline int pud_write(pud_t pud) 778 { 779 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 780 } 781 782 static inline int pmd_dirty(pmd_t pmd) 783 { 784 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 785 } 786 787 #define pmd_young pmd_young 788 static inline int pmd_young(pmd_t pmd) 789 { 790 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 791 } 792 793 static inline int pte_present(pte_t pte) 794 { 795 /* Bit pattern: (pte & 0x001) == 0x001 */ 796 return (pte_val(pte) & _PAGE_PRESENT) != 0; 797 } 798 799 static inline int pte_none(pte_t pte) 800 { 801 /* Bit pattern: pte == 0x400 */ 802 return pte_val(pte) == _PAGE_INVALID; 803 } 804 805 static inline int pte_swap(pte_t pte) 806 { 807 /* Bit pattern: (pte & 0x201) == 0x200 */ 808 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 809 == _PAGE_PROTECT; 810 } 811 812 static inline int pte_special(pte_t pte) 813 { 814 return (pte_val(pte) & _PAGE_SPECIAL); 815 } 816 817 #define __HAVE_ARCH_PTE_SAME 818 static inline int pte_same(pte_t a, pte_t b) 819 { 820 return pte_val(a) == pte_val(b); 821 } 822 823 #ifdef CONFIG_NUMA_BALANCING 824 static inline int pte_protnone(pte_t pte) 825 { 826 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 827 } 828 829 static inline int pmd_protnone(pmd_t pmd) 830 { 831 /* pmd_large(pmd) implies pmd_present(pmd) */ 832 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 833 } 834 #endif 835 836 static inline int pte_swp_exclusive(pte_t pte) 837 { 838 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 839 } 840 841 static inline pte_t pte_swp_mkexclusive(pte_t pte) 842 { 843 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 844 } 845 846 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 847 { 848 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 849 } 850 851 static inline int pte_soft_dirty(pte_t pte) 852 { 853 return pte_val(pte) & _PAGE_SOFT_DIRTY; 854 } 855 #define pte_swp_soft_dirty pte_soft_dirty 856 857 static inline pte_t pte_mksoft_dirty(pte_t pte) 858 { 859 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 860 } 861 #define pte_swp_mksoft_dirty pte_mksoft_dirty 862 863 static inline pte_t pte_clear_soft_dirty(pte_t pte) 864 { 865 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 866 } 867 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 868 869 static inline int pmd_soft_dirty(pmd_t pmd) 870 { 871 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 872 } 873 874 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 875 { 876 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 877 } 878 879 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 880 { 881 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 882 } 883 884 /* 885 * query functions pte_write/pte_dirty/pte_young only work if 886 * pte_present() is true. Undefined behaviour if not.. 887 */ 888 static inline int pte_write(pte_t pte) 889 { 890 return (pte_val(pte) & _PAGE_WRITE) != 0; 891 } 892 893 static inline int pte_dirty(pte_t pte) 894 { 895 return (pte_val(pte) & _PAGE_DIRTY) != 0; 896 } 897 898 static inline int pte_young(pte_t pte) 899 { 900 return (pte_val(pte) & _PAGE_YOUNG) != 0; 901 } 902 903 #define __HAVE_ARCH_PTE_UNUSED 904 static inline int pte_unused(pte_t pte) 905 { 906 return pte_val(pte) & _PAGE_UNUSED; 907 } 908 909 /* 910 * Extract the pgprot value from the given pte while at the same time making it 911 * usable for kernel address space mappings where fault driven dirty and 912 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 913 * must not be set. 914 */ 915 static inline pgprot_t pte_pgprot(pte_t pte) 916 { 917 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 918 919 if (pte_write(pte)) 920 pte_flags |= pgprot_val(PAGE_KERNEL); 921 else 922 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 923 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 924 925 return __pgprot(pte_flags); 926 } 927 928 /* 929 * pgd/pmd/pte modification functions 930 */ 931 932 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 933 { 934 WRITE_ONCE(*pgdp, pgd); 935 } 936 937 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 938 { 939 WRITE_ONCE(*p4dp, p4d); 940 } 941 942 static inline void set_pud(pud_t *pudp, pud_t pud) 943 { 944 WRITE_ONCE(*pudp, pud); 945 } 946 947 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 948 { 949 WRITE_ONCE(*pmdp, pmd); 950 } 951 952 static inline void set_pte(pte_t *ptep, pte_t pte) 953 { 954 WRITE_ONCE(*ptep, pte); 955 } 956 957 static inline void pgd_clear(pgd_t *pgd) 958 { 959 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 960 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 961 } 962 963 static inline void p4d_clear(p4d_t *p4d) 964 { 965 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 966 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 967 } 968 969 static inline void pud_clear(pud_t *pud) 970 { 971 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 972 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 973 } 974 975 static inline void pmd_clear(pmd_t *pmdp) 976 { 977 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 978 } 979 980 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 981 { 982 set_pte(ptep, __pte(_PAGE_INVALID)); 983 } 984 985 /* 986 * The following pte modification functions only work if 987 * pte_present() is true. Undefined behaviour if not.. 988 */ 989 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 990 { 991 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 992 pte = set_pte_bit(pte, newprot); 993 /* 994 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 995 * has the invalid bit set, clear it again for readable, young pages 996 */ 997 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 998 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 999 /* 1000 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 1001 * protection bit set, clear it again for writable, dirty pages 1002 */ 1003 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1004 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1005 return pte; 1006 } 1007 1008 static inline pte_t pte_wrprotect(pte_t pte) 1009 { 1010 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1011 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1012 } 1013 1014 static inline pte_t pte_mkwrite_novma(pte_t pte) 1015 { 1016 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1017 if (pte_val(pte) & _PAGE_DIRTY) 1018 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1019 return pte; 1020 } 1021 1022 static inline pte_t pte_mkclean(pte_t pte) 1023 { 1024 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1025 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1026 } 1027 1028 static inline pte_t pte_mkdirty(pte_t pte) 1029 { 1030 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1031 if (pte_val(pte) & _PAGE_WRITE) 1032 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1033 return pte; 1034 } 1035 1036 static inline pte_t pte_mkold(pte_t pte) 1037 { 1038 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1039 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1040 } 1041 1042 static inline pte_t pte_mkyoung(pte_t pte) 1043 { 1044 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1045 if (pte_val(pte) & _PAGE_READ) 1046 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1047 return pte; 1048 } 1049 1050 static inline pte_t pte_mkspecial(pte_t pte) 1051 { 1052 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1053 } 1054 1055 #ifdef CONFIG_HUGETLB_PAGE 1056 static inline pte_t pte_mkhuge(pte_t pte) 1057 { 1058 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1059 } 1060 #endif 1061 1062 #define IPTE_GLOBAL 0 1063 #define IPTE_LOCAL 1 1064 1065 #define IPTE_NODAT 0x400 1066 #define IPTE_GUEST_ASCE 0x800 1067 1068 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1069 unsigned long opt, unsigned long asce, 1070 int local) 1071 { 1072 unsigned long pto; 1073 1074 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1075 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1076 : "+m" (*ptep) 1077 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1078 [asce] "a" (asce), [m4] "i" (local)); 1079 } 1080 1081 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1082 unsigned long opt, unsigned long asce, 1083 int local) 1084 { 1085 unsigned long pto = __pa(ptep); 1086 1087 if (__builtin_constant_p(opt) && opt == 0) { 1088 /* Invalidation + TLB flush for the pte */ 1089 asm volatile( 1090 " ipte %[r1],%[r2],0,%[m4]" 1091 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1092 [m4] "i" (local)); 1093 return; 1094 } 1095 1096 /* Invalidate ptes with options + TLB flush of the ptes */ 1097 opt = opt | (asce & _ASCE_ORIGIN); 1098 asm volatile( 1099 " ipte %[r1],%[r2],%[r3],%[m4]" 1100 : [r2] "+a" (address), [r3] "+a" (opt) 1101 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1102 } 1103 1104 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1105 pte_t *ptep, int local) 1106 { 1107 unsigned long pto = __pa(ptep); 1108 1109 /* Invalidate a range of ptes + TLB flush of the ptes */ 1110 do { 1111 asm volatile( 1112 " ipte %[r1],%[r2],%[r3],%[m4]" 1113 : [r2] "+a" (address), [r3] "+a" (nr) 1114 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1115 } while (nr != 255); 1116 } 1117 1118 /* 1119 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1120 * both clear the TLB for the unmapped pte. The reason is that 1121 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1122 * to modify an active pte. The sequence is 1123 * 1) ptep_get_and_clear 1124 * 2) set_pte_at 1125 * 3) flush_tlb_range 1126 * On s390 the tlb needs to get flushed with the modification of the pte 1127 * if the pte is active. The only way how this can be implemented is to 1128 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1129 * is a nop. 1130 */ 1131 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1132 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1133 1134 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1135 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1136 unsigned long addr, pte_t *ptep) 1137 { 1138 pte_t pte = *ptep; 1139 1140 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1141 return pte_young(pte); 1142 } 1143 1144 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1145 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1146 unsigned long address, pte_t *ptep) 1147 { 1148 return ptep_test_and_clear_young(vma, address, ptep); 1149 } 1150 1151 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1152 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1153 unsigned long addr, pte_t *ptep) 1154 { 1155 pte_t res; 1156 1157 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1158 /* At this point the reference through the mapping is still present */ 1159 if (mm_is_protected(mm) && pte_present(res)) 1160 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1161 return res; 1162 } 1163 1164 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1165 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1166 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1167 pte_t *, pte_t, pte_t); 1168 1169 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1170 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1171 unsigned long addr, pte_t *ptep) 1172 { 1173 pte_t res; 1174 1175 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1176 /* At this point the reference through the mapping is still present */ 1177 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1178 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1179 return res; 1180 } 1181 1182 /* 1183 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1184 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1185 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1186 * cannot be accessed while the batched unmap is running. In this case 1187 * full==1 and a simple pte_clear is enough. See tlb.h. 1188 */ 1189 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1190 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1191 unsigned long addr, 1192 pte_t *ptep, int full) 1193 { 1194 pte_t res; 1195 1196 if (full) { 1197 res = *ptep; 1198 set_pte(ptep, __pte(_PAGE_INVALID)); 1199 } else { 1200 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1201 } 1202 /* Nothing to do */ 1203 if (!mm_is_protected(mm) || !pte_present(res)) 1204 return res; 1205 /* 1206 * At this point the reference through the mapping is still present. 1207 * The notifier should have destroyed all protected vCPUs at this 1208 * point, so the destroy should be successful. 1209 */ 1210 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1211 return res; 1212 /* 1213 * If something went wrong and the page could not be destroyed, or 1214 * if this is not a mm teardown, the slower export is used as 1215 * fallback instead. 1216 */ 1217 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1218 return res; 1219 } 1220 1221 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1222 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1223 unsigned long addr, pte_t *ptep) 1224 { 1225 pte_t pte = *ptep; 1226 1227 if (pte_write(pte)) 1228 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1229 } 1230 1231 /* 1232 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1233 * bits in the comparison. Those might change e.g. because of dirty and young 1234 * tracking. 1235 */ 1236 static inline int pte_allow_rdp(pte_t old, pte_t new) 1237 { 1238 /* 1239 * Only allow changes from RO to RW 1240 */ 1241 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1242 return 0; 1243 1244 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1245 } 1246 1247 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1248 unsigned long address, 1249 pte_t *ptep) 1250 { 1251 /* 1252 * RDP might not have propagated the PTE protection reset to all CPUs, 1253 * so there could be spurious TLB protection faults. 1254 * NOTE: This will also be called when a racing pagetable update on 1255 * another thread already installed the correct PTE. Both cases cannot 1256 * really be distinguished. 1257 * Therefore, only do the local TLB flush when RDP can be used, and the 1258 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1259 * A local RDP can be used to do the flush. 1260 */ 1261 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1262 __ptep_rdp(address, ptep, 0, 0, 1); 1263 } 1264 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1265 1266 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1267 pte_t new); 1268 1269 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1270 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1271 unsigned long addr, pte_t *ptep, 1272 pte_t entry, int dirty) 1273 { 1274 if (pte_same(*ptep, entry)) 1275 return 0; 1276 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1277 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1278 else 1279 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1280 return 1; 1281 } 1282 1283 /* 1284 * Additional functions to handle KVM guest page tables 1285 */ 1286 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1287 pte_t *ptep, pte_t entry); 1288 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1289 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1290 pte_t *ptep, unsigned long bits); 1291 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1292 pte_t *ptep, int prot, unsigned long bit); 1293 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1294 pte_t *ptep , int reset); 1295 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1296 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1297 pte_t *sptep, pte_t *tptep, pte_t pte); 1298 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1299 1300 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1301 pte_t *ptep); 1302 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1303 unsigned char key, bool nq); 1304 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1305 unsigned char key, unsigned char *oldkey, 1306 bool nq, bool mr, bool mc); 1307 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1308 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1309 unsigned char *key); 1310 1311 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1312 unsigned long bits, unsigned long value); 1313 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1314 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1315 unsigned long *oldpte, unsigned long *oldpgste); 1316 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1317 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1318 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1319 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1320 1321 #define pgprot_writecombine pgprot_writecombine 1322 pgprot_t pgprot_writecombine(pgprot_t prot); 1323 1324 #define pgprot_writethrough pgprot_writethrough 1325 pgprot_t pgprot_writethrough(pgprot_t prot); 1326 1327 /* 1328 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1329 * are within the same folio, PMD and VMA. 1330 */ 1331 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1332 pte_t *ptep, pte_t entry, unsigned int nr) 1333 { 1334 if (pte_present(entry)) 1335 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1336 if (mm_has_pgste(mm)) { 1337 for (;;) { 1338 ptep_set_pte_at(mm, addr, ptep, entry); 1339 if (--nr == 0) 1340 break; 1341 ptep++; 1342 entry = __pte(pte_val(entry) + PAGE_SIZE); 1343 addr += PAGE_SIZE; 1344 } 1345 } else { 1346 for (;;) { 1347 set_pte(ptep, entry); 1348 if (--nr == 0) 1349 break; 1350 ptep++; 1351 entry = __pte(pte_val(entry) + PAGE_SIZE); 1352 } 1353 } 1354 } 1355 #define set_ptes set_ptes 1356 1357 /* 1358 * Conversion functions: convert a page and protection to a page entry, 1359 * and a page entry and page directory to the page they refer to. 1360 */ 1361 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1362 { 1363 pte_t __pte; 1364 1365 __pte = __pte(physpage | pgprot_val(pgprot)); 1366 if (!MACHINE_HAS_NX) 1367 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1368 return pte_mkyoung(__pte); 1369 } 1370 1371 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1372 { 1373 unsigned long physpage = page_to_phys(page); 1374 pte_t __pte = mk_pte_phys(physpage, pgprot); 1375 1376 if (pte_write(__pte) && PageDirty(page)) 1377 __pte = pte_mkdirty(__pte); 1378 return __pte; 1379 } 1380 1381 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1382 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1383 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1384 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1385 1386 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1387 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1388 1389 static inline unsigned long pmd_deref(pmd_t pmd) 1390 { 1391 unsigned long origin_mask; 1392 1393 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1394 if (pmd_large(pmd)) 1395 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1396 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1397 } 1398 1399 static inline unsigned long pmd_pfn(pmd_t pmd) 1400 { 1401 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1402 } 1403 1404 static inline unsigned long pud_deref(pud_t pud) 1405 { 1406 unsigned long origin_mask; 1407 1408 origin_mask = _REGION_ENTRY_ORIGIN; 1409 if (pud_leaf(pud)) 1410 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1411 return (unsigned long)__va(pud_val(pud) & origin_mask); 1412 } 1413 1414 static inline unsigned long pud_pfn(pud_t pud) 1415 { 1416 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1417 } 1418 1419 /* 1420 * The pgd_offset function *always* adds the index for the top-level 1421 * region/segment table. This is done to get a sequence like the 1422 * following to work: 1423 * pgdp = pgd_offset(current->mm, addr); 1424 * pgd = READ_ONCE(*pgdp); 1425 * p4dp = p4d_offset(&pgd, addr); 1426 * ... 1427 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1428 * only add an index if they dereferenced the pointer. 1429 */ 1430 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1431 { 1432 unsigned long rste; 1433 unsigned int shift; 1434 1435 /* Get the first entry of the top level table */ 1436 rste = pgd_val(*pgd); 1437 /* Pick up the shift from the table type of the first entry */ 1438 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1439 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1440 } 1441 1442 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1443 1444 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1445 { 1446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1447 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1448 return (p4d_t *) pgdp; 1449 } 1450 #define p4d_offset_lockless p4d_offset_lockless 1451 1452 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1453 { 1454 return p4d_offset_lockless(pgdp, *pgdp, address); 1455 } 1456 1457 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1458 { 1459 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1460 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1461 return (pud_t *) p4dp; 1462 } 1463 #define pud_offset_lockless pud_offset_lockless 1464 1465 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1466 { 1467 return pud_offset_lockless(p4dp, *p4dp, address); 1468 } 1469 #define pud_offset pud_offset 1470 1471 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1472 { 1473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1474 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1475 return (pmd_t *) pudp; 1476 } 1477 #define pmd_offset_lockless pmd_offset_lockless 1478 1479 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1480 { 1481 return pmd_offset_lockless(pudp, *pudp, address); 1482 } 1483 #define pmd_offset pmd_offset 1484 1485 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1486 { 1487 return (unsigned long) pmd_deref(pmd); 1488 } 1489 1490 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1491 { 1492 return end <= current->mm->context.asce_limit; 1493 } 1494 #define gup_fast_permitted gup_fast_permitted 1495 1496 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1497 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1498 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1499 1500 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1501 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1502 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1503 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1504 1505 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1506 { 1507 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1508 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1509 } 1510 1511 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1512 { 1513 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1514 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1515 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1516 return pmd; 1517 } 1518 1519 static inline pmd_t pmd_mkclean(pmd_t pmd) 1520 { 1521 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1522 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1523 } 1524 1525 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1526 { 1527 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1528 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1529 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1530 return pmd; 1531 } 1532 1533 static inline pud_t pud_wrprotect(pud_t pud) 1534 { 1535 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1536 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1537 } 1538 1539 static inline pud_t pud_mkwrite(pud_t pud) 1540 { 1541 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1542 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1543 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1544 return pud; 1545 } 1546 1547 static inline pud_t pud_mkclean(pud_t pud) 1548 { 1549 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1550 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1551 } 1552 1553 static inline pud_t pud_mkdirty(pud_t pud) 1554 { 1555 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1556 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1557 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1558 return pud; 1559 } 1560 1561 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1562 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1563 { 1564 /* 1565 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1566 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1567 */ 1568 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1569 return pgprot_val(SEGMENT_NONE); 1570 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1571 return pgprot_val(SEGMENT_RO); 1572 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1573 return pgprot_val(SEGMENT_RX); 1574 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1575 return pgprot_val(SEGMENT_RW); 1576 return pgprot_val(SEGMENT_RWX); 1577 } 1578 1579 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1580 { 1581 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1582 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1583 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1584 return pmd; 1585 } 1586 1587 static inline pmd_t pmd_mkold(pmd_t pmd) 1588 { 1589 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1590 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1591 } 1592 1593 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1594 { 1595 unsigned long mask; 1596 1597 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1598 mask |= _SEGMENT_ENTRY_DIRTY; 1599 mask |= _SEGMENT_ENTRY_YOUNG; 1600 mask |= _SEGMENT_ENTRY_LARGE; 1601 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1602 pmd = __pmd(pmd_val(pmd) & mask); 1603 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1604 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1605 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1606 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1607 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1608 return pmd; 1609 } 1610 1611 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1612 { 1613 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1614 } 1615 1616 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1617 1618 static inline void __pmdp_csp(pmd_t *pmdp) 1619 { 1620 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1621 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1622 } 1623 1624 #define IDTE_GLOBAL 0 1625 #define IDTE_LOCAL 1 1626 1627 #define IDTE_PTOA 0x0800 1628 #define IDTE_NODAT 0x1000 1629 #define IDTE_GUEST_ASCE 0x2000 1630 1631 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1632 unsigned long opt, unsigned long asce, 1633 int local) 1634 { 1635 unsigned long sto; 1636 1637 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1638 if (__builtin_constant_p(opt) && opt == 0) { 1639 /* flush without guest asce */ 1640 asm volatile( 1641 " idte %[r1],0,%[r2],%[m4]" 1642 : "+m" (*pmdp) 1643 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1644 [m4] "i" (local) 1645 : "cc" ); 1646 } else { 1647 /* flush with guest asce */ 1648 asm volatile( 1649 " idte %[r1],%[r3],%[r2],%[m4]" 1650 : "+m" (*pmdp) 1651 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1652 [r3] "a" (asce), [m4] "i" (local) 1653 : "cc" ); 1654 } 1655 } 1656 1657 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1658 unsigned long opt, unsigned long asce, 1659 int local) 1660 { 1661 unsigned long r3o; 1662 1663 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1664 r3o |= _ASCE_TYPE_REGION3; 1665 if (__builtin_constant_p(opt) && opt == 0) { 1666 /* flush without guest asce */ 1667 asm volatile( 1668 " idte %[r1],0,%[r2],%[m4]" 1669 : "+m" (*pudp) 1670 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1671 [m4] "i" (local) 1672 : "cc"); 1673 } else { 1674 /* flush with guest asce */ 1675 asm volatile( 1676 " idte %[r1],%[r3],%[r2],%[m4]" 1677 : "+m" (*pudp) 1678 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1679 [r3] "a" (asce), [m4] "i" (local) 1680 : "cc" ); 1681 } 1682 } 1683 1684 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1685 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1686 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1687 1688 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1689 1690 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1691 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1692 pgtable_t pgtable); 1693 1694 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1695 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1696 1697 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1698 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1699 unsigned long addr, pmd_t *pmdp, 1700 pmd_t entry, int dirty) 1701 { 1702 VM_BUG_ON(addr & ~HPAGE_MASK); 1703 1704 entry = pmd_mkyoung(entry); 1705 if (dirty) 1706 entry = pmd_mkdirty(entry); 1707 if (pmd_val(*pmdp) == pmd_val(entry)) 1708 return 0; 1709 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1710 return 1; 1711 } 1712 1713 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1714 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1715 unsigned long addr, pmd_t *pmdp) 1716 { 1717 pmd_t pmd = *pmdp; 1718 1719 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1720 return pmd_young(pmd); 1721 } 1722 1723 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1724 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1725 unsigned long addr, pmd_t *pmdp) 1726 { 1727 VM_BUG_ON(addr & ~HPAGE_MASK); 1728 return pmdp_test_and_clear_young(vma, addr, pmdp); 1729 } 1730 1731 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1732 pmd_t *pmdp, pmd_t entry) 1733 { 1734 if (!MACHINE_HAS_NX) 1735 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1736 set_pmd(pmdp, entry); 1737 } 1738 1739 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1740 { 1741 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1742 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1743 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1744 } 1745 1746 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1747 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1748 unsigned long addr, pmd_t *pmdp) 1749 { 1750 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1751 } 1752 1753 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1754 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1755 unsigned long addr, 1756 pmd_t *pmdp, int full) 1757 { 1758 if (full) { 1759 pmd_t pmd = *pmdp; 1760 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1761 return pmd; 1762 } 1763 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1764 } 1765 1766 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1767 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1768 unsigned long addr, pmd_t *pmdp) 1769 { 1770 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1771 } 1772 1773 #define __HAVE_ARCH_PMDP_INVALIDATE 1774 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1775 unsigned long addr, pmd_t *pmdp) 1776 { 1777 pmd_t pmd; 1778 1779 VM_WARN_ON_ONCE(!pmd_present(*pmdp)); 1780 pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1781 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1782 } 1783 1784 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1785 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1786 unsigned long addr, pmd_t *pmdp) 1787 { 1788 pmd_t pmd = *pmdp; 1789 1790 if (pmd_write(pmd)) 1791 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1792 } 1793 1794 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1795 unsigned long address, 1796 pmd_t *pmdp) 1797 { 1798 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1799 } 1800 #define pmdp_collapse_flush pmdp_collapse_flush 1801 1802 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1803 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1804 1805 static inline int pmd_trans_huge(pmd_t pmd) 1806 { 1807 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1808 } 1809 1810 #define has_transparent_hugepage has_transparent_hugepage 1811 static inline int has_transparent_hugepage(void) 1812 { 1813 return MACHINE_HAS_EDAT1 ? 1 : 0; 1814 } 1815 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1816 1817 /* 1818 * 64 bit swap entry format: 1819 * A page-table entry has some bits we have to treat in a special way. 1820 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1821 * as invalid. 1822 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1823 * | offset |E11XX|type |S0| 1824 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1825 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1826 * 1827 * Bits 0-51 store the offset. 1828 * Bit 52 (E) is used to remember PG_anon_exclusive. 1829 * Bits 57-61 store the type. 1830 * Bit 62 (S) is used for softdirty tracking. 1831 * Bits 55 and 56 (X) are unused. 1832 */ 1833 1834 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1835 #define __SWP_OFFSET_SHIFT 12 1836 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1837 #define __SWP_TYPE_SHIFT 2 1838 1839 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1840 { 1841 unsigned long pteval; 1842 1843 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1844 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1845 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1846 return __pte(pteval); 1847 } 1848 1849 static inline unsigned long __swp_type(swp_entry_t entry) 1850 { 1851 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1852 } 1853 1854 static inline unsigned long __swp_offset(swp_entry_t entry) 1855 { 1856 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1857 } 1858 1859 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1860 { 1861 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1862 } 1863 1864 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1865 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1866 1867 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1868 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1869 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1870 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1871 extern void vmem_unmap_4k_page(unsigned long addr); 1872 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1873 extern int s390_enable_sie(void); 1874 extern int s390_enable_skey(void); 1875 extern void s390_reset_cmma(struct mm_struct *mm); 1876 1877 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1878 #define HAVE_ARCH_UNMAPPED_AREA 1879 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1880 1881 #define pmd_pgtable(pmd) \ 1882 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1883 1884 #endif /* _S390_PAGE_H */ 1885