1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/bug.h> 21 #include <asm/page.h> 22 #include <asm/uv.h> 23 24 extern pgd_t swapper_pg_dir[]; 25 extern void paging_init(void); 26 extern unsigned long s390_invalid_asce; 27 28 enum { 29 PG_DIRECT_MAP_4K = 0, 30 PG_DIRECT_MAP_1M, 31 PG_DIRECT_MAP_2G, 32 PG_DIRECT_MAP_MAX 33 }; 34 35 extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; 36 37 static inline void update_page_count(int level, long count) 38 { 39 if (IS_ENABLED(CONFIG_PROC_FS)) 40 atomic_long_add(count, &direct_pages_count[level]); 41 } 42 43 struct seq_file; 44 void arch_report_meminfo(struct seq_file *m); 45 46 /* 47 * The S390 doesn't have any external MMU info: the kernel page 48 * tables contain all the necessary information. 49 */ 50 #define update_mmu_cache(vma, address, ptep) do { } while (0) 51 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 52 53 /* 54 * ZERO_PAGE is a global shared page that is always zero; used 55 * for zero-mapped memory areas etc.. 56 */ 57 58 extern unsigned long empty_zero_page; 59 extern unsigned long zero_page_mask; 60 61 #define ZERO_PAGE(vaddr) \ 62 (virt_to_page((void *)(empty_zero_page + \ 63 (((unsigned long)(vaddr)) &zero_page_mask)))) 64 #define __HAVE_COLOR_ZERO_PAGE 65 66 /* TODO: s390 cannot support io_remap_pfn_range... */ 67 68 #define pte_ERROR(e) \ 69 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 70 #define pmd_ERROR(e) \ 71 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 72 #define pud_ERROR(e) \ 73 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 74 #define p4d_ERROR(e) \ 75 printk("%s:%d: bad p4d %p.\n", __FILE__, __LINE__, (void *) p4d_val(e)) 76 #define pgd_ERROR(e) \ 77 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 78 79 /* 80 * The vmalloc and module area will always be on the topmost area of the 81 * kernel mapping. 512GB are reserved for vmalloc by default. 82 * At the top of the vmalloc area a 2GB area is reserved where modules 83 * will reside. That makes sure that inter module branches always 84 * happen without trampolines and in addition the placement within a 85 * 2GB frame is branch prediction unit friendly. 86 */ 87 extern unsigned long VMALLOC_START; 88 extern unsigned long VMALLOC_END; 89 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 90 extern struct page *vmemmap; 91 extern unsigned long vmemmap_size; 92 93 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 94 95 extern unsigned long MODULES_VADDR; 96 extern unsigned long MODULES_END; 97 #define MODULES_VADDR MODULES_VADDR 98 #define MODULES_END MODULES_END 99 #define MODULES_LEN (1UL << 31) 100 101 static inline int is_module_addr(void *addr) 102 { 103 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 104 if (addr < (void *)MODULES_VADDR) 105 return 0; 106 if (addr > (void *)MODULES_END) 107 return 0; 108 return 1; 109 } 110 111 /* 112 * A 64 bit pagetable entry of S390 has following format: 113 * | PFRA |0IPC| OS | 114 * 0000000000111111111122222222223333333333444444444455555555556666 115 * 0123456789012345678901234567890123456789012345678901234567890123 116 * 117 * I Page-Invalid Bit: Page is not available for address-translation 118 * P Page-Protection Bit: Store access not possible for page 119 * C Change-bit override: HW is not required to set change bit 120 * 121 * A 64 bit segmenttable entry of S390 has following format: 122 * | P-table origin | TT 123 * 0000000000111111111122222222223333333333444444444455555555556666 124 * 0123456789012345678901234567890123456789012345678901234567890123 125 * 126 * I Segment-Invalid Bit: Segment is not available for address-translation 127 * C Common-Segment Bit: Segment is not private (PoP 3-30) 128 * P Page-Protection Bit: Store access not possible for page 129 * TT Type 00 130 * 131 * A 64 bit region table entry of S390 has following format: 132 * | S-table origin | TF TTTL 133 * 0000000000111111111122222222223333333333444444444455555555556666 134 * 0123456789012345678901234567890123456789012345678901234567890123 135 * 136 * I Segment-Invalid Bit: Segment is not available for address-translation 137 * TT Type 01 138 * TF 139 * TL Table length 140 * 141 * The 64 bit regiontable origin of S390 has following format: 142 * | region table origon | DTTL 143 * 0000000000111111111122222222223333333333444444444455555555556666 144 * 0123456789012345678901234567890123456789012345678901234567890123 145 * 146 * X Space-Switch event: 147 * G Segment-Invalid Bit: 148 * P Private-Space Bit: 149 * S Storage-Alteration: 150 * R Real space 151 * TL Table-Length: 152 * 153 * A storage key has the following format: 154 * | ACC |F|R|C|0| 155 * 0 3 4 5 6 7 156 * ACC: access key 157 * F : fetch protection bit 158 * R : referenced bit 159 * C : changed bit 160 */ 161 162 /* Hardware bits in the page table entry */ 163 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 164 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 165 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 166 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 167 168 /* Software bits in the page table entry */ 169 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 170 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 171 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 172 #define _PAGE_READ 0x010 /* SW pte read bit */ 173 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 174 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 175 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 176 177 #ifdef CONFIG_MEM_SOFT_DIRTY 178 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 179 #else 180 #define _PAGE_SOFT_DIRTY 0x000 181 #endif 182 183 /* Set of bits not changed in pte_modify */ 184 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 185 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 186 187 /* 188 * handle_pte_fault uses pte_present and pte_none to find out the pte type 189 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 190 * distinguish present from not-present ptes. It is changed only with the page 191 * table lock held. 192 * 193 * The following table gives the different possible bit combinations for 194 * the pte hardware and software bits in the last 12 bits of a pte 195 * (. unassigned bit, x don't care, t swap type): 196 * 197 * 842100000000 198 * 000084210000 199 * 000000008421 200 * .IR.uswrdy.p 201 * empty .10.00000000 202 * swap .11..ttttt.0 203 * prot-none, clean, old .11.xx0000.1 204 * prot-none, clean, young .11.xx0001.1 205 * prot-none, dirty, old .11.xx0010.1 206 * prot-none, dirty, young .11.xx0011.1 207 * read-only, clean, old .11.xx0100.1 208 * read-only, clean, young .01.xx0101.1 209 * read-only, dirty, old .11.xx0110.1 210 * read-only, dirty, young .01.xx0111.1 211 * read-write, clean, old .11.xx1100.1 212 * read-write, clean, young .01.xx1101.1 213 * read-write, dirty, old .10.xx1110.1 214 * read-write, dirty, young .00.xx1111.1 215 * HW-bits: R read-only, I invalid 216 * SW-bits: p present, y young, d dirty, r read, w write, s special, 217 * u unused, l large 218 * 219 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 220 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 221 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 222 */ 223 224 /* Bits in the segment/region table address-space-control-element */ 225 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 226 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 227 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 228 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 229 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 230 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 231 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 232 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 233 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 234 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 235 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 236 237 /* Bits in the region table entry */ 238 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 239 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 240 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 241 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 242 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 243 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 244 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 245 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 246 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 247 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 248 249 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 250 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 251 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 252 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 253 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 254 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 255 256 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 257 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 258 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 259 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 260 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 261 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 262 263 #ifdef CONFIG_MEM_SOFT_DIRTY 264 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 265 #else 266 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 267 #endif 268 269 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 270 271 /* Bits in the segment table entry */ 272 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 273 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 274 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 275 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 276 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 277 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 278 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 279 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 280 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 281 282 #define _SEGMENT_ENTRY (0) 283 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 284 285 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 286 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 287 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 288 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 289 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 290 291 #ifdef CONFIG_MEM_SOFT_DIRTY 292 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 293 #else 294 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 295 #endif 296 297 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 298 #define _PAGE_ENTRIES 256 /* number of page table entries */ 299 300 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 301 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 302 303 #define _REGION1_SHIFT 53 304 #define _REGION2_SHIFT 42 305 #define _REGION3_SHIFT 31 306 #define _SEGMENT_SHIFT 20 307 308 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 309 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 310 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 311 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 312 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 313 314 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 315 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 316 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 317 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 318 319 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 320 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 321 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 322 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 323 324 #define PMD_SHIFT _SEGMENT_SHIFT 325 #define PUD_SHIFT _REGION3_SHIFT 326 #define P4D_SHIFT _REGION2_SHIFT 327 #define PGDIR_SHIFT _REGION1_SHIFT 328 329 #define PMD_SIZE _SEGMENT_SIZE 330 #define PUD_SIZE _REGION3_SIZE 331 #define P4D_SIZE _REGION2_SIZE 332 #define PGDIR_SIZE _REGION1_SIZE 333 334 #define PMD_MASK _SEGMENT_MASK 335 #define PUD_MASK _REGION3_MASK 336 #define P4D_MASK _REGION2_MASK 337 #define PGDIR_MASK _REGION1_MASK 338 339 #define PTRS_PER_PTE _PAGE_ENTRIES 340 #define PTRS_PER_PMD _CRST_ENTRIES 341 #define PTRS_PER_PUD _CRST_ENTRIES 342 #define PTRS_PER_P4D _CRST_ENTRIES 343 #define PTRS_PER_PGD _CRST_ENTRIES 344 345 /* 346 * Segment table and region3 table entry encoding 347 * (R = read-only, I = invalid, y = young bit): 348 * dy..R...I...wr 349 * prot-none, clean, old 00..1...1...00 350 * prot-none, clean, young 01..1...1...00 351 * prot-none, dirty, old 10..1...1...00 352 * prot-none, dirty, young 11..1...1...00 353 * read-only, clean, old 00..1...1...01 354 * read-only, clean, young 01..1...0...01 355 * read-only, dirty, old 10..1...1...01 356 * read-only, dirty, young 11..1...0...01 357 * read-write, clean, old 00..1...1...11 358 * read-write, clean, young 01..1...0...11 359 * read-write, dirty, old 10..0...1...11 360 * read-write, dirty, young 11..0...0...11 361 * The segment table origin is used to distinguish empty (origin==0) from 362 * read-write, old segment table entries (origin!=0) 363 * HW-bits: R read-only, I invalid 364 * SW-bits: y young, d dirty, r read, w write 365 */ 366 367 /* Page status table bits for virtualization */ 368 #define PGSTE_ACC_BITS 0xf000000000000000UL 369 #define PGSTE_FP_BIT 0x0800000000000000UL 370 #define PGSTE_PCL_BIT 0x0080000000000000UL 371 #define PGSTE_HR_BIT 0x0040000000000000UL 372 #define PGSTE_HC_BIT 0x0020000000000000UL 373 #define PGSTE_GR_BIT 0x0004000000000000UL 374 #define PGSTE_GC_BIT 0x0002000000000000UL 375 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 376 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 377 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 378 379 /* Guest Page State used for virtualization */ 380 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 381 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 382 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 383 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 384 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 385 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 386 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 387 388 /* 389 * A user page table pointer has the space-switch-event bit, the 390 * private-space-control bit and the storage-alteration-event-control 391 * bit set. A kernel page table pointer doesn't need them. 392 */ 393 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 394 _ASCE_ALT_EVENT) 395 396 /* 397 * Page protection definitions. 398 */ 399 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 400 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 401 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 402 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 403 _PAGE_INVALID | _PAGE_PROTECT) 404 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 405 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 406 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 407 _PAGE_INVALID | _PAGE_PROTECT) 408 409 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 410 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 411 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 412 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 413 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 414 _PAGE_PROTECT | _PAGE_NOEXEC) 415 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 416 _PAGE_YOUNG | _PAGE_DIRTY) 417 418 /* 419 * On s390 the page table entry has an invalid bit and a read-only bit. 420 * Read permission implies execute permission and write permission 421 * implies read permission. 422 */ 423 /*xwr*/ 424 #define __P000 PAGE_NONE 425 #define __P001 PAGE_RO 426 #define __P010 PAGE_RO 427 #define __P011 PAGE_RO 428 #define __P100 PAGE_RX 429 #define __P101 PAGE_RX 430 #define __P110 PAGE_RX 431 #define __P111 PAGE_RX 432 433 #define __S000 PAGE_NONE 434 #define __S001 PAGE_RO 435 #define __S010 PAGE_RW 436 #define __S011 PAGE_RW 437 #define __S100 PAGE_RX 438 #define __S101 PAGE_RX 439 #define __S110 PAGE_RWX 440 #define __S111 PAGE_RWX 441 442 /* 443 * Segment entry (large page) protection definitions. 444 */ 445 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 446 _SEGMENT_ENTRY_PROTECT) 447 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 448 _SEGMENT_ENTRY_READ | \ 449 _SEGMENT_ENTRY_NOEXEC) 450 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 451 _SEGMENT_ENTRY_READ) 452 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 453 _SEGMENT_ENTRY_WRITE | \ 454 _SEGMENT_ENTRY_NOEXEC) 455 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 456 _SEGMENT_ENTRY_WRITE) 457 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 458 _SEGMENT_ENTRY_LARGE | \ 459 _SEGMENT_ENTRY_READ | \ 460 _SEGMENT_ENTRY_WRITE | \ 461 _SEGMENT_ENTRY_YOUNG | \ 462 _SEGMENT_ENTRY_DIRTY | \ 463 _SEGMENT_ENTRY_NOEXEC) 464 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 465 _SEGMENT_ENTRY_LARGE | \ 466 _SEGMENT_ENTRY_READ | \ 467 _SEGMENT_ENTRY_YOUNG | \ 468 _SEGMENT_ENTRY_PROTECT | \ 469 _SEGMENT_ENTRY_NOEXEC) 470 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 471 _SEGMENT_ENTRY_LARGE | \ 472 _SEGMENT_ENTRY_READ | \ 473 _SEGMENT_ENTRY_WRITE | \ 474 _SEGMENT_ENTRY_YOUNG | \ 475 _SEGMENT_ENTRY_DIRTY) 476 477 /* 478 * Region3 entry (large page) protection definitions. 479 */ 480 481 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 482 _REGION3_ENTRY_LARGE | \ 483 _REGION3_ENTRY_READ | \ 484 _REGION3_ENTRY_WRITE | \ 485 _REGION3_ENTRY_YOUNG | \ 486 _REGION3_ENTRY_DIRTY | \ 487 _REGION_ENTRY_NOEXEC) 488 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 489 _REGION3_ENTRY_LARGE | \ 490 _REGION3_ENTRY_READ | \ 491 _REGION3_ENTRY_YOUNG | \ 492 _REGION_ENTRY_PROTECT | \ 493 _REGION_ENTRY_NOEXEC) 494 495 static inline bool mm_p4d_folded(struct mm_struct *mm) 496 { 497 return mm->context.asce_limit <= _REGION1_SIZE; 498 } 499 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 500 501 static inline bool mm_pud_folded(struct mm_struct *mm) 502 { 503 return mm->context.asce_limit <= _REGION2_SIZE; 504 } 505 #define mm_pud_folded(mm) mm_pud_folded(mm) 506 507 static inline bool mm_pmd_folded(struct mm_struct *mm) 508 { 509 return mm->context.asce_limit <= _REGION3_SIZE; 510 } 511 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 512 513 static inline int mm_has_pgste(struct mm_struct *mm) 514 { 515 #ifdef CONFIG_PGSTE 516 if (unlikely(mm->context.has_pgste)) 517 return 1; 518 #endif 519 return 0; 520 } 521 522 static inline int mm_is_protected(struct mm_struct *mm) 523 { 524 #ifdef CONFIG_PGSTE 525 if (unlikely(atomic_read(&mm->context.is_protected))) 526 return 1; 527 #endif 528 return 0; 529 } 530 531 static inline int mm_alloc_pgste(struct mm_struct *mm) 532 { 533 #ifdef CONFIG_PGSTE 534 if (unlikely(mm->context.alloc_pgste)) 535 return 1; 536 #endif 537 return 0; 538 } 539 540 /* 541 * In the case that a guest uses storage keys 542 * faults should no longer be backed by zero pages 543 */ 544 #define mm_forbids_zeropage mm_has_pgste 545 static inline int mm_uses_skeys(struct mm_struct *mm) 546 { 547 #ifdef CONFIG_PGSTE 548 if (mm->context.uses_skeys) 549 return 1; 550 #endif 551 return 0; 552 } 553 554 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 555 { 556 register unsigned long reg2 asm("2") = old; 557 register unsigned long reg3 asm("3") = new; 558 unsigned long address = (unsigned long)ptr | 1; 559 560 asm volatile( 561 " csp %0,%3" 562 : "+d" (reg2), "+m" (*ptr) 563 : "d" (reg3), "d" (address) 564 : "cc"); 565 } 566 567 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 568 { 569 register unsigned long reg2 asm("2") = old; 570 register unsigned long reg3 asm("3") = new; 571 unsigned long address = (unsigned long)ptr | 1; 572 573 asm volatile( 574 " .insn rre,0xb98a0000,%0,%3" 575 : "+d" (reg2), "+m" (*ptr) 576 : "d" (reg3), "d" (address) 577 : "cc"); 578 } 579 580 #define CRDTE_DTT_PAGE 0x00UL 581 #define CRDTE_DTT_SEGMENT 0x10UL 582 #define CRDTE_DTT_REGION3 0x14UL 583 #define CRDTE_DTT_REGION2 0x18UL 584 #define CRDTE_DTT_REGION1 0x1cUL 585 586 static inline void crdte(unsigned long old, unsigned long new, 587 unsigned long table, unsigned long dtt, 588 unsigned long address, unsigned long asce) 589 { 590 register unsigned long reg2 asm("2") = old; 591 register unsigned long reg3 asm("3") = new; 592 register unsigned long reg4 asm("4") = table | dtt; 593 register unsigned long reg5 asm("5") = address; 594 595 asm volatile(".insn rrf,0xb98f0000,%0,%2,%4,0" 596 : "+d" (reg2) 597 : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce) 598 : "memory", "cc"); 599 } 600 601 /* 602 * pgd/p4d/pud/pmd/pte query functions 603 */ 604 static inline int pgd_folded(pgd_t pgd) 605 { 606 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 607 } 608 609 static inline int pgd_present(pgd_t pgd) 610 { 611 if (pgd_folded(pgd)) 612 return 1; 613 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 614 } 615 616 static inline int pgd_none(pgd_t pgd) 617 { 618 if (pgd_folded(pgd)) 619 return 0; 620 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 621 } 622 623 static inline int pgd_bad(pgd_t pgd) 624 { 625 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 626 return 0; 627 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 628 } 629 630 static inline unsigned long pgd_pfn(pgd_t pgd) 631 { 632 unsigned long origin_mask; 633 634 origin_mask = _REGION_ENTRY_ORIGIN; 635 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 636 } 637 638 static inline int p4d_folded(p4d_t p4d) 639 { 640 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 641 } 642 643 static inline int p4d_present(p4d_t p4d) 644 { 645 if (p4d_folded(p4d)) 646 return 1; 647 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 648 } 649 650 static inline int p4d_none(p4d_t p4d) 651 { 652 if (p4d_folded(p4d)) 653 return 0; 654 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 655 } 656 657 static inline unsigned long p4d_pfn(p4d_t p4d) 658 { 659 unsigned long origin_mask; 660 661 origin_mask = _REGION_ENTRY_ORIGIN; 662 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 663 } 664 665 static inline int pud_folded(pud_t pud) 666 { 667 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 668 } 669 670 static inline int pud_present(pud_t pud) 671 { 672 if (pud_folded(pud)) 673 return 1; 674 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 675 } 676 677 static inline int pud_none(pud_t pud) 678 { 679 if (pud_folded(pud)) 680 return 0; 681 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 682 } 683 684 #define pud_leaf pud_large 685 static inline int pud_large(pud_t pud) 686 { 687 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 688 return 0; 689 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 690 } 691 692 #define pmd_leaf pmd_large 693 static inline int pmd_large(pmd_t pmd) 694 { 695 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 696 } 697 698 static inline int pmd_bad(pmd_t pmd) 699 { 700 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 701 return 1; 702 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 703 } 704 705 static inline int pud_bad(pud_t pud) 706 { 707 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 708 709 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud)) 710 return 1; 711 if (type < _REGION_ENTRY_TYPE_R3) 712 return 0; 713 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 714 } 715 716 static inline int p4d_bad(p4d_t p4d) 717 { 718 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 719 720 if (type > _REGION_ENTRY_TYPE_R2) 721 return 1; 722 if (type < _REGION_ENTRY_TYPE_R2) 723 return 0; 724 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 725 } 726 727 static inline int pmd_present(pmd_t pmd) 728 { 729 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 730 } 731 732 static inline int pmd_none(pmd_t pmd) 733 { 734 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 735 } 736 737 #define pmd_write pmd_write 738 static inline int pmd_write(pmd_t pmd) 739 { 740 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 741 } 742 743 #define pud_write pud_write 744 static inline int pud_write(pud_t pud) 745 { 746 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 747 } 748 749 static inline int pmd_dirty(pmd_t pmd) 750 { 751 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 752 } 753 754 static inline int pmd_young(pmd_t pmd) 755 { 756 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 757 } 758 759 static inline int pte_present(pte_t pte) 760 { 761 /* Bit pattern: (pte & 0x001) == 0x001 */ 762 return (pte_val(pte) & _PAGE_PRESENT) != 0; 763 } 764 765 static inline int pte_none(pte_t pte) 766 { 767 /* Bit pattern: pte == 0x400 */ 768 return pte_val(pte) == _PAGE_INVALID; 769 } 770 771 static inline int pte_swap(pte_t pte) 772 { 773 /* Bit pattern: (pte & 0x201) == 0x200 */ 774 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 775 == _PAGE_PROTECT; 776 } 777 778 static inline int pte_special(pte_t pte) 779 { 780 return (pte_val(pte) & _PAGE_SPECIAL); 781 } 782 783 #define __HAVE_ARCH_PTE_SAME 784 static inline int pte_same(pte_t a, pte_t b) 785 { 786 return pte_val(a) == pte_val(b); 787 } 788 789 #ifdef CONFIG_NUMA_BALANCING 790 static inline int pte_protnone(pte_t pte) 791 { 792 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 793 } 794 795 static inline int pmd_protnone(pmd_t pmd) 796 { 797 /* pmd_large(pmd) implies pmd_present(pmd) */ 798 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 799 } 800 #endif 801 802 static inline int pte_soft_dirty(pte_t pte) 803 { 804 return pte_val(pte) & _PAGE_SOFT_DIRTY; 805 } 806 #define pte_swp_soft_dirty pte_soft_dirty 807 808 static inline pte_t pte_mksoft_dirty(pte_t pte) 809 { 810 pte_val(pte) |= _PAGE_SOFT_DIRTY; 811 return pte; 812 } 813 #define pte_swp_mksoft_dirty pte_mksoft_dirty 814 815 static inline pte_t pte_clear_soft_dirty(pte_t pte) 816 { 817 pte_val(pte) &= ~_PAGE_SOFT_DIRTY; 818 return pte; 819 } 820 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 821 822 static inline int pmd_soft_dirty(pmd_t pmd) 823 { 824 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 825 } 826 827 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 828 { 829 pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; 830 return pmd; 831 } 832 833 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 834 { 835 pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; 836 return pmd; 837 } 838 839 /* 840 * query functions pte_write/pte_dirty/pte_young only work if 841 * pte_present() is true. Undefined behaviour if not.. 842 */ 843 static inline int pte_write(pte_t pte) 844 { 845 return (pte_val(pte) & _PAGE_WRITE) != 0; 846 } 847 848 static inline int pte_dirty(pte_t pte) 849 { 850 return (pte_val(pte) & _PAGE_DIRTY) != 0; 851 } 852 853 static inline int pte_young(pte_t pte) 854 { 855 return (pte_val(pte) & _PAGE_YOUNG) != 0; 856 } 857 858 #define __HAVE_ARCH_PTE_UNUSED 859 static inline int pte_unused(pte_t pte) 860 { 861 return pte_val(pte) & _PAGE_UNUSED; 862 } 863 864 /* 865 * pgd/pmd/pte modification functions 866 */ 867 868 static inline void pgd_clear(pgd_t *pgd) 869 { 870 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 871 pgd_val(*pgd) = _REGION1_ENTRY_EMPTY; 872 } 873 874 static inline void p4d_clear(p4d_t *p4d) 875 { 876 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 877 p4d_val(*p4d) = _REGION2_ENTRY_EMPTY; 878 } 879 880 static inline void pud_clear(pud_t *pud) 881 { 882 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 883 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 884 } 885 886 static inline void pmd_clear(pmd_t *pmdp) 887 { 888 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; 889 } 890 891 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 892 { 893 pte_val(*ptep) = _PAGE_INVALID; 894 } 895 896 /* 897 * The following pte modification functions only work if 898 * pte_present() is true. Undefined behaviour if not.. 899 */ 900 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 901 { 902 pte_val(pte) &= _PAGE_CHG_MASK; 903 pte_val(pte) |= pgprot_val(newprot); 904 /* 905 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 906 * has the invalid bit set, clear it again for readable, young pages 907 */ 908 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 909 pte_val(pte) &= ~_PAGE_INVALID; 910 /* 911 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 912 * protection bit set, clear it again for writable, dirty pages 913 */ 914 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 915 pte_val(pte) &= ~_PAGE_PROTECT; 916 return pte; 917 } 918 919 static inline pte_t pte_wrprotect(pte_t pte) 920 { 921 pte_val(pte) &= ~_PAGE_WRITE; 922 pte_val(pte) |= _PAGE_PROTECT; 923 return pte; 924 } 925 926 static inline pte_t pte_mkwrite(pte_t pte) 927 { 928 pte_val(pte) |= _PAGE_WRITE; 929 if (pte_val(pte) & _PAGE_DIRTY) 930 pte_val(pte) &= ~_PAGE_PROTECT; 931 return pte; 932 } 933 934 static inline pte_t pte_mkclean(pte_t pte) 935 { 936 pte_val(pte) &= ~_PAGE_DIRTY; 937 pte_val(pte) |= _PAGE_PROTECT; 938 return pte; 939 } 940 941 static inline pte_t pte_mkdirty(pte_t pte) 942 { 943 pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; 944 if (pte_val(pte) & _PAGE_WRITE) 945 pte_val(pte) &= ~_PAGE_PROTECT; 946 return pte; 947 } 948 949 static inline pte_t pte_mkold(pte_t pte) 950 { 951 pte_val(pte) &= ~_PAGE_YOUNG; 952 pte_val(pte) |= _PAGE_INVALID; 953 return pte; 954 } 955 956 static inline pte_t pte_mkyoung(pte_t pte) 957 { 958 pte_val(pte) |= _PAGE_YOUNG; 959 if (pte_val(pte) & _PAGE_READ) 960 pte_val(pte) &= ~_PAGE_INVALID; 961 return pte; 962 } 963 964 static inline pte_t pte_mkspecial(pte_t pte) 965 { 966 pte_val(pte) |= _PAGE_SPECIAL; 967 return pte; 968 } 969 970 #ifdef CONFIG_HUGETLB_PAGE 971 static inline pte_t pte_mkhuge(pte_t pte) 972 { 973 pte_val(pte) |= _PAGE_LARGE; 974 return pte; 975 } 976 #endif 977 978 #define IPTE_GLOBAL 0 979 #define IPTE_LOCAL 1 980 981 #define IPTE_NODAT 0x400 982 #define IPTE_GUEST_ASCE 0x800 983 984 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 985 unsigned long opt, unsigned long asce, 986 int local) 987 { 988 unsigned long pto = (unsigned long) ptep; 989 990 if (__builtin_constant_p(opt) && opt == 0) { 991 /* Invalidation + TLB flush for the pte */ 992 asm volatile( 993 " .insn rrf,0xb2210000,%[r1],%[r2],0,%[m4]" 994 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 995 [m4] "i" (local)); 996 return; 997 } 998 999 /* Invalidate ptes with options + TLB flush of the ptes */ 1000 opt = opt | (asce & _ASCE_ORIGIN); 1001 asm volatile( 1002 " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" 1003 : [r2] "+a" (address), [r3] "+a" (opt) 1004 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1005 } 1006 1007 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1008 pte_t *ptep, int local) 1009 { 1010 unsigned long pto = (unsigned long) ptep; 1011 1012 /* Invalidate a range of ptes + TLB flush of the ptes */ 1013 do { 1014 asm volatile( 1015 " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" 1016 : [r2] "+a" (address), [r3] "+a" (nr) 1017 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1018 } while (nr != 255); 1019 } 1020 1021 /* 1022 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1023 * both clear the TLB for the unmapped pte. The reason is that 1024 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1025 * to modify an active pte. The sequence is 1026 * 1) ptep_get_and_clear 1027 * 2) set_pte_at 1028 * 3) flush_tlb_range 1029 * On s390 the tlb needs to get flushed with the modification of the pte 1030 * if the pte is active. The only way how this can be implemented is to 1031 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1032 * is a nop. 1033 */ 1034 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1035 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1036 1037 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1038 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1039 unsigned long addr, pte_t *ptep) 1040 { 1041 pte_t pte = *ptep; 1042 1043 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1044 return pte_young(pte); 1045 } 1046 1047 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1048 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1049 unsigned long address, pte_t *ptep) 1050 { 1051 return ptep_test_and_clear_young(vma, address, ptep); 1052 } 1053 1054 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1055 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1056 unsigned long addr, pte_t *ptep) 1057 { 1058 pte_t res; 1059 1060 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1061 if (mm_is_protected(mm) && pte_present(res)) 1062 uv_convert_from_secure(pte_val(res) & PAGE_MASK); 1063 return res; 1064 } 1065 1066 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1067 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1068 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1069 pte_t *, pte_t, pte_t); 1070 1071 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1072 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1073 unsigned long addr, pte_t *ptep) 1074 { 1075 pte_t res; 1076 1077 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1078 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1079 uv_convert_from_secure(pte_val(res) & PAGE_MASK); 1080 return res; 1081 } 1082 1083 /* 1084 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1085 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1086 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1087 * cannot be accessed while the batched unmap is running. In this case 1088 * full==1 and a simple pte_clear is enough. See tlb.h. 1089 */ 1090 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1091 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1092 unsigned long addr, 1093 pte_t *ptep, int full) 1094 { 1095 pte_t res; 1096 1097 if (full) { 1098 res = *ptep; 1099 *ptep = __pte(_PAGE_INVALID); 1100 } else { 1101 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1102 } 1103 if (mm_is_protected(mm) && pte_present(res)) 1104 uv_convert_from_secure(pte_val(res) & PAGE_MASK); 1105 return res; 1106 } 1107 1108 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1109 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1110 unsigned long addr, pte_t *ptep) 1111 { 1112 pte_t pte = *ptep; 1113 1114 if (pte_write(pte)) 1115 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1116 } 1117 1118 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1119 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1120 unsigned long addr, pte_t *ptep, 1121 pte_t entry, int dirty) 1122 { 1123 if (pte_same(*ptep, entry)) 1124 return 0; 1125 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1126 return 1; 1127 } 1128 1129 /* 1130 * Additional functions to handle KVM guest page tables 1131 */ 1132 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1133 pte_t *ptep, pte_t entry); 1134 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1135 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1136 pte_t *ptep, unsigned long bits); 1137 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1138 pte_t *ptep, int prot, unsigned long bit); 1139 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1140 pte_t *ptep , int reset); 1141 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1142 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1143 pte_t *sptep, pte_t *tptep, pte_t pte); 1144 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1145 1146 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1147 pte_t *ptep); 1148 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1149 unsigned char key, bool nq); 1150 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1151 unsigned char key, unsigned char *oldkey, 1152 bool nq, bool mr, bool mc); 1153 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1154 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1155 unsigned char *key); 1156 1157 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1158 unsigned long bits, unsigned long value); 1159 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1160 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1161 unsigned long *oldpte, unsigned long *oldpgste); 1162 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1163 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1164 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1165 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1166 1167 #define pgprot_writecombine pgprot_writecombine 1168 pgprot_t pgprot_writecombine(pgprot_t prot); 1169 1170 #define pgprot_writethrough pgprot_writethrough 1171 pgprot_t pgprot_writethrough(pgprot_t prot); 1172 1173 /* 1174 * Certain architectures need to do special things when PTEs 1175 * within a page table are directly modified. Thus, the following 1176 * hook is made available. 1177 */ 1178 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 1179 pte_t *ptep, pte_t entry) 1180 { 1181 if (pte_present(entry)) 1182 pte_val(entry) &= ~_PAGE_UNUSED; 1183 if (mm_has_pgste(mm)) 1184 ptep_set_pte_at(mm, addr, ptep, entry); 1185 else 1186 *ptep = entry; 1187 } 1188 1189 /* 1190 * Conversion functions: convert a page and protection to a page entry, 1191 * and a page entry and page directory to the page they refer to. 1192 */ 1193 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1194 { 1195 pte_t __pte; 1196 1197 pte_val(__pte) = physpage | pgprot_val(pgprot); 1198 if (!MACHINE_HAS_NX) 1199 pte_val(__pte) &= ~_PAGE_NOEXEC; 1200 return pte_mkyoung(__pte); 1201 } 1202 1203 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1204 { 1205 unsigned long physpage = page_to_phys(page); 1206 pte_t __pte = mk_pte_phys(physpage, pgprot); 1207 1208 if (pte_write(__pte) && PageDirty(page)) 1209 __pte = pte_mkdirty(__pte); 1210 return __pte; 1211 } 1212 1213 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1214 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1215 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1216 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1217 1218 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1219 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1220 1221 static inline unsigned long pmd_deref(pmd_t pmd) 1222 { 1223 unsigned long origin_mask; 1224 1225 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1226 if (pmd_large(pmd)) 1227 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1228 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1229 } 1230 1231 static inline unsigned long pmd_pfn(pmd_t pmd) 1232 { 1233 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1234 } 1235 1236 static inline unsigned long pud_deref(pud_t pud) 1237 { 1238 unsigned long origin_mask; 1239 1240 origin_mask = _REGION_ENTRY_ORIGIN; 1241 if (pud_large(pud)) 1242 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1243 return (unsigned long)__va(pud_val(pud) & origin_mask); 1244 } 1245 1246 static inline unsigned long pud_pfn(pud_t pud) 1247 { 1248 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1249 } 1250 1251 /* 1252 * The pgd_offset function *always* adds the index for the top-level 1253 * region/segment table. This is done to get a sequence like the 1254 * following to work: 1255 * pgdp = pgd_offset(current->mm, addr); 1256 * pgd = READ_ONCE(*pgdp); 1257 * p4dp = p4d_offset(&pgd, addr); 1258 * ... 1259 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1260 * only add an index if they dereferenced the pointer. 1261 */ 1262 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1263 { 1264 unsigned long rste; 1265 unsigned int shift; 1266 1267 /* Get the first entry of the top level table */ 1268 rste = pgd_val(*pgd); 1269 /* Pick up the shift from the table type of the first entry */ 1270 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1271 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1272 } 1273 1274 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1275 1276 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1277 { 1278 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1279 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1280 return (p4d_t *) pgdp; 1281 } 1282 #define p4d_offset_lockless p4d_offset_lockless 1283 1284 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1285 { 1286 return p4d_offset_lockless(pgdp, *pgdp, address); 1287 } 1288 1289 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1290 { 1291 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1292 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1293 return (pud_t *) p4dp; 1294 } 1295 #define pud_offset_lockless pud_offset_lockless 1296 1297 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1298 { 1299 return pud_offset_lockless(p4dp, *p4dp, address); 1300 } 1301 #define pud_offset pud_offset 1302 1303 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1304 { 1305 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1306 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1307 return (pmd_t *) pudp; 1308 } 1309 #define pmd_offset_lockless pmd_offset_lockless 1310 1311 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1312 { 1313 return pmd_offset_lockless(pudp, *pudp, address); 1314 } 1315 #define pmd_offset pmd_offset 1316 1317 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1318 { 1319 return (unsigned long) pmd_deref(pmd); 1320 } 1321 1322 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1323 { 1324 return end <= current->mm->context.asce_limit; 1325 } 1326 #define gup_fast_permitted gup_fast_permitted 1327 1328 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1329 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1330 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1331 1332 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1333 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1334 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1335 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1336 1337 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1338 { 1339 pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; 1340 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1341 return pmd; 1342 } 1343 1344 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1345 { 1346 pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; 1347 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1348 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1349 return pmd; 1350 } 1351 1352 static inline pmd_t pmd_mkclean(pmd_t pmd) 1353 { 1354 pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; 1355 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1356 return pmd; 1357 } 1358 1359 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1360 { 1361 pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY; 1362 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1363 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1364 return pmd; 1365 } 1366 1367 static inline pud_t pud_wrprotect(pud_t pud) 1368 { 1369 pud_val(pud) &= ~_REGION3_ENTRY_WRITE; 1370 pud_val(pud) |= _REGION_ENTRY_PROTECT; 1371 return pud; 1372 } 1373 1374 static inline pud_t pud_mkwrite(pud_t pud) 1375 { 1376 pud_val(pud) |= _REGION3_ENTRY_WRITE; 1377 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1378 pud_val(pud) &= ~_REGION_ENTRY_PROTECT; 1379 return pud; 1380 } 1381 1382 static inline pud_t pud_mkclean(pud_t pud) 1383 { 1384 pud_val(pud) &= ~_REGION3_ENTRY_DIRTY; 1385 pud_val(pud) |= _REGION_ENTRY_PROTECT; 1386 return pud; 1387 } 1388 1389 static inline pud_t pud_mkdirty(pud_t pud) 1390 { 1391 pud_val(pud) |= _REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY; 1392 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1393 pud_val(pud) &= ~_REGION_ENTRY_PROTECT; 1394 return pud; 1395 } 1396 1397 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1398 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1399 { 1400 /* 1401 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1402 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1403 */ 1404 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1405 return pgprot_val(SEGMENT_NONE); 1406 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1407 return pgprot_val(SEGMENT_RO); 1408 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1409 return pgprot_val(SEGMENT_RX); 1410 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1411 return pgprot_val(SEGMENT_RW); 1412 return pgprot_val(SEGMENT_RWX); 1413 } 1414 1415 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1416 { 1417 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1418 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1419 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; 1420 return pmd; 1421 } 1422 1423 static inline pmd_t pmd_mkold(pmd_t pmd) 1424 { 1425 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; 1426 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1427 return pmd; 1428 } 1429 1430 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1431 { 1432 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | 1433 _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | 1434 _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SOFT_DIRTY; 1435 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1436 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1437 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1438 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1439 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1440 return pmd; 1441 } 1442 1443 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1444 { 1445 pmd_t __pmd; 1446 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1447 return __pmd; 1448 } 1449 1450 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1451 1452 static inline void __pmdp_csp(pmd_t *pmdp) 1453 { 1454 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1455 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1456 } 1457 1458 #define IDTE_GLOBAL 0 1459 #define IDTE_LOCAL 1 1460 1461 #define IDTE_PTOA 0x0800 1462 #define IDTE_NODAT 0x1000 1463 #define IDTE_GUEST_ASCE 0x2000 1464 1465 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1466 unsigned long opt, unsigned long asce, 1467 int local) 1468 { 1469 unsigned long sto; 1470 1471 sto = (unsigned long) pmdp - pmd_index(addr) * sizeof(pmd_t); 1472 if (__builtin_constant_p(opt) && opt == 0) { 1473 /* flush without guest asce */ 1474 asm volatile( 1475 " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" 1476 : "+m" (*pmdp) 1477 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1478 [m4] "i" (local) 1479 : "cc" ); 1480 } else { 1481 /* flush with guest asce */ 1482 asm volatile( 1483 " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" 1484 : "+m" (*pmdp) 1485 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1486 [r3] "a" (asce), [m4] "i" (local) 1487 : "cc" ); 1488 } 1489 } 1490 1491 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1492 unsigned long opt, unsigned long asce, 1493 int local) 1494 { 1495 unsigned long r3o; 1496 1497 r3o = (unsigned long) pudp - pud_index(addr) * sizeof(pud_t); 1498 r3o |= _ASCE_TYPE_REGION3; 1499 if (__builtin_constant_p(opt) && opt == 0) { 1500 /* flush without guest asce */ 1501 asm volatile( 1502 " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" 1503 : "+m" (*pudp) 1504 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1505 [m4] "i" (local) 1506 : "cc"); 1507 } else { 1508 /* flush with guest asce */ 1509 asm volatile( 1510 " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" 1511 : "+m" (*pudp) 1512 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1513 [r3] "a" (asce), [m4] "i" (local) 1514 : "cc" ); 1515 } 1516 } 1517 1518 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1519 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1520 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1521 1522 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1523 1524 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1525 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1526 pgtable_t pgtable); 1527 1528 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1529 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1530 1531 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1532 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1533 unsigned long addr, pmd_t *pmdp, 1534 pmd_t entry, int dirty) 1535 { 1536 VM_BUG_ON(addr & ~HPAGE_MASK); 1537 1538 entry = pmd_mkyoung(entry); 1539 if (dirty) 1540 entry = pmd_mkdirty(entry); 1541 if (pmd_val(*pmdp) == pmd_val(entry)) 1542 return 0; 1543 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1544 return 1; 1545 } 1546 1547 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1548 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1549 unsigned long addr, pmd_t *pmdp) 1550 { 1551 pmd_t pmd = *pmdp; 1552 1553 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1554 return pmd_young(pmd); 1555 } 1556 1557 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1558 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1559 unsigned long addr, pmd_t *pmdp) 1560 { 1561 VM_BUG_ON(addr & ~HPAGE_MASK); 1562 return pmdp_test_and_clear_young(vma, addr, pmdp); 1563 } 1564 1565 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1566 pmd_t *pmdp, pmd_t entry) 1567 { 1568 if (!MACHINE_HAS_NX) 1569 pmd_val(entry) &= ~_SEGMENT_ENTRY_NOEXEC; 1570 *pmdp = entry; 1571 } 1572 1573 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1574 { 1575 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1576 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1577 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1578 return pmd; 1579 } 1580 1581 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1582 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1583 unsigned long addr, pmd_t *pmdp) 1584 { 1585 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1586 } 1587 1588 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1589 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1590 unsigned long addr, 1591 pmd_t *pmdp, int full) 1592 { 1593 if (full) { 1594 pmd_t pmd = *pmdp; 1595 *pmdp = __pmd(_SEGMENT_ENTRY_EMPTY); 1596 return pmd; 1597 } 1598 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1599 } 1600 1601 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1602 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1603 unsigned long addr, pmd_t *pmdp) 1604 { 1605 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1606 } 1607 1608 #define __HAVE_ARCH_PMDP_INVALIDATE 1609 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1610 unsigned long addr, pmd_t *pmdp) 1611 { 1612 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1613 1614 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1615 } 1616 1617 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1618 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1619 unsigned long addr, pmd_t *pmdp) 1620 { 1621 pmd_t pmd = *pmdp; 1622 1623 if (pmd_write(pmd)) 1624 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1625 } 1626 1627 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1628 unsigned long address, 1629 pmd_t *pmdp) 1630 { 1631 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1632 } 1633 #define pmdp_collapse_flush pmdp_collapse_flush 1634 1635 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1636 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1637 1638 static inline int pmd_trans_huge(pmd_t pmd) 1639 { 1640 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1641 } 1642 1643 #define has_transparent_hugepage has_transparent_hugepage 1644 static inline int has_transparent_hugepage(void) 1645 { 1646 return MACHINE_HAS_EDAT1 ? 1 : 0; 1647 } 1648 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1649 1650 /* 1651 * 64 bit swap entry format: 1652 * A page-table entry has some bits we have to treat in a special way. 1653 * Bits 52 and bit 55 have to be zero, otherwise a specification 1654 * exception will occur instead of a page translation exception. The 1655 * specification exception has the bad habit not to store necessary 1656 * information in the lowcore. 1657 * Bits 54 and 63 are used to indicate the page type. 1658 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1659 * This leaves the bits 0-51 and bits 56-62 to store type and offset. 1660 * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 1661 * for the offset. 1662 * | offset |01100|type |00| 1663 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1664 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1665 */ 1666 1667 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1668 #define __SWP_OFFSET_SHIFT 12 1669 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1670 #define __SWP_TYPE_SHIFT 2 1671 1672 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1673 { 1674 pte_t pte; 1675 1676 pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; 1677 pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1678 pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1679 return pte; 1680 } 1681 1682 static inline unsigned long __swp_type(swp_entry_t entry) 1683 { 1684 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1685 } 1686 1687 static inline unsigned long __swp_offset(swp_entry_t entry) 1688 { 1689 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1690 } 1691 1692 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1693 { 1694 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1695 } 1696 1697 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1698 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1699 1700 #define kern_addr_valid(addr) (1) 1701 1702 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1703 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1704 extern int s390_enable_sie(void); 1705 extern int s390_enable_skey(void); 1706 extern void s390_reset_cmma(struct mm_struct *mm); 1707 1708 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1709 #define HAVE_ARCH_UNMAPPED_AREA 1710 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1711 1712 #define pmd_pgtable(pmd) \ 1713 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1714 1715 #endif /* _S390_PAGE_H */ 1716