1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/bug.h> 22 #include <asm/page.h> 23 #include <asm/uv.h> 24 25 extern pgd_t swapper_pg_dir[]; 26 extern pgd_t invalid_pg_dir[]; 27 extern void paging_init(void); 28 extern unsigned long s390_invalid_asce; 29 30 enum { 31 PG_DIRECT_MAP_4K = 0, 32 PG_DIRECT_MAP_1M, 33 PG_DIRECT_MAP_2G, 34 PG_DIRECT_MAP_MAX 35 }; 36 37 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 38 39 static inline void update_page_count(int level, long count) 40 { 41 if (IS_ENABLED(CONFIG_PROC_FS)) 42 atomic_long_add(count, &direct_pages_count[level]); 43 } 44 45 /* 46 * The S390 doesn't have any external MMU info: the kernel page 47 * tables contain all the necessary information. 48 */ 49 #define update_mmu_cache(vma, address, ptep) do { } while (0) 50 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 51 52 /* 53 * ZERO_PAGE is a global shared page that is always zero; used 54 * for zero-mapped memory areas etc.. 55 */ 56 57 extern unsigned long empty_zero_page; 58 extern unsigned long zero_page_mask; 59 60 #define ZERO_PAGE(vaddr) \ 61 (virt_to_page((void *)(empty_zero_page + \ 62 (((unsigned long)(vaddr)) &zero_page_mask)))) 63 #define __HAVE_COLOR_ZERO_PAGE 64 65 /* TODO: s390 cannot support io_remap_pfn_range... */ 66 67 #define pte_ERROR(e) \ 68 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 69 #define pmd_ERROR(e) \ 70 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 71 #define pud_ERROR(e) \ 72 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 73 #define p4d_ERROR(e) \ 74 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 75 #define pgd_ERROR(e) \ 76 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 77 78 /* 79 * The vmalloc and module area will always be on the topmost area of the 80 * kernel mapping. 512GB are reserved for vmalloc by default. 81 * At the top of the vmalloc area a 2GB area is reserved where modules 82 * will reside. That makes sure that inter module branches always 83 * happen without trampolines and in addition the placement within a 84 * 2GB frame is branch prediction unit friendly. 85 */ 86 extern unsigned long __bootdata_preserved(VMALLOC_START); 87 extern unsigned long __bootdata_preserved(VMALLOC_END); 88 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 89 extern struct page *__bootdata_preserved(vmemmap); 90 extern unsigned long __bootdata_preserved(vmemmap_size); 91 92 extern unsigned long __bootdata_preserved(MODULES_VADDR); 93 extern unsigned long __bootdata_preserved(MODULES_END); 94 #define MODULES_VADDR MODULES_VADDR 95 #define MODULES_END MODULES_END 96 #define MODULES_LEN (1UL << 31) 97 98 static inline int is_module_addr(void *addr) 99 { 100 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 101 if (addr < (void *)MODULES_VADDR) 102 return 0; 103 if (addr > (void *)MODULES_END) 104 return 0; 105 return 1; 106 } 107 108 /* 109 * A 64 bit pagetable entry of S390 has following format: 110 * | PFRA |0IPC| OS | 111 * 0000000000111111111122222222223333333333444444444455555555556666 112 * 0123456789012345678901234567890123456789012345678901234567890123 113 * 114 * I Page-Invalid Bit: Page is not available for address-translation 115 * P Page-Protection Bit: Store access not possible for page 116 * C Change-bit override: HW is not required to set change bit 117 * 118 * A 64 bit segmenttable entry of S390 has following format: 119 * | P-table origin | TT 120 * 0000000000111111111122222222223333333333444444444455555555556666 121 * 0123456789012345678901234567890123456789012345678901234567890123 122 * 123 * I Segment-Invalid Bit: Segment is not available for address-translation 124 * C Common-Segment Bit: Segment is not private (PoP 3-30) 125 * P Page-Protection Bit: Store access not possible for page 126 * TT Type 00 127 * 128 * A 64 bit region table entry of S390 has following format: 129 * | S-table origin | TF TTTL 130 * 0000000000111111111122222222223333333333444444444455555555556666 131 * 0123456789012345678901234567890123456789012345678901234567890123 132 * 133 * I Segment-Invalid Bit: Segment is not available for address-translation 134 * TT Type 01 135 * TF 136 * TL Table length 137 * 138 * The 64 bit regiontable origin of S390 has following format: 139 * | region table origon | DTTL 140 * 0000000000111111111122222222223333333333444444444455555555556666 141 * 0123456789012345678901234567890123456789012345678901234567890123 142 * 143 * X Space-Switch event: 144 * G Segment-Invalid Bit: 145 * P Private-Space Bit: 146 * S Storage-Alteration: 147 * R Real space 148 * TL Table-Length: 149 * 150 * A storage key has the following format: 151 * | ACC |F|R|C|0| 152 * 0 3 4 5 6 7 153 * ACC: access key 154 * F : fetch protection bit 155 * R : referenced bit 156 * C : changed bit 157 */ 158 159 /* Hardware bits in the page table entry */ 160 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 161 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 162 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 163 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 164 165 /* Software bits in the page table entry */ 166 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 167 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 168 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 169 #define _PAGE_READ 0x010 /* SW pte read bit */ 170 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 171 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 172 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 173 174 #ifdef CONFIG_MEM_SOFT_DIRTY 175 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 176 #else 177 #define _PAGE_SOFT_DIRTY 0x000 178 #endif 179 180 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 181 182 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 183 184 /* Set of bits not changed in pte_modify */ 185 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 186 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 187 188 /* 189 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 190 * HW bit and all SW bits. 191 */ 192 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 193 194 /* 195 * handle_pte_fault uses pte_present and pte_none to find out the pte type 196 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 197 * distinguish present from not-present ptes. It is changed only with the page 198 * table lock held. 199 * 200 * The following table gives the different possible bit combinations for 201 * the pte hardware and software bits in the last 12 bits of a pte 202 * (. unassigned bit, x don't care, t swap type): 203 * 204 * 842100000000 205 * 000084210000 206 * 000000008421 207 * .IR.uswrdy.p 208 * empty .10.00000000 209 * swap .11..ttttt.0 210 * prot-none, clean, old .11.xx0000.1 211 * prot-none, clean, young .11.xx0001.1 212 * prot-none, dirty, old .11.xx0010.1 213 * prot-none, dirty, young .11.xx0011.1 214 * read-only, clean, old .11.xx0100.1 215 * read-only, clean, young .01.xx0101.1 216 * read-only, dirty, old .11.xx0110.1 217 * read-only, dirty, young .01.xx0111.1 218 * read-write, clean, old .11.xx1100.1 219 * read-write, clean, young .01.xx1101.1 220 * read-write, dirty, old .10.xx1110.1 221 * read-write, dirty, young .00.xx1111.1 222 * HW-bits: R read-only, I invalid 223 * SW-bits: p present, y young, d dirty, r read, w write, s special, 224 * u unused, l large 225 * 226 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 227 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 228 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 229 */ 230 231 /* Bits in the segment/region table address-space-control-element */ 232 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 233 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 234 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 235 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 236 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 237 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 238 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 239 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 240 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 241 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 242 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 243 244 /* Bits in the region table entry */ 245 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 246 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 247 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 248 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 249 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 250 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 251 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 252 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 253 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 254 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 255 256 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 257 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 258 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 259 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 260 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 261 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 262 263 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 264 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 265 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 266 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 267 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 268 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 269 270 #ifdef CONFIG_MEM_SOFT_DIRTY 271 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 272 #else 273 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 274 #endif 275 276 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 277 278 /* Bits in the segment table entry */ 279 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 280 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 281 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 282 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 283 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 284 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 285 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 286 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 287 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 288 289 #define _SEGMENT_ENTRY (0) 290 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 291 292 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 293 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 294 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 295 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 296 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 297 298 #ifdef CONFIG_MEM_SOFT_DIRTY 299 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 300 #else 301 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 302 #endif 303 304 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 305 #define _PAGE_ENTRIES 256 /* number of page table entries */ 306 307 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 308 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 309 310 #define _REGION1_SHIFT 53 311 #define _REGION2_SHIFT 42 312 #define _REGION3_SHIFT 31 313 #define _SEGMENT_SHIFT 20 314 315 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 316 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 317 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 318 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 319 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 320 321 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 322 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 323 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 324 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 325 326 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 327 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 328 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 329 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 330 331 #define PMD_SHIFT _SEGMENT_SHIFT 332 #define PUD_SHIFT _REGION3_SHIFT 333 #define P4D_SHIFT _REGION2_SHIFT 334 #define PGDIR_SHIFT _REGION1_SHIFT 335 336 #define PMD_SIZE _SEGMENT_SIZE 337 #define PUD_SIZE _REGION3_SIZE 338 #define P4D_SIZE _REGION2_SIZE 339 #define PGDIR_SIZE _REGION1_SIZE 340 341 #define PMD_MASK _SEGMENT_MASK 342 #define PUD_MASK _REGION3_MASK 343 #define P4D_MASK _REGION2_MASK 344 #define PGDIR_MASK _REGION1_MASK 345 346 #define PTRS_PER_PTE _PAGE_ENTRIES 347 #define PTRS_PER_PMD _CRST_ENTRIES 348 #define PTRS_PER_PUD _CRST_ENTRIES 349 #define PTRS_PER_P4D _CRST_ENTRIES 350 #define PTRS_PER_PGD _CRST_ENTRIES 351 352 /* 353 * Segment table and region3 table entry encoding 354 * (R = read-only, I = invalid, y = young bit): 355 * dy..R...I...wr 356 * prot-none, clean, old 00..1...1...00 357 * prot-none, clean, young 01..1...1...00 358 * prot-none, dirty, old 10..1...1...00 359 * prot-none, dirty, young 11..1...1...00 360 * read-only, clean, old 00..1...1...01 361 * read-only, clean, young 01..1...0...01 362 * read-only, dirty, old 10..1...1...01 363 * read-only, dirty, young 11..1...0...01 364 * read-write, clean, old 00..1...1...11 365 * read-write, clean, young 01..1...0...11 366 * read-write, dirty, old 10..0...1...11 367 * read-write, dirty, young 11..0...0...11 368 * The segment table origin is used to distinguish empty (origin==0) from 369 * read-write, old segment table entries (origin!=0) 370 * HW-bits: R read-only, I invalid 371 * SW-bits: y young, d dirty, r read, w write 372 */ 373 374 /* Page status table bits for virtualization */ 375 #define PGSTE_ACC_BITS 0xf000000000000000UL 376 #define PGSTE_FP_BIT 0x0800000000000000UL 377 #define PGSTE_PCL_BIT 0x0080000000000000UL 378 #define PGSTE_HR_BIT 0x0040000000000000UL 379 #define PGSTE_HC_BIT 0x0020000000000000UL 380 #define PGSTE_GR_BIT 0x0004000000000000UL 381 #define PGSTE_GC_BIT 0x0002000000000000UL 382 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 383 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 384 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 385 386 /* Guest Page State used for virtualization */ 387 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 388 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 389 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 390 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 391 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 392 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 393 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 394 395 /* 396 * A user page table pointer has the space-switch-event bit, the 397 * private-space-control bit and the storage-alteration-event-control 398 * bit set. A kernel page table pointer doesn't need them. 399 */ 400 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 401 _ASCE_ALT_EVENT) 402 403 /* 404 * Page protection definitions. 405 */ 406 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 407 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 408 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 409 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 410 _PAGE_INVALID | _PAGE_PROTECT) 411 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 412 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 413 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 414 _PAGE_INVALID | _PAGE_PROTECT) 415 416 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 417 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 418 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 419 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 420 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 421 _PAGE_PROTECT | _PAGE_NOEXEC) 422 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 423 _PAGE_YOUNG | _PAGE_DIRTY) 424 425 /* 426 * On s390 the page table entry has an invalid bit and a read-only bit. 427 * Read permission implies execute permission and write permission 428 * implies read permission. 429 */ 430 /*xwr*/ 431 432 /* 433 * Segment entry (large page) protection definitions. 434 */ 435 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 436 _SEGMENT_ENTRY_PROTECT) 437 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 438 _SEGMENT_ENTRY_READ | \ 439 _SEGMENT_ENTRY_NOEXEC) 440 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 441 _SEGMENT_ENTRY_READ) 442 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 443 _SEGMENT_ENTRY_WRITE | \ 444 _SEGMENT_ENTRY_NOEXEC) 445 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 446 _SEGMENT_ENTRY_WRITE) 447 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 448 _SEGMENT_ENTRY_LARGE | \ 449 _SEGMENT_ENTRY_READ | \ 450 _SEGMENT_ENTRY_WRITE | \ 451 _SEGMENT_ENTRY_YOUNG | \ 452 _SEGMENT_ENTRY_DIRTY | \ 453 _SEGMENT_ENTRY_NOEXEC) 454 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 455 _SEGMENT_ENTRY_LARGE | \ 456 _SEGMENT_ENTRY_READ | \ 457 _SEGMENT_ENTRY_YOUNG | \ 458 _SEGMENT_ENTRY_PROTECT | \ 459 _SEGMENT_ENTRY_NOEXEC) 460 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 461 _SEGMENT_ENTRY_LARGE | \ 462 _SEGMENT_ENTRY_READ | \ 463 _SEGMENT_ENTRY_WRITE | \ 464 _SEGMENT_ENTRY_YOUNG | \ 465 _SEGMENT_ENTRY_DIRTY) 466 467 /* 468 * Region3 entry (large page) protection definitions. 469 */ 470 471 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 472 _REGION3_ENTRY_LARGE | \ 473 _REGION3_ENTRY_READ | \ 474 _REGION3_ENTRY_WRITE | \ 475 _REGION3_ENTRY_YOUNG | \ 476 _REGION3_ENTRY_DIRTY | \ 477 _REGION_ENTRY_NOEXEC) 478 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 479 _REGION3_ENTRY_LARGE | \ 480 _REGION3_ENTRY_READ | \ 481 _REGION3_ENTRY_YOUNG | \ 482 _REGION_ENTRY_PROTECT | \ 483 _REGION_ENTRY_NOEXEC) 484 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 485 _REGION3_ENTRY_LARGE | \ 486 _REGION3_ENTRY_READ | \ 487 _REGION3_ENTRY_WRITE | \ 488 _REGION3_ENTRY_YOUNG | \ 489 _REGION3_ENTRY_DIRTY) 490 491 static inline bool mm_p4d_folded(struct mm_struct *mm) 492 { 493 return mm->context.asce_limit <= _REGION1_SIZE; 494 } 495 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 496 497 static inline bool mm_pud_folded(struct mm_struct *mm) 498 { 499 return mm->context.asce_limit <= _REGION2_SIZE; 500 } 501 #define mm_pud_folded(mm) mm_pud_folded(mm) 502 503 static inline bool mm_pmd_folded(struct mm_struct *mm) 504 { 505 return mm->context.asce_limit <= _REGION3_SIZE; 506 } 507 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 508 509 static inline int mm_has_pgste(struct mm_struct *mm) 510 { 511 #ifdef CONFIG_PGSTE 512 if (unlikely(mm->context.has_pgste)) 513 return 1; 514 #endif 515 return 0; 516 } 517 518 static inline int mm_is_protected(struct mm_struct *mm) 519 { 520 #ifdef CONFIG_PGSTE 521 if (unlikely(atomic_read(&mm->context.protected_count))) 522 return 1; 523 #endif 524 return 0; 525 } 526 527 static inline int mm_alloc_pgste(struct mm_struct *mm) 528 { 529 #ifdef CONFIG_PGSTE 530 if (unlikely(mm->context.alloc_pgste)) 531 return 1; 532 #endif 533 return 0; 534 } 535 536 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 537 { 538 return __pte(pte_val(pte) & ~pgprot_val(prot)); 539 } 540 541 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 542 { 543 return __pte(pte_val(pte) | pgprot_val(prot)); 544 } 545 546 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 547 { 548 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 549 } 550 551 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 552 { 553 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 554 } 555 556 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 557 { 558 return __pud(pud_val(pud) & ~pgprot_val(prot)); 559 } 560 561 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 562 { 563 return __pud(pud_val(pud) | pgprot_val(prot)); 564 } 565 566 /* 567 * In the case that a guest uses storage keys 568 * faults should no longer be backed by zero pages 569 */ 570 #define mm_forbids_zeropage mm_has_pgste 571 static inline int mm_uses_skeys(struct mm_struct *mm) 572 { 573 #ifdef CONFIG_PGSTE 574 if (mm->context.uses_skeys) 575 return 1; 576 #endif 577 return 0; 578 } 579 580 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 581 { 582 union register_pair r1 = { .even = old, .odd = new, }; 583 unsigned long address = (unsigned long)ptr | 1; 584 585 asm volatile( 586 " csp %[r1],%[address]" 587 : [r1] "+&d" (r1.pair), "+m" (*ptr) 588 : [address] "d" (address) 589 : "cc"); 590 } 591 592 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 593 { 594 union register_pair r1 = { .even = old, .odd = new, }; 595 unsigned long address = (unsigned long)ptr | 1; 596 597 asm volatile( 598 " cspg %[r1],%[address]" 599 : [r1] "+&d" (r1.pair), "+m" (*ptr) 600 : [address] "d" (address) 601 : "cc"); 602 } 603 604 #define CRDTE_DTT_PAGE 0x00UL 605 #define CRDTE_DTT_SEGMENT 0x10UL 606 #define CRDTE_DTT_REGION3 0x14UL 607 #define CRDTE_DTT_REGION2 0x18UL 608 #define CRDTE_DTT_REGION1 0x1cUL 609 610 static inline void crdte(unsigned long old, unsigned long new, 611 unsigned long *table, unsigned long dtt, 612 unsigned long address, unsigned long asce) 613 { 614 union register_pair r1 = { .even = old, .odd = new, }; 615 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 616 617 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 618 : [r1] "+&d" (r1.pair) 619 : [r2] "d" (r2.pair), [asce] "a" (asce) 620 : "memory", "cc"); 621 } 622 623 /* 624 * pgd/p4d/pud/pmd/pte query functions 625 */ 626 static inline int pgd_folded(pgd_t pgd) 627 { 628 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 629 } 630 631 static inline int pgd_present(pgd_t pgd) 632 { 633 if (pgd_folded(pgd)) 634 return 1; 635 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 636 } 637 638 static inline int pgd_none(pgd_t pgd) 639 { 640 if (pgd_folded(pgd)) 641 return 0; 642 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 643 } 644 645 static inline int pgd_bad(pgd_t pgd) 646 { 647 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 648 return 0; 649 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 650 } 651 652 static inline unsigned long pgd_pfn(pgd_t pgd) 653 { 654 unsigned long origin_mask; 655 656 origin_mask = _REGION_ENTRY_ORIGIN; 657 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 658 } 659 660 static inline int p4d_folded(p4d_t p4d) 661 { 662 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 663 } 664 665 static inline int p4d_present(p4d_t p4d) 666 { 667 if (p4d_folded(p4d)) 668 return 1; 669 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 670 } 671 672 static inline int p4d_none(p4d_t p4d) 673 { 674 if (p4d_folded(p4d)) 675 return 0; 676 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 677 } 678 679 static inline unsigned long p4d_pfn(p4d_t p4d) 680 { 681 unsigned long origin_mask; 682 683 origin_mask = _REGION_ENTRY_ORIGIN; 684 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 685 } 686 687 static inline int pud_folded(pud_t pud) 688 { 689 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 690 } 691 692 static inline int pud_present(pud_t pud) 693 { 694 if (pud_folded(pud)) 695 return 1; 696 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 697 } 698 699 static inline int pud_none(pud_t pud) 700 { 701 if (pud_folded(pud)) 702 return 0; 703 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 704 } 705 706 #define pud_leaf pud_large 707 static inline int pud_large(pud_t pud) 708 { 709 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 710 return 0; 711 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 712 } 713 714 #define pmd_leaf pmd_large 715 static inline int pmd_large(pmd_t pmd) 716 { 717 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 718 } 719 720 static inline int pmd_bad(pmd_t pmd) 721 { 722 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 723 return 1; 724 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 725 } 726 727 static inline int pud_bad(pud_t pud) 728 { 729 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 730 731 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud)) 732 return 1; 733 if (type < _REGION_ENTRY_TYPE_R3) 734 return 0; 735 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 736 } 737 738 static inline int p4d_bad(p4d_t p4d) 739 { 740 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 741 742 if (type > _REGION_ENTRY_TYPE_R2) 743 return 1; 744 if (type < _REGION_ENTRY_TYPE_R2) 745 return 0; 746 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 747 } 748 749 static inline int pmd_present(pmd_t pmd) 750 { 751 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 752 } 753 754 static inline int pmd_none(pmd_t pmd) 755 { 756 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 757 } 758 759 #define pmd_write pmd_write 760 static inline int pmd_write(pmd_t pmd) 761 { 762 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 763 } 764 765 #define pud_write pud_write 766 static inline int pud_write(pud_t pud) 767 { 768 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 769 } 770 771 static inline int pmd_dirty(pmd_t pmd) 772 { 773 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 774 } 775 776 #define pmd_young pmd_young 777 static inline int pmd_young(pmd_t pmd) 778 { 779 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 780 } 781 782 static inline int pte_present(pte_t pte) 783 { 784 /* Bit pattern: (pte & 0x001) == 0x001 */ 785 return (pte_val(pte) & _PAGE_PRESENT) != 0; 786 } 787 788 static inline int pte_none(pte_t pte) 789 { 790 /* Bit pattern: pte == 0x400 */ 791 return pte_val(pte) == _PAGE_INVALID; 792 } 793 794 static inline int pte_swap(pte_t pte) 795 { 796 /* Bit pattern: (pte & 0x201) == 0x200 */ 797 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 798 == _PAGE_PROTECT; 799 } 800 801 static inline int pte_special(pte_t pte) 802 { 803 return (pte_val(pte) & _PAGE_SPECIAL); 804 } 805 806 #define __HAVE_ARCH_PTE_SAME 807 static inline int pte_same(pte_t a, pte_t b) 808 { 809 return pte_val(a) == pte_val(b); 810 } 811 812 #ifdef CONFIG_NUMA_BALANCING 813 static inline int pte_protnone(pte_t pte) 814 { 815 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 816 } 817 818 static inline int pmd_protnone(pmd_t pmd) 819 { 820 /* pmd_large(pmd) implies pmd_present(pmd) */ 821 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 822 } 823 #endif 824 825 static inline int pte_swp_exclusive(pte_t pte) 826 { 827 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 828 } 829 830 static inline pte_t pte_swp_mkexclusive(pte_t pte) 831 { 832 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 833 } 834 835 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 836 { 837 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 838 } 839 840 static inline int pte_soft_dirty(pte_t pte) 841 { 842 return pte_val(pte) & _PAGE_SOFT_DIRTY; 843 } 844 #define pte_swp_soft_dirty pte_soft_dirty 845 846 static inline pte_t pte_mksoft_dirty(pte_t pte) 847 { 848 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 849 } 850 #define pte_swp_mksoft_dirty pte_mksoft_dirty 851 852 static inline pte_t pte_clear_soft_dirty(pte_t pte) 853 { 854 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 855 } 856 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 857 858 static inline int pmd_soft_dirty(pmd_t pmd) 859 { 860 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 861 } 862 863 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 864 { 865 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 866 } 867 868 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 869 { 870 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 871 } 872 873 /* 874 * query functions pte_write/pte_dirty/pte_young only work if 875 * pte_present() is true. Undefined behaviour if not.. 876 */ 877 static inline int pte_write(pte_t pte) 878 { 879 return (pte_val(pte) & _PAGE_WRITE) != 0; 880 } 881 882 static inline int pte_dirty(pte_t pte) 883 { 884 return (pte_val(pte) & _PAGE_DIRTY) != 0; 885 } 886 887 static inline int pte_young(pte_t pte) 888 { 889 return (pte_val(pte) & _PAGE_YOUNG) != 0; 890 } 891 892 #define __HAVE_ARCH_PTE_UNUSED 893 static inline int pte_unused(pte_t pte) 894 { 895 return pte_val(pte) & _PAGE_UNUSED; 896 } 897 898 /* 899 * Extract the pgprot value from the given pte while at the same time making it 900 * usable for kernel address space mappings where fault driven dirty and 901 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 902 * must not be set. 903 */ 904 static inline pgprot_t pte_pgprot(pte_t pte) 905 { 906 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 907 908 if (pte_write(pte)) 909 pte_flags |= pgprot_val(PAGE_KERNEL); 910 else 911 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 912 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 913 914 return __pgprot(pte_flags); 915 } 916 917 /* 918 * pgd/pmd/pte modification functions 919 */ 920 921 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 922 { 923 WRITE_ONCE(*pgdp, pgd); 924 } 925 926 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 927 { 928 WRITE_ONCE(*p4dp, p4d); 929 } 930 931 static inline void set_pud(pud_t *pudp, pud_t pud) 932 { 933 WRITE_ONCE(*pudp, pud); 934 } 935 936 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 937 { 938 WRITE_ONCE(*pmdp, pmd); 939 } 940 941 static inline void set_pte(pte_t *ptep, pte_t pte) 942 { 943 WRITE_ONCE(*ptep, pte); 944 } 945 946 static inline void pgd_clear(pgd_t *pgd) 947 { 948 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 949 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 950 } 951 952 static inline void p4d_clear(p4d_t *p4d) 953 { 954 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 955 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 956 } 957 958 static inline void pud_clear(pud_t *pud) 959 { 960 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 961 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 962 } 963 964 static inline void pmd_clear(pmd_t *pmdp) 965 { 966 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 967 } 968 969 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 970 { 971 set_pte(ptep, __pte(_PAGE_INVALID)); 972 } 973 974 /* 975 * The following pte modification functions only work if 976 * pte_present() is true. Undefined behaviour if not.. 977 */ 978 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 979 { 980 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 981 pte = set_pte_bit(pte, newprot); 982 /* 983 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 984 * has the invalid bit set, clear it again for readable, young pages 985 */ 986 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 987 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 988 /* 989 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 990 * protection bit set, clear it again for writable, dirty pages 991 */ 992 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 993 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 994 return pte; 995 } 996 997 static inline pte_t pte_wrprotect(pte_t pte) 998 { 999 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1000 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1001 } 1002 1003 static inline pte_t pte_mkwrite(pte_t pte) 1004 { 1005 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1006 if (pte_val(pte) & _PAGE_DIRTY) 1007 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1008 return pte; 1009 } 1010 1011 static inline pte_t pte_mkclean(pte_t pte) 1012 { 1013 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1014 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1015 } 1016 1017 static inline pte_t pte_mkdirty(pte_t pte) 1018 { 1019 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1020 if (pte_val(pte) & _PAGE_WRITE) 1021 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1022 return pte; 1023 } 1024 1025 static inline pte_t pte_mkold(pte_t pte) 1026 { 1027 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1028 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1029 } 1030 1031 static inline pte_t pte_mkyoung(pte_t pte) 1032 { 1033 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1034 if (pte_val(pte) & _PAGE_READ) 1035 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1036 return pte; 1037 } 1038 1039 static inline pte_t pte_mkspecial(pte_t pte) 1040 { 1041 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1042 } 1043 1044 #ifdef CONFIG_HUGETLB_PAGE 1045 static inline pte_t pte_mkhuge(pte_t pte) 1046 { 1047 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1048 } 1049 #endif 1050 1051 #define IPTE_GLOBAL 0 1052 #define IPTE_LOCAL 1 1053 1054 #define IPTE_NODAT 0x400 1055 #define IPTE_GUEST_ASCE 0x800 1056 1057 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1058 unsigned long opt, unsigned long asce, 1059 int local) 1060 { 1061 unsigned long pto; 1062 1063 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1064 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1065 : "+m" (*ptep) 1066 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1067 [asce] "a" (asce), [m4] "i" (local)); 1068 } 1069 1070 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1071 unsigned long opt, unsigned long asce, 1072 int local) 1073 { 1074 unsigned long pto = __pa(ptep); 1075 1076 if (__builtin_constant_p(opt) && opt == 0) { 1077 /* Invalidation + TLB flush for the pte */ 1078 asm volatile( 1079 " ipte %[r1],%[r2],0,%[m4]" 1080 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1081 [m4] "i" (local)); 1082 return; 1083 } 1084 1085 /* Invalidate ptes with options + TLB flush of the ptes */ 1086 opt = opt | (asce & _ASCE_ORIGIN); 1087 asm volatile( 1088 " ipte %[r1],%[r2],%[r3],%[m4]" 1089 : [r2] "+a" (address), [r3] "+a" (opt) 1090 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1091 } 1092 1093 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1094 pte_t *ptep, int local) 1095 { 1096 unsigned long pto = __pa(ptep); 1097 1098 /* Invalidate a range of ptes + TLB flush of the ptes */ 1099 do { 1100 asm volatile( 1101 " ipte %[r1],%[r2],%[r3],%[m4]" 1102 : [r2] "+a" (address), [r3] "+a" (nr) 1103 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1104 } while (nr != 255); 1105 } 1106 1107 /* 1108 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1109 * both clear the TLB for the unmapped pte. The reason is that 1110 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1111 * to modify an active pte. The sequence is 1112 * 1) ptep_get_and_clear 1113 * 2) set_pte_at 1114 * 3) flush_tlb_range 1115 * On s390 the tlb needs to get flushed with the modification of the pte 1116 * if the pte is active. The only way how this can be implemented is to 1117 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1118 * is a nop. 1119 */ 1120 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1121 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1122 1123 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1124 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1125 unsigned long addr, pte_t *ptep) 1126 { 1127 pte_t pte = *ptep; 1128 1129 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1130 return pte_young(pte); 1131 } 1132 1133 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1134 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1135 unsigned long address, pte_t *ptep) 1136 { 1137 return ptep_test_and_clear_young(vma, address, ptep); 1138 } 1139 1140 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1141 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1142 unsigned long addr, pte_t *ptep) 1143 { 1144 pte_t res; 1145 1146 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1147 /* At this point the reference through the mapping is still present */ 1148 if (mm_is_protected(mm) && pte_present(res)) 1149 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1150 return res; 1151 } 1152 1153 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1154 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1155 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1156 pte_t *, pte_t, pte_t); 1157 1158 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1159 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1160 unsigned long addr, pte_t *ptep) 1161 { 1162 pte_t res; 1163 1164 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1165 /* At this point the reference through the mapping is still present */ 1166 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1167 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1168 return res; 1169 } 1170 1171 /* 1172 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1173 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1174 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1175 * cannot be accessed while the batched unmap is running. In this case 1176 * full==1 and a simple pte_clear is enough. See tlb.h. 1177 */ 1178 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1179 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1180 unsigned long addr, 1181 pte_t *ptep, int full) 1182 { 1183 pte_t res; 1184 1185 if (full) { 1186 res = *ptep; 1187 set_pte(ptep, __pte(_PAGE_INVALID)); 1188 } else { 1189 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1190 } 1191 /* Nothing to do */ 1192 if (!mm_is_protected(mm) || !pte_present(res)) 1193 return res; 1194 /* 1195 * At this point the reference through the mapping is still present. 1196 * The notifier should have destroyed all protected vCPUs at this 1197 * point, so the destroy should be successful. 1198 */ 1199 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1200 return res; 1201 /* 1202 * If something went wrong and the page could not be destroyed, or 1203 * if this is not a mm teardown, the slower export is used as 1204 * fallback instead. 1205 */ 1206 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1207 return res; 1208 } 1209 1210 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1211 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1212 unsigned long addr, pte_t *ptep) 1213 { 1214 pte_t pte = *ptep; 1215 1216 if (pte_write(pte)) 1217 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1218 } 1219 1220 /* 1221 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1222 * bits in the comparison. Those might change e.g. because of dirty and young 1223 * tracking. 1224 */ 1225 static inline int pte_allow_rdp(pte_t old, pte_t new) 1226 { 1227 /* 1228 * Only allow changes from RO to RW 1229 */ 1230 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1231 return 0; 1232 1233 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1234 } 1235 1236 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1237 unsigned long address, 1238 pte_t *ptep) 1239 { 1240 /* 1241 * RDP might not have propagated the PTE protection reset to all CPUs, 1242 * so there could be spurious TLB protection faults. 1243 * NOTE: This will also be called when a racing pagetable update on 1244 * another thread already installed the correct PTE. Both cases cannot 1245 * really be distinguished. 1246 * Therefore, only do the local TLB flush when RDP can be used, and the 1247 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1248 * A local RDP can be used to do the flush. 1249 */ 1250 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1251 __ptep_rdp(address, ptep, 0, 0, 1); 1252 } 1253 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1254 1255 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1256 pte_t new); 1257 1258 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1259 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1260 unsigned long addr, pte_t *ptep, 1261 pte_t entry, int dirty) 1262 { 1263 if (pte_same(*ptep, entry)) 1264 return 0; 1265 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1266 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1267 else 1268 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1269 return 1; 1270 } 1271 1272 /* 1273 * Additional functions to handle KVM guest page tables 1274 */ 1275 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1276 pte_t *ptep, pte_t entry); 1277 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1278 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1279 pte_t *ptep, unsigned long bits); 1280 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1281 pte_t *ptep, int prot, unsigned long bit); 1282 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1283 pte_t *ptep , int reset); 1284 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1285 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1286 pte_t *sptep, pte_t *tptep, pte_t pte); 1287 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1288 1289 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1290 pte_t *ptep); 1291 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1292 unsigned char key, bool nq); 1293 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1294 unsigned char key, unsigned char *oldkey, 1295 bool nq, bool mr, bool mc); 1296 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1297 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1298 unsigned char *key); 1299 1300 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1301 unsigned long bits, unsigned long value); 1302 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1303 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1304 unsigned long *oldpte, unsigned long *oldpgste); 1305 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1306 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1307 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1308 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1309 1310 #define pgprot_writecombine pgprot_writecombine 1311 pgprot_t pgprot_writecombine(pgprot_t prot); 1312 1313 #define pgprot_writethrough pgprot_writethrough 1314 pgprot_t pgprot_writethrough(pgprot_t prot); 1315 1316 /* 1317 * Certain architectures need to do special things when PTEs 1318 * within a page table are directly modified. Thus, the following 1319 * hook is made available. 1320 */ 1321 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 1322 pte_t *ptep, pte_t entry) 1323 { 1324 if (pte_present(entry)) 1325 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1326 if (mm_has_pgste(mm)) 1327 ptep_set_pte_at(mm, addr, ptep, entry); 1328 else 1329 set_pte(ptep, entry); 1330 } 1331 1332 /* 1333 * Conversion functions: convert a page and protection to a page entry, 1334 * and a page entry and page directory to the page they refer to. 1335 */ 1336 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1337 { 1338 pte_t __pte; 1339 1340 __pte = __pte(physpage | pgprot_val(pgprot)); 1341 if (!MACHINE_HAS_NX) 1342 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1343 return pte_mkyoung(__pte); 1344 } 1345 1346 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1347 { 1348 unsigned long physpage = page_to_phys(page); 1349 pte_t __pte = mk_pte_phys(physpage, pgprot); 1350 1351 if (pte_write(__pte) && PageDirty(page)) 1352 __pte = pte_mkdirty(__pte); 1353 return __pte; 1354 } 1355 1356 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1357 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1358 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1359 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1360 1361 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1362 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1363 1364 static inline unsigned long pmd_deref(pmd_t pmd) 1365 { 1366 unsigned long origin_mask; 1367 1368 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1369 if (pmd_large(pmd)) 1370 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1371 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1372 } 1373 1374 static inline unsigned long pmd_pfn(pmd_t pmd) 1375 { 1376 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1377 } 1378 1379 static inline unsigned long pud_deref(pud_t pud) 1380 { 1381 unsigned long origin_mask; 1382 1383 origin_mask = _REGION_ENTRY_ORIGIN; 1384 if (pud_large(pud)) 1385 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1386 return (unsigned long)__va(pud_val(pud) & origin_mask); 1387 } 1388 1389 static inline unsigned long pud_pfn(pud_t pud) 1390 { 1391 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1392 } 1393 1394 /* 1395 * The pgd_offset function *always* adds the index for the top-level 1396 * region/segment table. This is done to get a sequence like the 1397 * following to work: 1398 * pgdp = pgd_offset(current->mm, addr); 1399 * pgd = READ_ONCE(*pgdp); 1400 * p4dp = p4d_offset(&pgd, addr); 1401 * ... 1402 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1403 * only add an index if they dereferenced the pointer. 1404 */ 1405 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1406 { 1407 unsigned long rste; 1408 unsigned int shift; 1409 1410 /* Get the first entry of the top level table */ 1411 rste = pgd_val(*pgd); 1412 /* Pick up the shift from the table type of the first entry */ 1413 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1414 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1415 } 1416 1417 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1418 1419 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1420 { 1421 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1422 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1423 return (p4d_t *) pgdp; 1424 } 1425 #define p4d_offset_lockless p4d_offset_lockless 1426 1427 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1428 { 1429 return p4d_offset_lockless(pgdp, *pgdp, address); 1430 } 1431 1432 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1433 { 1434 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1435 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1436 return (pud_t *) p4dp; 1437 } 1438 #define pud_offset_lockless pud_offset_lockless 1439 1440 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1441 { 1442 return pud_offset_lockless(p4dp, *p4dp, address); 1443 } 1444 #define pud_offset pud_offset 1445 1446 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1447 { 1448 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1449 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1450 return (pmd_t *) pudp; 1451 } 1452 #define pmd_offset_lockless pmd_offset_lockless 1453 1454 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1455 { 1456 return pmd_offset_lockless(pudp, *pudp, address); 1457 } 1458 #define pmd_offset pmd_offset 1459 1460 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1461 { 1462 return (unsigned long) pmd_deref(pmd); 1463 } 1464 1465 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1466 { 1467 return end <= current->mm->context.asce_limit; 1468 } 1469 #define gup_fast_permitted gup_fast_permitted 1470 1471 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1472 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1473 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1474 1475 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1476 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1477 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1478 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1479 1480 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1481 { 1482 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1483 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1484 } 1485 1486 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1487 { 1488 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1489 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1490 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1491 return pmd; 1492 } 1493 1494 static inline pmd_t pmd_mkclean(pmd_t pmd) 1495 { 1496 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1497 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1498 } 1499 1500 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1501 { 1502 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1503 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1504 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1505 return pmd; 1506 } 1507 1508 static inline pud_t pud_wrprotect(pud_t pud) 1509 { 1510 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1511 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1512 } 1513 1514 static inline pud_t pud_mkwrite(pud_t pud) 1515 { 1516 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1517 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1518 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1519 return pud; 1520 } 1521 1522 static inline pud_t pud_mkclean(pud_t pud) 1523 { 1524 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1525 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1526 } 1527 1528 static inline pud_t pud_mkdirty(pud_t pud) 1529 { 1530 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1531 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1532 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1533 return pud; 1534 } 1535 1536 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1537 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1538 { 1539 /* 1540 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1541 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1542 */ 1543 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1544 return pgprot_val(SEGMENT_NONE); 1545 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1546 return pgprot_val(SEGMENT_RO); 1547 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1548 return pgprot_val(SEGMENT_RX); 1549 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1550 return pgprot_val(SEGMENT_RW); 1551 return pgprot_val(SEGMENT_RWX); 1552 } 1553 1554 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1555 { 1556 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1557 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1558 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1559 return pmd; 1560 } 1561 1562 static inline pmd_t pmd_mkold(pmd_t pmd) 1563 { 1564 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1565 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1566 } 1567 1568 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1569 { 1570 unsigned long mask; 1571 1572 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1573 mask |= _SEGMENT_ENTRY_DIRTY; 1574 mask |= _SEGMENT_ENTRY_YOUNG; 1575 mask |= _SEGMENT_ENTRY_LARGE; 1576 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1577 pmd = __pmd(pmd_val(pmd) & mask); 1578 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1579 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1580 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1581 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1582 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1583 return pmd; 1584 } 1585 1586 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1587 { 1588 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1589 } 1590 1591 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1592 1593 static inline void __pmdp_csp(pmd_t *pmdp) 1594 { 1595 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1596 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1597 } 1598 1599 #define IDTE_GLOBAL 0 1600 #define IDTE_LOCAL 1 1601 1602 #define IDTE_PTOA 0x0800 1603 #define IDTE_NODAT 0x1000 1604 #define IDTE_GUEST_ASCE 0x2000 1605 1606 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1607 unsigned long opt, unsigned long asce, 1608 int local) 1609 { 1610 unsigned long sto; 1611 1612 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1613 if (__builtin_constant_p(opt) && opt == 0) { 1614 /* flush without guest asce */ 1615 asm volatile( 1616 " idte %[r1],0,%[r2],%[m4]" 1617 : "+m" (*pmdp) 1618 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1619 [m4] "i" (local) 1620 : "cc" ); 1621 } else { 1622 /* flush with guest asce */ 1623 asm volatile( 1624 " idte %[r1],%[r3],%[r2],%[m4]" 1625 : "+m" (*pmdp) 1626 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1627 [r3] "a" (asce), [m4] "i" (local) 1628 : "cc" ); 1629 } 1630 } 1631 1632 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1633 unsigned long opt, unsigned long asce, 1634 int local) 1635 { 1636 unsigned long r3o; 1637 1638 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1639 r3o |= _ASCE_TYPE_REGION3; 1640 if (__builtin_constant_p(opt) && opt == 0) { 1641 /* flush without guest asce */ 1642 asm volatile( 1643 " idte %[r1],0,%[r2],%[m4]" 1644 : "+m" (*pudp) 1645 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1646 [m4] "i" (local) 1647 : "cc"); 1648 } else { 1649 /* flush with guest asce */ 1650 asm volatile( 1651 " idte %[r1],%[r3],%[r2],%[m4]" 1652 : "+m" (*pudp) 1653 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1654 [r3] "a" (asce), [m4] "i" (local) 1655 : "cc" ); 1656 } 1657 } 1658 1659 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1660 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1661 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1662 1663 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1664 1665 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1666 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1667 pgtable_t pgtable); 1668 1669 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1670 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1671 1672 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1673 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1674 unsigned long addr, pmd_t *pmdp, 1675 pmd_t entry, int dirty) 1676 { 1677 VM_BUG_ON(addr & ~HPAGE_MASK); 1678 1679 entry = pmd_mkyoung(entry); 1680 if (dirty) 1681 entry = pmd_mkdirty(entry); 1682 if (pmd_val(*pmdp) == pmd_val(entry)) 1683 return 0; 1684 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1685 return 1; 1686 } 1687 1688 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1689 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1690 unsigned long addr, pmd_t *pmdp) 1691 { 1692 pmd_t pmd = *pmdp; 1693 1694 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1695 return pmd_young(pmd); 1696 } 1697 1698 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1699 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1700 unsigned long addr, pmd_t *pmdp) 1701 { 1702 VM_BUG_ON(addr & ~HPAGE_MASK); 1703 return pmdp_test_and_clear_young(vma, addr, pmdp); 1704 } 1705 1706 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1707 pmd_t *pmdp, pmd_t entry) 1708 { 1709 if (!MACHINE_HAS_NX) 1710 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1711 set_pmd(pmdp, entry); 1712 } 1713 1714 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1715 { 1716 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1717 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1718 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1719 } 1720 1721 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1722 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1723 unsigned long addr, pmd_t *pmdp) 1724 { 1725 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1726 } 1727 1728 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1729 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1730 unsigned long addr, 1731 pmd_t *pmdp, int full) 1732 { 1733 if (full) { 1734 pmd_t pmd = *pmdp; 1735 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1736 return pmd; 1737 } 1738 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1739 } 1740 1741 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1742 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1743 unsigned long addr, pmd_t *pmdp) 1744 { 1745 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1746 } 1747 1748 #define __HAVE_ARCH_PMDP_INVALIDATE 1749 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1750 unsigned long addr, pmd_t *pmdp) 1751 { 1752 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1753 1754 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1755 } 1756 1757 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1758 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1759 unsigned long addr, pmd_t *pmdp) 1760 { 1761 pmd_t pmd = *pmdp; 1762 1763 if (pmd_write(pmd)) 1764 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1765 } 1766 1767 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1768 unsigned long address, 1769 pmd_t *pmdp) 1770 { 1771 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1772 } 1773 #define pmdp_collapse_flush pmdp_collapse_flush 1774 1775 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1776 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1777 1778 static inline int pmd_trans_huge(pmd_t pmd) 1779 { 1780 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1781 } 1782 1783 #define has_transparent_hugepage has_transparent_hugepage 1784 static inline int has_transparent_hugepage(void) 1785 { 1786 return MACHINE_HAS_EDAT1 ? 1 : 0; 1787 } 1788 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1789 1790 /* 1791 * 64 bit swap entry format: 1792 * A page-table entry has some bits we have to treat in a special way. 1793 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1794 * as invalid. 1795 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1796 * | offset |E11XX|type |S0| 1797 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1798 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1799 * 1800 * Bits 0-51 store the offset. 1801 * Bit 52 (E) is used to remember PG_anon_exclusive. 1802 * Bits 57-61 store the type. 1803 * Bit 62 (S) is used for softdirty tracking. 1804 * Bits 55 and 56 (X) are unused. 1805 */ 1806 1807 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1808 #define __SWP_OFFSET_SHIFT 12 1809 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1810 #define __SWP_TYPE_SHIFT 2 1811 1812 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1813 { 1814 unsigned long pteval; 1815 1816 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1817 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1818 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1819 return __pte(pteval); 1820 } 1821 1822 static inline unsigned long __swp_type(swp_entry_t entry) 1823 { 1824 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1825 } 1826 1827 static inline unsigned long __swp_offset(swp_entry_t entry) 1828 { 1829 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1830 } 1831 1832 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1833 { 1834 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1835 } 1836 1837 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1838 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1839 1840 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1841 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1842 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1843 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1844 extern void vmem_unmap_4k_page(unsigned long addr); 1845 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1846 extern int s390_enable_sie(void); 1847 extern int s390_enable_skey(void); 1848 extern void s390_reset_cmma(struct mm_struct *mm); 1849 1850 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1851 #define HAVE_ARCH_UNMAPPED_AREA 1852 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1853 1854 #define pmd_pgtable(pmd) \ 1855 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1856 1857 #endif /* _S390_PAGE_H */ 1858