1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/bug.h> 21 #include <asm/page.h> 22 #include <asm/uv.h> 23 24 extern pgd_t swapper_pg_dir[]; 25 extern void paging_init(void); 26 extern unsigned long s390_invalid_asce; 27 28 enum { 29 PG_DIRECT_MAP_4K = 0, 30 PG_DIRECT_MAP_1M, 31 PG_DIRECT_MAP_2G, 32 PG_DIRECT_MAP_MAX 33 }; 34 35 extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; 36 37 static inline void update_page_count(int level, long count) 38 { 39 if (IS_ENABLED(CONFIG_PROC_FS)) 40 atomic_long_add(count, &direct_pages_count[level]); 41 } 42 43 struct seq_file; 44 void arch_report_meminfo(struct seq_file *m); 45 46 /* 47 * The S390 doesn't have any external MMU info: the kernel page 48 * tables contain all the necessary information. 49 */ 50 #define update_mmu_cache(vma, address, ptep) do { } while (0) 51 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 52 53 /* 54 * ZERO_PAGE is a global shared page that is always zero; used 55 * for zero-mapped memory areas etc.. 56 */ 57 58 extern unsigned long empty_zero_page; 59 extern unsigned long zero_page_mask; 60 61 #define ZERO_PAGE(vaddr) \ 62 (virt_to_page((void *)(empty_zero_page + \ 63 (((unsigned long)(vaddr)) &zero_page_mask)))) 64 #define __HAVE_COLOR_ZERO_PAGE 65 66 /* TODO: s390 cannot support io_remap_pfn_range... */ 67 68 #define FIRST_USER_ADDRESS 0UL 69 70 #define pte_ERROR(e) \ 71 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 72 #define pmd_ERROR(e) \ 73 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 74 #define pud_ERROR(e) \ 75 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 76 #define p4d_ERROR(e) \ 77 printk("%s:%d: bad p4d %p.\n", __FILE__, __LINE__, (void *) p4d_val(e)) 78 #define pgd_ERROR(e) \ 79 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 80 81 /* 82 * The vmalloc and module area will always be on the topmost area of the 83 * kernel mapping. 512GB are reserved for vmalloc by default. 84 * At the top of the vmalloc area a 2GB area is reserved where modules 85 * will reside. That makes sure that inter module branches always 86 * happen without trampolines and in addition the placement within a 87 * 2GB frame is branch prediction unit friendly. 88 */ 89 extern unsigned long VMALLOC_START; 90 extern unsigned long VMALLOC_END; 91 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 92 extern struct page *vmemmap; 93 extern unsigned long vmemmap_size; 94 95 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 96 97 extern unsigned long MODULES_VADDR; 98 extern unsigned long MODULES_END; 99 #define MODULES_VADDR MODULES_VADDR 100 #define MODULES_END MODULES_END 101 #define MODULES_LEN (1UL << 31) 102 103 static inline int is_module_addr(void *addr) 104 { 105 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 106 if (addr < (void *)MODULES_VADDR) 107 return 0; 108 if (addr > (void *)MODULES_END) 109 return 0; 110 return 1; 111 } 112 113 /* 114 * A 64 bit pagetable entry of S390 has following format: 115 * | PFRA |0IPC| OS | 116 * 0000000000111111111122222222223333333333444444444455555555556666 117 * 0123456789012345678901234567890123456789012345678901234567890123 118 * 119 * I Page-Invalid Bit: Page is not available for address-translation 120 * P Page-Protection Bit: Store access not possible for page 121 * C Change-bit override: HW is not required to set change bit 122 * 123 * A 64 bit segmenttable entry of S390 has following format: 124 * | P-table origin | TT 125 * 0000000000111111111122222222223333333333444444444455555555556666 126 * 0123456789012345678901234567890123456789012345678901234567890123 127 * 128 * I Segment-Invalid Bit: Segment is not available for address-translation 129 * C Common-Segment Bit: Segment is not private (PoP 3-30) 130 * P Page-Protection Bit: Store access not possible for page 131 * TT Type 00 132 * 133 * A 64 bit region table entry of S390 has following format: 134 * | S-table origin | TF TTTL 135 * 0000000000111111111122222222223333333333444444444455555555556666 136 * 0123456789012345678901234567890123456789012345678901234567890123 137 * 138 * I Segment-Invalid Bit: Segment is not available for address-translation 139 * TT Type 01 140 * TF 141 * TL Table length 142 * 143 * The 64 bit regiontable origin of S390 has following format: 144 * | region table origon | DTTL 145 * 0000000000111111111122222222223333333333444444444455555555556666 146 * 0123456789012345678901234567890123456789012345678901234567890123 147 * 148 * X Space-Switch event: 149 * G Segment-Invalid Bit: 150 * P Private-Space Bit: 151 * S Storage-Alteration: 152 * R Real space 153 * TL Table-Length: 154 * 155 * A storage key has the following format: 156 * | ACC |F|R|C|0| 157 * 0 3 4 5 6 7 158 * ACC: access key 159 * F : fetch protection bit 160 * R : referenced bit 161 * C : changed bit 162 */ 163 164 /* Hardware bits in the page table entry */ 165 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 166 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 167 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 168 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 169 170 /* Software bits in the page table entry */ 171 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 172 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 173 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 174 #define _PAGE_READ 0x010 /* SW pte read bit */ 175 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 176 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 177 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 178 179 #ifdef CONFIG_MEM_SOFT_DIRTY 180 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 181 #else 182 #define _PAGE_SOFT_DIRTY 0x000 183 #endif 184 185 /* Set of bits not changed in pte_modify */ 186 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 187 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 188 189 /* 190 * handle_pte_fault uses pte_present and pte_none to find out the pte type 191 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 192 * distinguish present from not-present ptes. It is changed only with the page 193 * table lock held. 194 * 195 * The following table gives the different possible bit combinations for 196 * the pte hardware and software bits in the last 12 bits of a pte 197 * (. unassigned bit, x don't care, t swap type): 198 * 199 * 842100000000 200 * 000084210000 201 * 000000008421 202 * .IR.uswrdy.p 203 * empty .10.00000000 204 * swap .11..ttttt.0 205 * prot-none, clean, old .11.xx0000.1 206 * prot-none, clean, young .11.xx0001.1 207 * prot-none, dirty, old .11.xx0010.1 208 * prot-none, dirty, young .11.xx0011.1 209 * read-only, clean, old .11.xx0100.1 210 * read-only, clean, young .01.xx0101.1 211 * read-only, dirty, old .11.xx0110.1 212 * read-only, dirty, young .01.xx0111.1 213 * read-write, clean, old .11.xx1100.1 214 * read-write, clean, young .01.xx1101.1 215 * read-write, dirty, old .10.xx1110.1 216 * read-write, dirty, young .00.xx1111.1 217 * HW-bits: R read-only, I invalid 218 * SW-bits: p present, y young, d dirty, r read, w write, s special, 219 * u unused, l large 220 * 221 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 222 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 223 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 224 */ 225 226 /* Bits in the segment/region table address-space-control-element */ 227 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 228 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 229 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 230 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 231 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 232 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 233 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 234 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 235 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 236 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 237 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 238 239 /* Bits in the region table entry */ 240 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 241 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 242 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 243 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 244 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 245 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 246 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 247 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 248 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 249 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 250 251 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 252 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 253 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 254 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 255 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 256 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 257 258 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 259 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 260 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 261 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 262 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 263 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 264 265 #ifdef CONFIG_MEM_SOFT_DIRTY 266 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 267 #else 268 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 269 #endif 270 271 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 272 273 /* Bits in the segment table entry */ 274 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 275 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 276 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 277 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 278 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 279 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 280 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 281 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 282 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 283 284 #define _SEGMENT_ENTRY (0) 285 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 286 287 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 288 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 289 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 290 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 291 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 292 293 #ifdef CONFIG_MEM_SOFT_DIRTY 294 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 295 #else 296 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 297 #endif 298 299 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 300 #define _PAGE_ENTRIES 256 /* number of page table entries */ 301 302 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 303 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 304 305 #define _REGION1_SHIFT 53 306 #define _REGION2_SHIFT 42 307 #define _REGION3_SHIFT 31 308 #define _SEGMENT_SHIFT 20 309 310 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 311 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 312 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 313 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 314 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 315 316 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 317 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 318 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 319 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 320 321 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 322 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 323 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 324 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 325 326 #define PMD_SHIFT _SEGMENT_SHIFT 327 #define PUD_SHIFT _REGION3_SHIFT 328 #define P4D_SHIFT _REGION2_SHIFT 329 #define PGDIR_SHIFT _REGION1_SHIFT 330 331 #define PMD_SIZE _SEGMENT_SIZE 332 #define PUD_SIZE _REGION3_SIZE 333 #define P4D_SIZE _REGION2_SIZE 334 #define PGDIR_SIZE _REGION1_SIZE 335 336 #define PMD_MASK _SEGMENT_MASK 337 #define PUD_MASK _REGION3_MASK 338 #define P4D_MASK _REGION2_MASK 339 #define PGDIR_MASK _REGION1_MASK 340 341 #define PTRS_PER_PTE _PAGE_ENTRIES 342 #define PTRS_PER_PMD _CRST_ENTRIES 343 #define PTRS_PER_PUD _CRST_ENTRIES 344 #define PTRS_PER_P4D _CRST_ENTRIES 345 #define PTRS_PER_PGD _CRST_ENTRIES 346 347 /* 348 * Segment table and region3 table entry encoding 349 * (R = read-only, I = invalid, y = young bit): 350 * dy..R...I...wr 351 * prot-none, clean, old 00..1...1...00 352 * prot-none, clean, young 01..1...1...00 353 * prot-none, dirty, old 10..1...1...00 354 * prot-none, dirty, young 11..1...1...00 355 * read-only, clean, old 00..1...1...01 356 * read-only, clean, young 01..1...0...01 357 * read-only, dirty, old 10..1...1...01 358 * read-only, dirty, young 11..1...0...01 359 * read-write, clean, old 00..1...1...11 360 * read-write, clean, young 01..1...0...11 361 * read-write, dirty, old 10..0...1...11 362 * read-write, dirty, young 11..0...0...11 363 * The segment table origin is used to distinguish empty (origin==0) from 364 * read-write, old segment table entries (origin!=0) 365 * HW-bits: R read-only, I invalid 366 * SW-bits: y young, d dirty, r read, w write 367 */ 368 369 /* Page status table bits for virtualization */ 370 #define PGSTE_ACC_BITS 0xf000000000000000UL 371 #define PGSTE_FP_BIT 0x0800000000000000UL 372 #define PGSTE_PCL_BIT 0x0080000000000000UL 373 #define PGSTE_HR_BIT 0x0040000000000000UL 374 #define PGSTE_HC_BIT 0x0020000000000000UL 375 #define PGSTE_GR_BIT 0x0004000000000000UL 376 #define PGSTE_GC_BIT 0x0002000000000000UL 377 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 378 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 379 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 380 381 /* Guest Page State used for virtualization */ 382 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 383 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 384 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 385 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 386 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 387 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 388 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 389 390 /* 391 * A user page table pointer has the space-switch-event bit, the 392 * private-space-control bit and the storage-alteration-event-control 393 * bit set. A kernel page table pointer doesn't need them. 394 */ 395 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 396 _ASCE_ALT_EVENT) 397 398 /* 399 * Page protection definitions. 400 */ 401 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 402 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 403 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 404 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 405 _PAGE_INVALID | _PAGE_PROTECT) 406 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 407 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 408 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 409 _PAGE_INVALID | _PAGE_PROTECT) 410 411 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 412 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 413 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 414 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 415 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 416 _PAGE_PROTECT | _PAGE_NOEXEC) 417 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 418 _PAGE_YOUNG | _PAGE_DIRTY) 419 420 /* 421 * On s390 the page table entry has an invalid bit and a read-only bit. 422 * Read permission implies execute permission and write permission 423 * implies read permission. 424 */ 425 /*xwr*/ 426 #define __P000 PAGE_NONE 427 #define __P001 PAGE_RO 428 #define __P010 PAGE_RO 429 #define __P011 PAGE_RO 430 #define __P100 PAGE_RX 431 #define __P101 PAGE_RX 432 #define __P110 PAGE_RX 433 #define __P111 PAGE_RX 434 435 #define __S000 PAGE_NONE 436 #define __S001 PAGE_RO 437 #define __S010 PAGE_RW 438 #define __S011 PAGE_RW 439 #define __S100 PAGE_RX 440 #define __S101 PAGE_RX 441 #define __S110 PAGE_RWX 442 #define __S111 PAGE_RWX 443 444 /* 445 * Segment entry (large page) protection definitions. 446 */ 447 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 448 _SEGMENT_ENTRY_PROTECT) 449 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 450 _SEGMENT_ENTRY_READ | \ 451 _SEGMENT_ENTRY_NOEXEC) 452 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 453 _SEGMENT_ENTRY_READ) 454 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 455 _SEGMENT_ENTRY_WRITE | \ 456 _SEGMENT_ENTRY_NOEXEC) 457 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 458 _SEGMENT_ENTRY_WRITE) 459 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 460 _SEGMENT_ENTRY_LARGE | \ 461 _SEGMENT_ENTRY_READ | \ 462 _SEGMENT_ENTRY_WRITE | \ 463 _SEGMENT_ENTRY_YOUNG | \ 464 _SEGMENT_ENTRY_DIRTY | \ 465 _SEGMENT_ENTRY_NOEXEC) 466 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 467 _SEGMENT_ENTRY_LARGE | \ 468 _SEGMENT_ENTRY_READ | \ 469 _SEGMENT_ENTRY_YOUNG | \ 470 _SEGMENT_ENTRY_PROTECT | \ 471 _SEGMENT_ENTRY_NOEXEC) 472 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 473 _SEGMENT_ENTRY_LARGE | \ 474 _SEGMENT_ENTRY_READ | \ 475 _SEGMENT_ENTRY_WRITE | \ 476 _SEGMENT_ENTRY_YOUNG | \ 477 _SEGMENT_ENTRY_DIRTY) 478 479 /* 480 * Region3 entry (large page) protection definitions. 481 */ 482 483 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 484 _REGION3_ENTRY_LARGE | \ 485 _REGION3_ENTRY_READ | \ 486 _REGION3_ENTRY_WRITE | \ 487 _REGION3_ENTRY_YOUNG | \ 488 _REGION3_ENTRY_DIRTY | \ 489 _REGION_ENTRY_NOEXEC) 490 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 491 _REGION3_ENTRY_LARGE | \ 492 _REGION3_ENTRY_READ | \ 493 _REGION3_ENTRY_YOUNG | \ 494 _REGION_ENTRY_PROTECT | \ 495 _REGION_ENTRY_NOEXEC) 496 497 static inline bool mm_p4d_folded(struct mm_struct *mm) 498 { 499 return mm->context.asce_limit <= _REGION1_SIZE; 500 } 501 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 502 503 static inline bool mm_pud_folded(struct mm_struct *mm) 504 { 505 return mm->context.asce_limit <= _REGION2_SIZE; 506 } 507 #define mm_pud_folded(mm) mm_pud_folded(mm) 508 509 static inline bool mm_pmd_folded(struct mm_struct *mm) 510 { 511 return mm->context.asce_limit <= _REGION3_SIZE; 512 } 513 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 514 515 static inline int mm_has_pgste(struct mm_struct *mm) 516 { 517 #ifdef CONFIG_PGSTE 518 if (unlikely(mm->context.has_pgste)) 519 return 1; 520 #endif 521 return 0; 522 } 523 524 static inline int mm_is_protected(struct mm_struct *mm) 525 { 526 #ifdef CONFIG_PGSTE 527 if (unlikely(atomic_read(&mm->context.is_protected))) 528 return 1; 529 #endif 530 return 0; 531 } 532 533 static inline int mm_alloc_pgste(struct mm_struct *mm) 534 { 535 #ifdef CONFIG_PGSTE 536 if (unlikely(mm->context.alloc_pgste)) 537 return 1; 538 #endif 539 return 0; 540 } 541 542 /* 543 * In the case that a guest uses storage keys 544 * faults should no longer be backed by zero pages 545 */ 546 #define mm_forbids_zeropage mm_has_pgste 547 static inline int mm_uses_skeys(struct mm_struct *mm) 548 { 549 #ifdef CONFIG_PGSTE 550 if (mm->context.uses_skeys) 551 return 1; 552 #endif 553 return 0; 554 } 555 556 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 557 { 558 register unsigned long reg2 asm("2") = old; 559 register unsigned long reg3 asm("3") = new; 560 unsigned long address = (unsigned long)ptr | 1; 561 562 asm volatile( 563 " csp %0,%3" 564 : "+d" (reg2), "+m" (*ptr) 565 : "d" (reg3), "d" (address) 566 : "cc"); 567 } 568 569 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 570 { 571 register unsigned long reg2 asm("2") = old; 572 register unsigned long reg3 asm("3") = new; 573 unsigned long address = (unsigned long)ptr | 1; 574 575 asm volatile( 576 " .insn rre,0xb98a0000,%0,%3" 577 : "+d" (reg2), "+m" (*ptr) 578 : "d" (reg3), "d" (address) 579 : "cc"); 580 } 581 582 #define CRDTE_DTT_PAGE 0x00UL 583 #define CRDTE_DTT_SEGMENT 0x10UL 584 #define CRDTE_DTT_REGION3 0x14UL 585 #define CRDTE_DTT_REGION2 0x18UL 586 #define CRDTE_DTT_REGION1 0x1cUL 587 588 static inline void crdte(unsigned long old, unsigned long new, 589 unsigned long table, unsigned long dtt, 590 unsigned long address, unsigned long asce) 591 { 592 register unsigned long reg2 asm("2") = old; 593 register unsigned long reg3 asm("3") = new; 594 register unsigned long reg4 asm("4") = table | dtt; 595 register unsigned long reg5 asm("5") = address; 596 597 asm volatile(".insn rrf,0xb98f0000,%0,%2,%4,0" 598 : "+d" (reg2) 599 : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce) 600 : "memory", "cc"); 601 } 602 603 /* 604 * pgd/p4d/pud/pmd/pte query functions 605 */ 606 static inline int pgd_folded(pgd_t pgd) 607 { 608 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 609 } 610 611 static inline int pgd_present(pgd_t pgd) 612 { 613 if (pgd_folded(pgd)) 614 return 1; 615 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 616 } 617 618 static inline int pgd_none(pgd_t pgd) 619 { 620 if (pgd_folded(pgd)) 621 return 0; 622 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 623 } 624 625 static inline int pgd_bad(pgd_t pgd) 626 { 627 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 628 return 0; 629 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 630 } 631 632 static inline unsigned long pgd_pfn(pgd_t pgd) 633 { 634 unsigned long origin_mask; 635 636 origin_mask = _REGION_ENTRY_ORIGIN; 637 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 638 } 639 640 static inline int p4d_folded(p4d_t p4d) 641 { 642 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 643 } 644 645 static inline int p4d_present(p4d_t p4d) 646 { 647 if (p4d_folded(p4d)) 648 return 1; 649 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 650 } 651 652 static inline int p4d_none(p4d_t p4d) 653 { 654 if (p4d_folded(p4d)) 655 return 0; 656 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 657 } 658 659 static inline unsigned long p4d_pfn(p4d_t p4d) 660 { 661 unsigned long origin_mask; 662 663 origin_mask = _REGION_ENTRY_ORIGIN; 664 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 665 } 666 667 static inline int pud_folded(pud_t pud) 668 { 669 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 670 } 671 672 static inline int pud_present(pud_t pud) 673 { 674 if (pud_folded(pud)) 675 return 1; 676 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 677 } 678 679 static inline int pud_none(pud_t pud) 680 { 681 if (pud_folded(pud)) 682 return 0; 683 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 684 } 685 686 #define pud_leaf pud_large 687 static inline int pud_large(pud_t pud) 688 { 689 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 690 return 0; 691 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 692 } 693 694 #define pmd_leaf pmd_large 695 static inline int pmd_large(pmd_t pmd) 696 { 697 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 698 } 699 700 static inline int pmd_bad(pmd_t pmd) 701 { 702 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 703 return 1; 704 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 705 } 706 707 static inline int pud_bad(pud_t pud) 708 { 709 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 710 711 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud)) 712 return 1; 713 if (type < _REGION_ENTRY_TYPE_R3) 714 return 0; 715 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 716 } 717 718 static inline int p4d_bad(p4d_t p4d) 719 { 720 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 721 722 if (type > _REGION_ENTRY_TYPE_R2) 723 return 1; 724 if (type < _REGION_ENTRY_TYPE_R2) 725 return 0; 726 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 727 } 728 729 static inline int pmd_present(pmd_t pmd) 730 { 731 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 732 } 733 734 static inline int pmd_none(pmd_t pmd) 735 { 736 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 737 } 738 739 #define pmd_write pmd_write 740 static inline int pmd_write(pmd_t pmd) 741 { 742 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 743 } 744 745 #define pud_write pud_write 746 static inline int pud_write(pud_t pud) 747 { 748 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 749 } 750 751 static inline int pmd_dirty(pmd_t pmd) 752 { 753 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 754 } 755 756 static inline int pmd_young(pmd_t pmd) 757 { 758 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 759 } 760 761 static inline int pte_present(pte_t pte) 762 { 763 /* Bit pattern: (pte & 0x001) == 0x001 */ 764 return (pte_val(pte) & _PAGE_PRESENT) != 0; 765 } 766 767 static inline int pte_none(pte_t pte) 768 { 769 /* Bit pattern: pte == 0x400 */ 770 return pte_val(pte) == _PAGE_INVALID; 771 } 772 773 static inline int pte_swap(pte_t pte) 774 { 775 /* Bit pattern: (pte & 0x201) == 0x200 */ 776 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 777 == _PAGE_PROTECT; 778 } 779 780 static inline int pte_special(pte_t pte) 781 { 782 return (pte_val(pte) & _PAGE_SPECIAL); 783 } 784 785 #define __HAVE_ARCH_PTE_SAME 786 static inline int pte_same(pte_t a, pte_t b) 787 { 788 return pte_val(a) == pte_val(b); 789 } 790 791 #ifdef CONFIG_NUMA_BALANCING 792 static inline int pte_protnone(pte_t pte) 793 { 794 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 795 } 796 797 static inline int pmd_protnone(pmd_t pmd) 798 { 799 /* pmd_large(pmd) implies pmd_present(pmd) */ 800 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 801 } 802 #endif 803 804 static inline int pte_soft_dirty(pte_t pte) 805 { 806 return pte_val(pte) & _PAGE_SOFT_DIRTY; 807 } 808 #define pte_swp_soft_dirty pte_soft_dirty 809 810 static inline pte_t pte_mksoft_dirty(pte_t pte) 811 { 812 pte_val(pte) |= _PAGE_SOFT_DIRTY; 813 return pte; 814 } 815 #define pte_swp_mksoft_dirty pte_mksoft_dirty 816 817 static inline pte_t pte_clear_soft_dirty(pte_t pte) 818 { 819 pte_val(pte) &= ~_PAGE_SOFT_DIRTY; 820 return pte; 821 } 822 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 823 824 static inline int pmd_soft_dirty(pmd_t pmd) 825 { 826 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 827 } 828 829 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 830 { 831 pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; 832 return pmd; 833 } 834 835 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 836 { 837 pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; 838 return pmd; 839 } 840 841 /* 842 * query functions pte_write/pte_dirty/pte_young only work if 843 * pte_present() is true. Undefined behaviour if not.. 844 */ 845 static inline int pte_write(pte_t pte) 846 { 847 return (pte_val(pte) & _PAGE_WRITE) != 0; 848 } 849 850 static inline int pte_dirty(pte_t pte) 851 { 852 return (pte_val(pte) & _PAGE_DIRTY) != 0; 853 } 854 855 static inline int pte_young(pte_t pte) 856 { 857 return (pte_val(pte) & _PAGE_YOUNG) != 0; 858 } 859 860 #define __HAVE_ARCH_PTE_UNUSED 861 static inline int pte_unused(pte_t pte) 862 { 863 return pte_val(pte) & _PAGE_UNUSED; 864 } 865 866 /* 867 * pgd/pmd/pte modification functions 868 */ 869 870 static inline void pgd_clear(pgd_t *pgd) 871 { 872 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 873 pgd_val(*pgd) = _REGION1_ENTRY_EMPTY; 874 } 875 876 static inline void p4d_clear(p4d_t *p4d) 877 { 878 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 879 p4d_val(*p4d) = _REGION2_ENTRY_EMPTY; 880 } 881 882 static inline void pud_clear(pud_t *pud) 883 { 884 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 885 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 886 } 887 888 static inline void pmd_clear(pmd_t *pmdp) 889 { 890 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; 891 } 892 893 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 894 { 895 pte_val(*ptep) = _PAGE_INVALID; 896 } 897 898 /* 899 * The following pte modification functions only work if 900 * pte_present() is true. Undefined behaviour if not.. 901 */ 902 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 903 { 904 pte_val(pte) &= _PAGE_CHG_MASK; 905 pte_val(pte) |= pgprot_val(newprot); 906 /* 907 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 908 * has the invalid bit set, clear it again for readable, young pages 909 */ 910 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 911 pte_val(pte) &= ~_PAGE_INVALID; 912 /* 913 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 914 * protection bit set, clear it again for writable, dirty pages 915 */ 916 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 917 pte_val(pte) &= ~_PAGE_PROTECT; 918 return pte; 919 } 920 921 static inline pte_t pte_wrprotect(pte_t pte) 922 { 923 pte_val(pte) &= ~_PAGE_WRITE; 924 pte_val(pte) |= _PAGE_PROTECT; 925 return pte; 926 } 927 928 static inline pte_t pte_mkwrite(pte_t pte) 929 { 930 pte_val(pte) |= _PAGE_WRITE; 931 if (pte_val(pte) & _PAGE_DIRTY) 932 pte_val(pte) &= ~_PAGE_PROTECT; 933 return pte; 934 } 935 936 static inline pte_t pte_mkclean(pte_t pte) 937 { 938 pte_val(pte) &= ~_PAGE_DIRTY; 939 pte_val(pte) |= _PAGE_PROTECT; 940 return pte; 941 } 942 943 static inline pte_t pte_mkdirty(pte_t pte) 944 { 945 pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; 946 if (pte_val(pte) & _PAGE_WRITE) 947 pte_val(pte) &= ~_PAGE_PROTECT; 948 return pte; 949 } 950 951 static inline pte_t pte_mkold(pte_t pte) 952 { 953 pte_val(pte) &= ~_PAGE_YOUNG; 954 pte_val(pte) |= _PAGE_INVALID; 955 return pte; 956 } 957 958 static inline pte_t pte_mkyoung(pte_t pte) 959 { 960 pte_val(pte) |= _PAGE_YOUNG; 961 if (pte_val(pte) & _PAGE_READ) 962 pte_val(pte) &= ~_PAGE_INVALID; 963 return pte; 964 } 965 966 static inline pte_t pte_mkspecial(pte_t pte) 967 { 968 pte_val(pte) |= _PAGE_SPECIAL; 969 return pte; 970 } 971 972 #ifdef CONFIG_HUGETLB_PAGE 973 static inline pte_t pte_mkhuge(pte_t pte) 974 { 975 pte_val(pte) |= _PAGE_LARGE; 976 return pte; 977 } 978 #endif 979 980 #define IPTE_GLOBAL 0 981 #define IPTE_LOCAL 1 982 983 #define IPTE_NODAT 0x400 984 #define IPTE_GUEST_ASCE 0x800 985 986 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 987 unsigned long opt, unsigned long asce, 988 int local) 989 { 990 unsigned long pto = (unsigned long) ptep; 991 992 if (__builtin_constant_p(opt) && opt == 0) { 993 /* Invalidation + TLB flush for the pte */ 994 asm volatile( 995 " .insn rrf,0xb2210000,%[r1],%[r2],0,%[m4]" 996 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 997 [m4] "i" (local)); 998 return; 999 } 1000 1001 /* Invalidate ptes with options + TLB flush of the ptes */ 1002 opt = opt | (asce & _ASCE_ORIGIN); 1003 asm volatile( 1004 " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" 1005 : [r2] "+a" (address), [r3] "+a" (opt) 1006 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1007 } 1008 1009 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1010 pte_t *ptep, int local) 1011 { 1012 unsigned long pto = (unsigned long) ptep; 1013 1014 /* Invalidate a range of ptes + TLB flush of the ptes */ 1015 do { 1016 asm volatile( 1017 " .insn rrf,0xb2210000,%[r1],%[r2],%[r3],%[m4]" 1018 : [r2] "+a" (address), [r3] "+a" (nr) 1019 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1020 } while (nr != 255); 1021 } 1022 1023 /* 1024 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1025 * both clear the TLB for the unmapped pte. The reason is that 1026 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1027 * to modify an active pte. The sequence is 1028 * 1) ptep_get_and_clear 1029 * 2) set_pte_at 1030 * 3) flush_tlb_range 1031 * On s390 the tlb needs to get flushed with the modification of the pte 1032 * if the pte is active. The only way how this can be implemented is to 1033 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1034 * is a nop. 1035 */ 1036 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1037 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1038 1039 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1040 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1041 unsigned long addr, pte_t *ptep) 1042 { 1043 pte_t pte = *ptep; 1044 1045 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1046 return pte_young(pte); 1047 } 1048 1049 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1050 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1051 unsigned long address, pte_t *ptep) 1052 { 1053 return ptep_test_and_clear_young(vma, address, ptep); 1054 } 1055 1056 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1057 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1058 unsigned long addr, pte_t *ptep) 1059 { 1060 pte_t res; 1061 1062 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1063 if (mm_is_protected(mm) && pte_present(res)) 1064 uv_convert_from_secure(pte_val(res) & PAGE_MASK); 1065 return res; 1066 } 1067 1068 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1069 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1070 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1071 pte_t *, pte_t, pte_t); 1072 1073 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1074 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1075 unsigned long addr, pte_t *ptep) 1076 { 1077 pte_t res; 1078 1079 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1080 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1081 uv_convert_from_secure(pte_val(res) & PAGE_MASK); 1082 return res; 1083 } 1084 1085 /* 1086 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1087 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1088 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1089 * cannot be accessed while the batched unmap is running. In this case 1090 * full==1 and a simple pte_clear is enough. See tlb.h. 1091 */ 1092 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1093 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1094 unsigned long addr, 1095 pte_t *ptep, int full) 1096 { 1097 pte_t res; 1098 1099 if (full) { 1100 res = *ptep; 1101 *ptep = __pte(_PAGE_INVALID); 1102 } else { 1103 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1104 } 1105 if (mm_is_protected(mm) && pte_present(res)) 1106 uv_convert_from_secure(pte_val(res) & PAGE_MASK); 1107 return res; 1108 } 1109 1110 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1111 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1112 unsigned long addr, pte_t *ptep) 1113 { 1114 pte_t pte = *ptep; 1115 1116 if (pte_write(pte)) 1117 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1118 } 1119 1120 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1121 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1122 unsigned long addr, pte_t *ptep, 1123 pte_t entry, int dirty) 1124 { 1125 if (pte_same(*ptep, entry)) 1126 return 0; 1127 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1128 return 1; 1129 } 1130 1131 /* 1132 * Additional functions to handle KVM guest page tables 1133 */ 1134 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1135 pte_t *ptep, pte_t entry); 1136 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1137 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1138 pte_t *ptep, unsigned long bits); 1139 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1140 pte_t *ptep, int prot, unsigned long bit); 1141 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1142 pte_t *ptep , int reset); 1143 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1144 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1145 pte_t *sptep, pte_t *tptep, pte_t pte); 1146 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1147 1148 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1149 pte_t *ptep); 1150 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1151 unsigned char key, bool nq); 1152 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1153 unsigned char key, unsigned char *oldkey, 1154 bool nq, bool mr, bool mc); 1155 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1156 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1157 unsigned char *key); 1158 1159 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1160 unsigned long bits, unsigned long value); 1161 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1162 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1163 unsigned long *oldpte, unsigned long *oldpgste); 1164 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1165 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1166 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1167 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1168 1169 #define pgprot_writecombine pgprot_writecombine 1170 pgprot_t pgprot_writecombine(pgprot_t prot); 1171 1172 #define pgprot_writethrough pgprot_writethrough 1173 pgprot_t pgprot_writethrough(pgprot_t prot); 1174 1175 /* 1176 * Certain architectures need to do special things when PTEs 1177 * within a page table are directly modified. Thus, the following 1178 * hook is made available. 1179 */ 1180 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 1181 pte_t *ptep, pte_t entry) 1182 { 1183 if (pte_present(entry)) 1184 pte_val(entry) &= ~_PAGE_UNUSED; 1185 if (mm_has_pgste(mm)) 1186 ptep_set_pte_at(mm, addr, ptep, entry); 1187 else 1188 *ptep = entry; 1189 } 1190 1191 /* 1192 * Conversion functions: convert a page and protection to a page entry, 1193 * and a page entry and page directory to the page they refer to. 1194 */ 1195 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1196 { 1197 pte_t __pte; 1198 1199 pte_val(__pte) = physpage | pgprot_val(pgprot); 1200 if (!MACHINE_HAS_NX) 1201 pte_val(__pte) &= ~_PAGE_NOEXEC; 1202 return pte_mkyoung(__pte); 1203 } 1204 1205 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1206 { 1207 unsigned long physpage = page_to_phys(page); 1208 pte_t __pte = mk_pte_phys(physpage, pgprot); 1209 1210 if (pte_write(__pte) && PageDirty(page)) 1211 __pte = pte_mkdirty(__pte); 1212 return __pte; 1213 } 1214 1215 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1216 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1217 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1218 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1219 1220 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1221 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1222 1223 static inline unsigned long pmd_deref(pmd_t pmd) 1224 { 1225 unsigned long origin_mask; 1226 1227 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1228 if (pmd_large(pmd)) 1229 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1230 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1231 } 1232 1233 static inline unsigned long pmd_pfn(pmd_t pmd) 1234 { 1235 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1236 } 1237 1238 static inline unsigned long pud_deref(pud_t pud) 1239 { 1240 unsigned long origin_mask; 1241 1242 origin_mask = _REGION_ENTRY_ORIGIN; 1243 if (pud_large(pud)) 1244 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1245 return (unsigned long)__va(pud_val(pud) & origin_mask); 1246 } 1247 1248 static inline unsigned long pud_pfn(pud_t pud) 1249 { 1250 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1251 } 1252 1253 /* 1254 * The pgd_offset function *always* adds the index for the top-level 1255 * region/segment table. This is done to get a sequence like the 1256 * following to work: 1257 * pgdp = pgd_offset(current->mm, addr); 1258 * pgd = READ_ONCE(*pgdp); 1259 * p4dp = p4d_offset(&pgd, addr); 1260 * ... 1261 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1262 * only add an index if they dereferenced the pointer. 1263 */ 1264 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1265 { 1266 unsigned long rste; 1267 unsigned int shift; 1268 1269 /* Get the first entry of the top level table */ 1270 rste = pgd_val(*pgd); 1271 /* Pick up the shift from the table type of the first entry */ 1272 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1273 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1274 } 1275 1276 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1277 1278 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1279 { 1280 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1281 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1282 return (p4d_t *) pgdp; 1283 } 1284 #define p4d_offset_lockless p4d_offset_lockless 1285 1286 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1287 { 1288 return p4d_offset_lockless(pgdp, *pgdp, address); 1289 } 1290 1291 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1292 { 1293 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1294 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1295 return (pud_t *) p4dp; 1296 } 1297 #define pud_offset_lockless pud_offset_lockless 1298 1299 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1300 { 1301 return pud_offset_lockless(p4dp, *p4dp, address); 1302 } 1303 #define pud_offset pud_offset 1304 1305 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1306 { 1307 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1308 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1309 return (pmd_t *) pudp; 1310 } 1311 #define pmd_offset_lockless pmd_offset_lockless 1312 1313 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1314 { 1315 return pmd_offset_lockless(pudp, *pudp, address); 1316 } 1317 #define pmd_offset pmd_offset 1318 1319 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1320 { 1321 return (unsigned long) pmd_deref(pmd); 1322 } 1323 1324 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1325 { 1326 return end <= current->mm->context.asce_limit; 1327 } 1328 #define gup_fast_permitted gup_fast_permitted 1329 1330 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1331 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1332 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1333 1334 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1335 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1336 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1337 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1338 1339 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1340 { 1341 pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; 1342 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1343 return pmd; 1344 } 1345 1346 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1347 { 1348 pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; 1349 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1350 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1351 return pmd; 1352 } 1353 1354 static inline pmd_t pmd_mkclean(pmd_t pmd) 1355 { 1356 pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; 1357 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1358 return pmd; 1359 } 1360 1361 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1362 { 1363 pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY; 1364 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1365 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; 1366 return pmd; 1367 } 1368 1369 static inline pud_t pud_wrprotect(pud_t pud) 1370 { 1371 pud_val(pud) &= ~_REGION3_ENTRY_WRITE; 1372 pud_val(pud) |= _REGION_ENTRY_PROTECT; 1373 return pud; 1374 } 1375 1376 static inline pud_t pud_mkwrite(pud_t pud) 1377 { 1378 pud_val(pud) |= _REGION3_ENTRY_WRITE; 1379 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1380 pud_val(pud) &= ~_REGION_ENTRY_PROTECT; 1381 return pud; 1382 } 1383 1384 static inline pud_t pud_mkclean(pud_t pud) 1385 { 1386 pud_val(pud) &= ~_REGION3_ENTRY_DIRTY; 1387 pud_val(pud) |= _REGION_ENTRY_PROTECT; 1388 return pud; 1389 } 1390 1391 static inline pud_t pud_mkdirty(pud_t pud) 1392 { 1393 pud_val(pud) |= _REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY; 1394 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1395 pud_val(pud) &= ~_REGION_ENTRY_PROTECT; 1396 return pud; 1397 } 1398 1399 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1400 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1401 { 1402 /* 1403 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1404 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1405 */ 1406 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1407 return pgprot_val(SEGMENT_NONE); 1408 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1409 return pgprot_val(SEGMENT_RO); 1410 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1411 return pgprot_val(SEGMENT_RX); 1412 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1413 return pgprot_val(SEGMENT_RW); 1414 return pgprot_val(SEGMENT_RWX); 1415 } 1416 1417 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1418 { 1419 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1420 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1421 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; 1422 return pmd; 1423 } 1424 1425 static inline pmd_t pmd_mkold(pmd_t pmd) 1426 { 1427 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; 1428 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1429 return pmd; 1430 } 1431 1432 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1433 { 1434 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | 1435 _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | 1436 _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SOFT_DIRTY; 1437 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1438 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1439 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1440 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1441 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; 1442 return pmd; 1443 } 1444 1445 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1446 { 1447 pmd_t __pmd; 1448 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1449 return __pmd; 1450 } 1451 1452 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1453 1454 static inline void __pmdp_csp(pmd_t *pmdp) 1455 { 1456 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1457 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1458 } 1459 1460 #define IDTE_GLOBAL 0 1461 #define IDTE_LOCAL 1 1462 1463 #define IDTE_PTOA 0x0800 1464 #define IDTE_NODAT 0x1000 1465 #define IDTE_GUEST_ASCE 0x2000 1466 1467 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1468 unsigned long opt, unsigned long asce, 1469 int local) 1470 { 1471 unsigned long sto; 1472 1473 sto = (unsigned long) pmdp - pmd_index(addr) * sizeof(pmd_t); 1474 if (__builtin_constant_p(opt) && opt == 0) { 1475 /* flush without guest asce */ 1476 asm volatile( 1477 " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" 1478 : "+m" (*pmdp) 1479 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1480 [m4] "i" (local) 1481 : "cc" ); 1482 } else { 1483 /* flush with guest asce */ 1484 asm volatile( 1485 " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" 1486 : "+m" (*pmdp) 1487 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1488 [r3] "a" (asce), [m4] "i" (local) 1489 : "cc" ); 1490 } 1491 } 1492 1493 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1494 unsigned long opt, unsigned long asce, 1495 int local) 1496 { 1497 unsigned long r3o; 1498 1499 r3o = (unsigned long) pudp - pud_index(addr) * sizeof(pud_t); 1500 r3o |= _ASCE_TYPE_REGION3; 1501 if (__builtin_constant_p(opt) && opt == 0) { 1502 /* flush without guest asce */ 1503 asm volatile( 1504 " .insn rrf,0xb98e0000,%[r1],%[r2],0,%[m4]" 1505 : "+m" (*pudp) 1506 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1507 [m4] "i" (local) 1508 : "cc"); 1509 } else { 1510 /* flush with guest asce */ 1511 asm volatile( 1512 " .insn rrf,0xb98e0000,%[r1],%[r2],%[r3],%[m4]" 1513 : "+m" (*pudp) 1514 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1515 [r3] "a" (asce), [m4] "i" (local) 1516 : "cc" ); 1517 } 1518 } 1519 1520 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1521 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1522 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1523 1524 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1525 1526 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1527 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1528 pgtable_t pgtable); 1529 1530 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1531 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1532 1533 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1534 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1535 unsigned long addr, pmd_t *pmdp, 1536 pmd_t entry, int dirty) 1537 { 1538 VM_BUG_ON(addr & ~HPAGE_MASK); 1539 1540 entry = pmd_mkyoung(entry); 1541 if (dirty) 1542 entry = pmd_mkdirty(entry); 1543 if (pmd_val(*pmdp) == pmd_val(entry)) 1544 return 0; 1545 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1546 return 1; 1547 } 1548 1549 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1550 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1551 unsigned long addr, pmd_t *pmdp) 1552 { 1553 pmd_t pmd = *pmdp; 1554 1555 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1556 return pmd_young(pmd); 1557 } 1558 1559 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1560 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1561 unsigned long addr, pmd_t *pmdp) 1562 { 1563 VM_BUG_ON(addr & ~HPAGE_MASK); 1564 return pmdp_test_and_clear_young(vma, addr, pmdp); 1565 } 1566 1567 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1568 pmd_t *pmdp, pmd_t entry) 1569 { 1570 if (!MACHINE_HAS_NX) 1571 pmd_val(entry) &= ~_SEGMENT_ENTRY_NOEXEC; 1572 *pmdp = entry; 1573 } 1574 1575 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1576 { 1577 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1578 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; 1579 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; 1580 return pmd; 1581 } 1582 1583 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1584 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1585 unsigned long addr, pmd_t *pmdp) 1586 { 1587 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1588 } 1589 1590 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1591 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1592 unsigned long addr, 1593 pmd_t *pmdp, int full) 1594 { 1595 if (full) { 1596 pmd_t pmd = *pmdp; 1597 *pmdp = __pmd(_SEGMENT_ENTRY_EMPTY); 1598 return pmd; 1599 } 1600 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1601 } 1602 1603 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1604 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1605 unsigned long addr, pmd_t *pmdp) 1606 { 1607 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1608 } 1609 1610 #define __HAVE_ARCH_PMDP_INVALIDATE 1611 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1612 unsigned long addr, pmd_t *pmdp) 1613 { 1614 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1615 1616 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1617 } 1618 1619 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1620 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1621 unsigned long addr, pmd_t *pmdp) 1622 { 1623 pmd_t pmd = *pmdp; 1624 1625 if (pmd_write(pmd)) 1626 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1627 } 1628 1629 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1630 unsigned long address, 1631 pmd_t *pmdp) 1632 { 1633 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1634 } 1635 #define pmdp_collapse_flush pmdp_collapse_flush 1636 1637 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1638 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1639 1640 static inline int pmd_trans_huge(pmd_t pmd) 1641 { 1642 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1643 } 1644 1645 #define has_transparent_hugepage has_transparent_hugepage 1646 static inline int has_transparent_hugepage(void) 1647 { 1648 return MACHINE_HAS_EDAT1 ? 1 : 0; 1649 } 1650 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1651 1652 /* 1653 * 64 bit swap entry format: 1654 * A page-table entry has some bits we have to treat in a special way. 1655 * Bits 52 and bit 55 have to be zero, otherwise a specification 1656 * exception will occur instead of a page translation exception. The 1657 * specification exception has the bad habit not to store necessary 1658 * information in the lowcore. 1659 * Bits 54 and 63 are used to indicate the page type. 1660 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1661 * This leaves the bits 0-51 and bits 56-62 to store type and offset. 1662 * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 1663 * for the offset. 1664 * | offset |01100|type |00| 1665 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1666 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1667 */ 1668 1669 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1670 #define __SWP_OFFSET_SHIFT 12 1671 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1672 #define __SWP_TYPE_SHIFT 2 1673 1674 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1675 { 1676 pte_t pte; 1677 1678 pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; 1679 pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1680 pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1681 return pte; 1682 } 1683 1684 static inline unsigned long __swp_type(swp_entry_t entry) 1685 { 1686 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1687 } 1688 1689 static inline unsigned long __swp_offset(swp_entry_t entry) 1690 { 1691 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1692 } 1693 1694 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1695 { 1696 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1697 } 1698 1699 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1700 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1701 1702 #define kern_addr_valid(addr) (1) 1703 1704 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1705 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1706 extern int s390_enable_sie(void); 1707 extern int s390_enable_skey(void); 1708 extern void s390_reset_cmma(struct mm_struct *mm); 1709 1710 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1711 #define HAVE_ARCH_UNMAPPED_AREA 1712 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1713 1714 #endif /* _S390_PAGE_H */ 1715