1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/bug.h> 22 #include <asm/page.h> 23 #include <asm/uv.h> 24 25 extern pgd_t swapper_pg_dir[]; 26 extern pgd_t invalid_pg_dir[]; 27 extern void paging_init(void); 28 extern unsigned long s390_invalid_asce; 29 30 enum { 31 PG_DIRECT_MAP_4K = 0, 32 PG_DIRECT_MAP_1M, 33 PG_DIRECT_MAP_2G, 34 PG_DIRECT_MAP_MAX 35 }; 36 37 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 38 39 static inline void update_page_count(int level, long count) 40 { 41 if (IS_ENABLED(CONFIG_PROC_FS)) 42 atomic_long_add(count, &direct_pages_count[level]); 43 } 44 45 /* 46 * The S390 doesn't have any external MMU info: the kernel page 47 * tables contain all the necessary information. 48 */ 49 #define update_mmu_cache(vma, address, ptep) do { } while (0) 50 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 51 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 52 53 /* 54 * ZERO_PAGE is a global shared page that is always zero; used 55 * for zero-mapped memory areas etc.. 56 */ 57 58 extern unsigned long empty_zero_page; 59 extern unsigned long zero_page_mask; 60 61 #define ZERO_PAGE(vaddr) \ 62 (virt_to_page((void *)(empty_zero_page + \ 63 (((unsigned long)(vaddr)) &zero_page_mask)))) 64 #define __HAVE_COLOR_ZERO_PAGE 65 66 /* TODO: s390 cannot support io_remap_pfn_range... */ 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 70 #define pmd_ERROR(e) \ 71 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 72 #define pud_ERROR(e) \ 73 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 74 #define p4d_ERROR(e) \ 75 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 76 #define pgd_ERROR(e) \ 77 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 78 79 /* 80 * The vmalloc and module area will always be on the topmost area of the 81 * kernel mapping. 512GB are reserved for vmalloc by default. 82 * At the top of the vmalloc area a 2GB area is reserved where modules 83 * will reside. That makes sure that inter module branches always 84 * happen without trampolines and in addition the placement within a 85 * 2GB frame is branch prediction unit friendly. 86 */ 87 extern unsigned long __bootdata_preserved(VMALLOC_START); 88 extern unsigned long __bootdata_preserved(VMALLOC_END); 89 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 90 extern struct page *__bootdata_preserved(vmemmap); 91 extern unsigned long __bootdata_preserved(vmemmap_size); 92 93 extern unsigned long __bootdata_preserved(MODULES_VADDR); 94 extern unsigned long __bootdata_preserved(MODULES_END); 95 #define MODULES_VADDR MODULES_VADDR 96 #define MODULES_END MODULES_END 97 #define MODULES_LEN (1UL << 31) 98 99 static inline int is_module_addr(void *addr) 100 { 101 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 102 if (addr < (void *)MODULES_VADDR) 103 return 0; 104 if (addr > (void *)MODULES_END) 105 return 0; 106 return 1; 107 } 108 109 /* 110 * A 64 bit pagetable entry of S390 has following format: 111 * | PFRA |0IPC| OS | 112 * 0000000000111111111122222222223333333333444444444455555555556666 113 * 0123456789012345678901234567890123456789012345678901234567890123 114 * 115 * I Page-Invalid Bit: Page is not available for address-translation 116 * P Page-Protection Bit: Store access not possible for page 117 * C Change-bit override: HW is not required to set change bit 118 * 119 * A 64 bit segmenttable entry of S390 has following format: 120 * | P-table origin | TT 121 * 0000000000111111111122222222223333333333444444444455555555556666 122 * 0123456789012345678901234567890123456789012345678901234567890123 123 * 124 * I Segment-Invalid Bit: Segment is not available for address-translation 125 * C Common-Segment Bit: Segment is not private (PoP 3-30) 126 * P Page-Protection Bit: Store access not possible for page 127 * TT Type 00 128 * 129 * A 64 bit region table entry of S390 has following format: 130 * | S-table origin | TF TTTL 131 * 0000000000111111111122222222223333333333444444444455555555556666 132 * 0123456789012345678901234567890123456789012345678901234567890123 133 * 134 * I Segment-Invalid Bit: Segment is not available for address-translation 135 * TT Type 01 136 * TF 137 * TL Table length 138 * 139 * The 64 bit regiontable origin of S390 has following format: 140 * | region table origon | DTTL 141 * 0000000000111111111122222222223333333333444444444455555555556666 142 * 0123456789012345678901234567890123456789012345678901234567890123 143 * 144 * X Space-Switch event: 145 * G Segment-Invalid Bit: 146 * P Private-Space Bit: 147 * S Storage-Alteration: 148 * R Real space 149 * TL Table-Length: 150 * 151 * A storage key has the following format: 152 * | ACC |F|R|C|0| 153 * 0 3 4 5 6 7 154 * ACC: access key 155 * F : fetch protection bit 156 * R : referenced bit 157 * C : changed bit 158 */ 159 160 /* Hardware bits in the page table entry */ 161 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 162 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 163 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 164 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 165 166 /* Software bits in the page table entry */ 167 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 168 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 169 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 170 #define _PAGE_READ 0x010 /* SW pte read bit */ 171 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 172 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 173 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 174 175 #ifdef CONFIG_MEM_SOFT_DIRTY 176 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 177 #else 178 #define _PAGE_SOFT_DIRTY 0x000 179 #endif 180 181 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 182 183 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 184 185 /* Set of bits not changed in pte_modify */ 186 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 187 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 188 189 /* 190 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 191 * HW bit and all SW bits. 192 */ 193 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 194 195 /* 196 * handle_pte_fault uses pte_present and pte_none to find out the pte type 197 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 198 * distinguish present from not-present ptes. It is changed only with the page 199 * table lock held. 200 * 201 * The following table gives the different possible bit combinations for 202 * the pte hardware and software bits in the last 12 bits of a pte 203 * (. unassigned bit, x don't care, t swap type): 204 * 205 * 842100000000 206 * 000084210000 207 * 000000008421 208 * .IR.uswrdy.p 209 * empty .10.00000000 210 * swap .11..ttttt.0 211 * prot-none, clean, old .11.xx0000.1 212 * prot-none, clean, young .11.xx0001.1 213 * prot-none, dirty, old .11.xx0010.1 214 * prot-none, dirty, young .11.xx0011.1 215 * read-only, clean, old .11.xx0100.1 216 * read-only, clean, young .01.xx0101.1 217 * read-only, dirty, old .11.xx0110.1 218 * read-only, dirty, young .01.xx0111.1 219 * read-write, clean, old .11.xx1100.1 220 * read-write, clean, young .01.xx1101.1 221 * read-write, dirty, old .10.xx1110.1 222 * read-write, dirty, young .00.xx1111.1 223 * HW-bits: R read-only, I invalid 224 * SW-bits: p present, y young, d dirty, r read, w write, s special, 225 * u unused, l large 226 * 227 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 228 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 229 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 230 */ 231 232 /* Bits in the segment/region table address-space-control-element */ 233 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 234 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 235 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 236 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 237 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 238 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 239 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 240 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 241 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 242 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 243 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 244 245 /* Bits in the region table entry */ 246 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 247 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 248 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 249 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 250 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 251 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 252 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 253 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 254 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 255 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 256 257 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 258 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 259 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 260 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 261 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 262 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 263 264 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 265 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 266 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 267 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 268 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 269 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 270 271 #ifdef CONFIG_MEM_SOFT_DIRTY 272 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 273 #else 274 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 275 #endif 276 277 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 278 279 /* Bits in the segment table entry */ 280 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 281 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 282 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 283 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 284 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 285 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 286 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 287 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 288 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 289 290 #define _SEGMENT_ENTRY (0) 291 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 292 293 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 294 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 295 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 296 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 297 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 298 299 #ifdef CONFIG_MEM_SOFT_DIRTY 300 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 301 #else 302 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 303 #endif 304 305 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 306 #define _PAGE_ENTRIES 256 /* number of page table entries */ 307 308 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 309 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 310 311 #define _REGION1_SHIFT 53 312 #define _REGION2_SHIFT 42 313 #define _REGION3_SHIFT 31 314 #define _SEGMENT_SHIFT 20 315 316 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 317 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 318 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 319 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 320 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 321 322 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 323 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 324 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 325 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 326 327 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 328 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 329 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 330 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 331 332 #define PMD_SHIFT _SEGMENT_SHIFT 333 #define PUD_SHIFT _REGION3_SHIFT 334 #define P4D_SHIFT _REGION2_SHIFT 335 #define PGDIR_SHIFT _REGION1_SHIFT 336 337 #define PMD_SIZE _SEGMENT_SIZE 338 #define PUD_SIZE _REGION3_SIZE 339 #define P4D_SIZE _REGION2_SIZE 340 #define PGDIR_SIZE _REGION1_SIZE 341 342 #define PMD_MASK _SEGMENT_MASK 343 #define PUD_MASK _REGION3_MASK 344 #define P4D_MASK _REGION2_MASK 345 #define PGDIR_MASK _REGION1_MASK 346 347 #define PTRS_PER_PTE _PAGE_ENTRIES 348 #define PTRS_PER_PMD _CRST_ENTRIES 349 #define PTRS_PER_PUD _CRST_ENTRIES 350 #define PTRS_PER_P4D _CRST_ENTRIES 351 #define PTRS_PER_PGD _CRST_ENTRIES 352 353 /* 354 * Segment table and region3 table entry encoding 355 * (R = read-only, I = invalid, y = young bit): 356 * dy..R...I...wr 357 * prot-none, clean, old 00..1...1...00 358 * prot-none, clean, young 01..1...1...00 359 * prot-none, dirty, old 10..1...1...00 360 * prot-none, dirty, young 11..1...1...00 361 * read-only, clean, old 00..1...1...01 362 * read-only, clean, young 01..1...0...01 363 * read-only, dirty, old 10..1...1...01 364 * read-only, dirty, young 11..1...0...01 365 * read-write, clean, old 00..1...1...11 366 * read-write, clean, young 01..1...0...11 367 * read-write, dirty, old 10..0...1...11 368 * read-write, dirty, young 11..0...0...11 369 * The segment table origin is used to distinguish empty (origin==0) from 370 * read-write, old segment table entries (origin!=0) 371 * HW-bits: R read-only, I invalid 372 * SW-bits: y young, d dirty, r read, w write 373 */ 374 375 /* Page status table bits for virtualization */ 376 #define PGSTE_ACC_BITS 0xf000000000000000UL 377 #define PGSTE_FP_BIT 0x0800000000000000UL 378 #define PGSTE_PCL_BIT 0x0080000000000000UL 379 #define PGSTE_HR_BIT 0x0040000000000000UL 380 #define PGSTE_HC_BIT 0x0020000000000000UL 381 #define PGSTE_GR_BIT 0x0004000000000000UL 382 #define PGSTE_GC_BIT 0x0002000000000000UL 383 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 384 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 385 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 386 387 /* Guest Page State used for virtualization */ 388 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 389 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 390 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 391 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 392 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 393 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 394 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 395 396 /* 397 * A user page table pointer has the space-switch-event bit, the 398 * private-space-control bit and the storage-alteration-event-control 399 * bit set. A kernel page table pointer doesn't need them. 400 */ 401 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 402 _ASCE_ALT_EVENT) 403 404 /* 405 * Page protection definitions. 406 */ 407 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 408 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 409 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 410 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 411 _PAGE_INVALID | _PAGE_PROTECT) 412 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 413 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 414 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 415 _PAGE_INVALID | _PAGE_PROTECT) 416 417 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 418 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 419 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 420 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 421 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 422 _PAGE_PROTECT | _PAGE_NOEXEC) 423 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 424 _PAGE_YOUNG | _PAGE_DIRTY) 425 426 /* 427 * On s390 the page table entry has an invalid bit and a read-only bit. 428 * Read permission implies execute permission and write permission 429 * implies read permission. 430 */ 431 /*xwr*/ 432 433 /* 434 * Segment entry (large page) protection definitions. 435 */ 436 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 437 _SEGMENT_ENTRY_PROTECT) 438 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 439 _SEGMENT_ENTRY_READ | \ 440 _SEGMENT_ENTRY_NOEXEC) 441 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 442 _SEGMENT_ENTRY_READ) 443 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 444 _SEGMENT_ENTRY_WRITE | \ 445 _SEGMENT_ENTRY_NOEXEC) 446 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 447 _SEGMENT_ENTRY_WRITE) 448 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 449 _SEGMENT_ENTRY_LARGE | \ 450 _SEGMENT_ENTRY_READ | \ 451 _SEGMENT_ENTRY_WRITE | \ 452 _SEGMENT_ENTRY_YOUNG | \ 453 _SEGMENT_ENTRY_DIRTY | \ 454 _SEGMENT_ENTRY_NOEXEC) 455 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 456 _SEGMENT_ENTRY_LARGE | \ 457 _SEGMENT_ENTRY_READ | \ 458 _SEGMENT_ENTRY_YOUNG | \ 459 _SEGMENT_ENTRY_PROTECT | \ 460 _SEGMENT_ENTRY_NOEXEC) 461 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 462 _SEGMENT_ENTRY_LARGE | \ 463 _SEGMENT_ENTRY_READ | \ 464 _SEGMENT_ENTRY_WRITE | \ 465 _SEGMENT_ENTRY_YOUNG | \ 466 _SEGMENT_ENTRY_DIRTY) 467 468 /* 469 * Region3 entry (large page) protection definitions. 470 */ 471 472 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 473 _REGION3_ENTRY_LARGE | \ 474 _REGION3_ENTRY_READ | \ 475 _REGION3_ENTRY_WRITE | \ 476 _REGION3_ENTRY_YOUNG | \ 477 _REGION3_ENTRY_DIRTY | \ 478 _REGION_ENTRY_NOEXEC) 479 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 480 _REGION3_ENTRY_LARGE | \ 481 _REGION3_ENTRY_READ | \ 482 _REGION3_ENTRY_YOUNG | \ 483 _REGION_ENTRY_PROTECT | \ 484 _REGION_ENTRY_NOEXEC) 485 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 486 _REGION3_ENTRY_LARGE | \ 487 _REGION3_ENTRY_READ | \ 488 _REGION3_ENTRY_WRITE | \ 489 _REGION3_ENTRY_YOUNG | \ 490 _REGION3_ENTRY_DIRTY) 491 492 static inline bool mm_p4d_folded(struct mm_struct *mm) 493 { 494 return mm->context.asce_limit <= _REGION1_SIZE; 495 } 496 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 497 498 static inline bool mm_pud_folded(struct mm_struct *mm) 499 { 500 return mm->context.asce_limit <= _REGION2_SIZE; 501 } 502 #define mm_pud_folded(mm) mm_pud_folded(mm) 503 504 static inline bool mm_pmd_folded(struct mm_struct *mm) 505 { 506 return mm->context.asce_limit <= _REGION3_SIZE; 507 } 508 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 509 510 static inline int mm_has_pgste(struct mm_struct *mm) 511 { 512 #ifdef CONFIG_PGSTE 513 if (unlikely(mm->context.has_pgste)) 514 return 1; 515 #endif 516 return 0; 517 } 518 519 static inline int mm_is_protected(struct mm_struct *mm) 520 { 521 #ifdef CONFIG_PGSTE 522 if (unlikely(atomic_read(&mm->context.protected_count))) 523 return 1; 524 #endif 525 return 0; 526 } 527 528 static inline int mm_alloc_pgste(struct mm_struct *mm) 529 { 530 #ifdef CONFIG_PGSTE 531 if (unlikely(mm->context.alloc_pgste)) 532 return 1; 533 #endif 534 return 0; 535 } 536 537 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 538 { 539 return __pte(pte_val(pte) & ~pgprot_val(prot)); 540 } 541 542 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 543 { 544 return __pte(pte_val(pte) | pgprot_val(prot)); 545 } 546 547 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 548 { 549 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 550 } 551 552 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 553 { 554 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 555 } 556 557 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 558 { 559 return __pud(pud_val(pud) & ~pgprot_val(prot)); 560 } 561 562 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 563 { 564 return __pud(pud_val(pud) | pgprot_val(prot)); 565 } 566 567 /* 568 * In the case that a guest uses storage keys 569 * faults should no longer be backed by zero pages 570 */ 571 #define mm_forbids_zeropage mm_has_pgste 572 static inline int mm_uses_skeys(struct mm_struct *mm) 573 { 574 #ifdef CONFIG_PGSTE 575 if (mm->context.uses_skeys) 576 return 1; 577 #endif 578 return 0; 579 } 580 581 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 582 { 583 union register_pair r1 = { .even = old, .odd = new, }; 584 unsigned long address = (unsigned long)ptr | 1; 585 586 asm volatile( 587 " csp %[r1],%[address]" 588 : [r1] "+&d" (r1.pair), "+m" (*ptr) 589 : [address] "d" (address) 590 : "cc"); 591 } 592 593 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 594 { 595 union register_pair r1 = { .even = old, .odd = new, }; 596 unsigned long address = (unsigned long)ptr | 1; 597 598 asm volatile( 599 " cspg %[r1],%[address]" 600 : [r1] "+&d" (r1.pair), "+m" (*ptr) 601 : [address] "d" (address) 602 : "cc"); 603 } 604 605 #define CRDTE_DTT_PAGE 0x00UL 606 #define CRDTE_DTT_SEGMENT 0x10UL 607 #define CRDTE_DTT_REGION3 0x14UL 608 #define CRDTE_DTT_REGION2 0x18UL 609 #define CRDTE_DTT_REGION1 0x1cUL 610 611 static inline void crdte(unsigned long old, unsigned long new, 612 unsigned long *table, unsigned long dtt, 613 unsigned long address, unsigned long asce) 614 { 615 union register_pair r1 = { .even = old, .odd = new, }; 616 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 617 618 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 619 : [r1] "+&d" (r1.pair) 620 : [r2] "d" (r2.pair), [asce] "a" (asce) 621 : "memory", "cc"); 622 } 623 624 /* 625 * pgd/p4d/pud/pmd/pte query functions 626 */ 627 static inline int pgd_folded(pgd_t pgd) 628 { 629 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 630 } 631 632 static inline int pgd_present(pgd_t pgd) 633 { 634 if (pgd_folded(pgd)) 635 return 1; 636 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 637 } 638 639 static inline int pgd_none(pgd_t pgd) 640 { 641 if (pgd_folded(pgd)) 642 return 0; 643 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 644 } 645 646 static inline int pgd_bad(pgd_t pgd) 647 { 648 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 649 return 0; 650 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 651 } 652 653 static inline unsigned long pgd_pfn(pgd_t pgd) 654 { 655 unsigned long origin_mask; 656 657 origin_mask = _REGION_ENTRY_ORIGIN; 658 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 659 } 660 661 static inline int p4d_folded(p4d_t p4d) 662 { 663 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 664 } 665 666 static inline int p4d_present(p4d_t p4d) 667 { 668 if (p4d_folded(p4d)) 669 return 1; 670 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 671 } 672 673 static inline int p4d_none(p4d_t p4d) 674 { 675 if (p4d_folded(p4d)) 676 return 0; 677 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 678 } 679 680 static inline unsigned long p4d_pfn(p4d_t p4d) 681 { 682 unsigned long origin_mask; 683 684 origin_mask = _REGION_ENTRY_ORIGIN; 685 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 686 } 687 688 static inline int pud_folded(pud_t pud) 689 { 690 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 691 } 692 693 static inline int pud_present(pud_t pud) 694 { 695 if (pud_folded(pud)) 696 return 1; 697 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 698 } 699 700 static inline int pud_none(pud_t pud) 701 { 702 if (pud_folded(pud)) 703 return 0; 704 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 705 } 706 707 #define pud_leaf pud_large 708 static inline int pud_large(pud_t pud) 709 { 710 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 711 return 0; 712 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 713 } 714 715 #define pmd_leaf pmd_large 716 static inline int pmd_large(pmd_t pmd) 717 { 718 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 719 } 720 721 static inline int pmd_bad(pmd_t pmd) 722 { 723 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd)) 724 return 1; 725 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 726 } 727 728 static inline int pud_bad(pud_t pud) 729 { 730 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 731 732 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud)) 733 return 1; 734 if (type < _REGION_ENTRY_TYPE_R3) 735 return 0; 736 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 737 } 738 739 static inline int p4d_bad(p4d_t p4d) 740 { 741 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 742 743 if (type > _REGION_ENTRY_TYPE_R2) 744 return 1; 745 if (type < _REGION_ENTRY_TYPE_R2) 746 return 0; 747 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 748 } 749 750 static inline int pmd_present(pmd_t pmd) 751 { 752 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 753 } 754 755 static inline int pmd_none(pmd_t pmd) 756 { 757 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 758 } 759 760 #define pmd_write pmd_write 761 static inline int pmd_write(pmd_t pmd) 762 { 763 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 764 } 765 766 #define pud_write pud_write 767 static inline int pud_write(pud_t pud) 768 { 769 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 770 } 771 772 static inline int pmd_dirty(pmd_t pmd) 773 { 774 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 775 } 776 777 #define pmd_young pmd_young 778 static inline int pmd_young(pmd_t pmd) 779 { 780 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 781 } 782 783 static inline int pte_present(pte_t pte) 784 { 785 /* Bit pattern: (pte & 0x001) == 0x001 */ 786 return (pte_val(pte) & _PAGE_PRESENT) != 0; 787 } 788 789 static inline int pte_none(pte_t pte) 790 { 791 /* Bit pattern: pte == 0x400 */ 792 return pte_val(pte) == _PAGE_INVALID; 793 } 794 795 static inline int pte_swap(pte_t pte) 796 { 797 /* Bit pattern: (pte & 0x201) == 0x200 */ 798 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 799 == _PAGE_PROTECT; 800 } 801 802 static inline int pte_special(pte_t pte) 803 { 804 return (pte_val(pte) & _PAGE_SPECIAL); 805 } 806 807 #define __HAVE_ARCH_PTE_SAME 808 static inline int pte_same(pte_t a, pte_t b) 809 { 810 return pte_val(a) == pte_val(b); 811 } 812 813 #ifdef CONFIG_NUMA_BALANCING 814 static inline int pte_protnone(pte_t pte) 815 { 816 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 817 } 818 819 static inline int pmd_protnone(pmd_t pmd) 820 { 821 /* pmd_large(pmd) implies pmd_present(pmd) */ 822 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 823 } 824 #endif 825 826 static inline int pte_swp_exclusive(pte_t pte) 827 { 828 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 829 } 830 831 static inline pte_t pte_swp_mkexclusive(pte_t pte) 832 { 833 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 834 } 835 836 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 837 { 838 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 839 } 840 841 static inline int pte_soft_dirty(pte_t pte) 842 { 843 return pte_val(pte) & _PAGE_SOFT_DIRTY; 844 } 845 #define pte_swp_soft_dirty pte_soft_dirty 846 847 static inline pte_t pte_mksoft_dirty(pte_t pte) 848 { 849 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 850 } 851 #define pte_swp_mksoft_dirty pte_mksoft_dirty 852 853 static inline pte_t pte_clear_soft_dirty(pte_t pte) 854 { 855 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 856 } 857 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 858 859 static inline int pmd_soft_dirty(pmd_t pmd) 860 { 861 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 862 } 863 864 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 865 { 866 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 867 } 868 869 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 870 { 871 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 872 } 873 874 /* 875 * query functions pte_write/pte_dirty/pte_young only work if 876 * pte_present() is true. Undefined behaviour if not.. 877 */ 878 static inline int pte_write(pte_t pte) 879 { 880 return (pte_val(pte) & _PAGE_WRITE) != 0; 881 } 882 883 static inline int pte_dirty(pte_t pte) 884 { 885 return (pte_val(pte) & _PAGE_DIRTY) != 0; 886 } 887 888 static inline int pte_young(pte_t pte) 889 { 890 return (pte_val(pte) & _PAGE_YOUNG) != 0; 891 } 892 893 #define __HAVE_ARCH_PTE_UNUSED 894 static inline int pte_unused(pte_t pte) 895 { 896 return pte_val(pte) & _PAGE_UNUSED; 897 } 898 899 /* 900 * Extract the pgprot value from the given pte while at the same time making it 901 * usable for kernel address space mappings where fault driven dirty and 902 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 903 * must not be set. 904 */ 905 static inline pgprot_t pte_pgprot(pte_t pte) 906 { 907 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 908 909 if (pte_write(pte)) 910 pte_flags |= pgprot_val(PAGE_KERNEL); 911 else 912 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 913 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 914 915 return __pgprot(pte_flags); 916 } 917 918 /* 919 * pgd/pmd/pte modification functions 920 */ 921 922 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 923 { 924 WRITE_ONCE(*pgdp, pgd); 925 } 926 927 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 928 { 929 WRITE_ONCE(*p4dp, p4d); 930 } 931 932 static inline void set_pud(pud_t *pudp, pud_t pud) 933 { 934 WRITE_ONCE(*pudp, pud); 935 } 936 937 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 938 { 939 WRITE_ONCE(*pmdp, pmd); 940 } 941 942 static inline void set_pte(pte_t *ptep, pte_t pte) 943 { 944 WRITE_ONCE(*ptep, pte); 945 } 946 947 static inline void pgd_clear(pgd_t *pgd) 948 { 949 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 950 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 951 } 952 953 static inline void p4d_clear(p4d_t *p4d) 954 { 955 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 956 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 957 } 958 959 static inline void pud_clear(pud_t *pud) 960 { 961 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 962 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 963 } 964 965 static inline void pmd_clear(pmd_t *pmdp) 966 { 967 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 968 } 969 970 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 971 { 972 set_pte(ptep, __pte(_PAGE_INVALID)); 973 } 974 975 /* 976 * The following pte modification functions only work if 977 * pte_present() is true. Undefined behaviour if not.. 978 */ 979 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 980 { 981 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 982 pte = set_pte_bit(pte, newprot); 983 /* 984 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 985 * has the invalid bit set, clear it again for readable, young pages 986 */ 987 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 988 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 989 /* 990 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 991 * protection bit set, clear it again for writable, dirty pages 992 */ 993 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 994 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 995 return pte; 996 } 997 998 static inline pte_t pte_wrprotect(pte_t pte) 999 { 1000 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1001 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1002 } 1003 1004 static inline pte_t pte_mkwrite_novma(pte_t pte) 1005 { 1006 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1007 if (pte_val(pte) & _PAGE_DIRTY) 1008 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1009 return pte; 1010 } 1011 1012 static inline pte_t pte_mkclean(pte_t pte) 1013 { 1014 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1015 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1016 } 1017 1018 static inline pte_t pte_mkdirty(pte_t pte) 1019 { 1020 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1021 if (pte_val(pte) & _PAGE_WRITE) 1022 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1023 return pte; 1024 } 1025 1026 static inline pte_t pte_mkold(pte_t pte) 1027 { 1028 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1029 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1030 } 1031 1032 static inline pte_t pte_mkyoung(pte_t pte) 1033 { 1034 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1035 if (pte_val(pte) & _PAGE_READ) 1036 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1037 return pte; 1038 } 1039 1040 static inline pte_t pte_mkspecial(pte_t pte) 1041 { 1042 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1043 } 1044 1045 #ifdef CONFIG_HUGETLB_PAGE 1046 static inline pte_t pte_mkhuge(pte_t pte) 1047 { 1048 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1049 } 1050 #endif 1051 1052 #define IPTE_GLOBAL 0 1053 #define IPTE_LOCAL 1 1054 1055 #define IPTE_NODAT 0x400 1056 #define IPTE_GUEST_ASCE 0x800 1057 1058 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1059 unsigned long opt, unsigned long asce, 1060 int local) 1061 { 1062 unsigned long pto; 1063 1064 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1065 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1066 : "+m" (*ptep) 1067 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1068 [asce] "a" (asce), [m4] "i" (local)); 1069 } 1070 1071 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1072 unsigned long opt, unsigned long asce, 1073 int local) 1074 { 1075 unsigned long pto = __pa(ptep); 1076 1077 if (__builtin_constant_p(opt) && opt == 0) { 1078 /* Invalidation + TLB flush for the pte */ 1079 asm volatile( 1080 " ipte %[r1],%[r2],0,%[m4]" 1081 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1082 [m4] "i" (local)); 1083 return; 1084 } 1085 1086 /* Invalidate ptes with options + TLB flush of the ptes */ 1087 opt = opt | (asce & _ASCE_ORIGIN); 1088 asm volatile( 1089 " ipte %[r1],%[r2],%[r3],%[m4]" 1090 : [r2] "+a" (address), [r3] "+a" (opt) 1091 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1092 } 1093 1094 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1095 pte_t *ptep, int local) 1096 { 1097 unsigned long pto = __pa(ptep); 1098 1099 /* Invalidate a range of ptes + TLB flush of the ptes */ 1100 do { 1101 asm volatile( 1102 " ipte %[r1],%[r2],%[r3],%[m4]" 1103 : [r2] "+a" (address), [r3] "+a" (nr) 1104 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1105 } while (nr != 255); 1106 } 1107 1108 /* 1109 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1110 * both clear the TLB for the unmapped pte. The reason is that 1111 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1112 * to modify an active pte. The sequence is 1113 * 1) ptep_get_and_clear 1114 * 2) set_pte_at 1115 * 3) flush_tlb_range 1116 * On s390 the tlb needs to get flushed with the modification of the pte 1117 * if the pte is active. The only way how this can be implemented is to 1118 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1119 * is a nop. 1120 */ 1121 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1122 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1123 1124 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1125 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1126 unsigned long addr, pte_t *ptep) 1127 { 1128 pte_t pte = *ptep; 1129 1130 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1131 return pte_young(pte); 1132 } 1133 1134 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1135 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1136 unsigned long address, pte_t *ptep) 1137 { 1138 return ptep_test_and_clear_young(vma, address, ptep); 1139 } 1140 1141 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1142 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1143 unsigned long addr, pte_t *ptep) 1144 { 1145 pte_t res; 1146 1147 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1148 /* At this point the reference through the mapping is still present */ 1149 if (mm_is_protected(mm) && pte_present(res)) 1150 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1151 return res; 1152 } 1153 1154 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1155 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1156 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1157 pte_t *, pte_t, pte_t); 1158 1159 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1160 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1161 unsigned long addr, pte_t *ptep) 1162 { 1163 pte_t res; 1164 1165 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1166 /* At this point the reference through the mapping is still present */ 1167 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1168 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1169 return res; 1170 } 1171 1172 /* 1173 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1174 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1175 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1176 * cannot be accessed while the batched unmap is running. In this case 1177 * full==1 and a simple pte_clear is enough. See tlb.h. 1178 */ 1179 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1180 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1181 unsigned long addr, 1182 pte_t *ptep, int full) 1183 { 1184 pte_t res; 1185 1186 if (full) { 1187 res = *ptep; 1188 set_pte(ptep, __pte(_PAGE_INVALID)); 1189 } else { 1190 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1191 } 1192 /* Nothing to do */ 1193 if (!mm_is_protected(mm) || !pte_present(res)) 1194 return res; 1195 /* 1196 * At this point the reference through the mapping is still present. 1197 * The notifier should have destroyed all protected vCPUs at this 1198 * point, so the destroy should be successful. 1199 */ 1200 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1201 return res; 1202 /* 1203 * If something went wrong and the page could not be destroyed, or 1204 * if this is not a mm teardown, the slower export is used as 1205 * fallback instead. 1206 */ 1207 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1208 return res; 1209 } 1210 1211 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1212 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1213 unsigned long addr, pte_t *ptep) 1214 { 1215 pte_t pte = *ptep; 1216 1217 if (pte_write(pte)) 1218 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1219 } 1220 1221 /* 1222 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1223 * bits in the comparison. Those might change e.g. because of dirty and young 1224 * tracking. 1225 */ 1226 static inline int pte_allow_rdp(pte_t old, pte_t new) 1227 { 1228 /* 1229 * Only allow changes from RO to RW 1230 */ 1231 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1232 return 0; 1233 1234 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1235 } 1236 1237 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1238 unsigned long address, 1239 pte_t *ptep) 1240 { 1241 /* 1242 * RDP might not have propagated the PTE protection reset to all CPUs, 1243 * so there could be spurious TLB protection faults. 1244 * NOTE: This will also be called when a racing pagetable update on 1245 * another thread already installed the correct PTE. Both cases cannot 1246 * really be distinguished. 1247 * Therefore, only do the local TLB flush when RDP can be used, and the 1248 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1249 * A local RDP can be used to do the flush. 1250 */ 1251 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1252 __ptep_rdp(address, ptep, 0, 0, 1); 1253 } 1254 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1255 1256 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1257 pte_t new); 1258 1259 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1260 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1261 unsigned long addr, pte_t *ptep, 1262 pte_t entry, int dirty) 1263 { 1264 if (pte_same(*ptep, entry)) 1265 return 0; 1266 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1267 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1268 else 1269 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1270 return 1; 1271 } 1272 1273 /* 1274 * Additional functions to handle KVM guest page tables 1275 */ 1276 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1277 pte_t *ptep, pte_t entry); 1278 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1279 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1280 pte_t *ptep, unsigned long bits); 1281 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1282 pte_t *ptep, int prot, unsigned long bit); 1283 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1284 pte_t *ptep , int reset); 1285 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1286 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1287 pte_t *sptep, pte_t *tptep, pte_t pte); 1288 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1289 1290 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1291 pte_t *ptep); 1292 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1293 unsigned char key, bool nq); 1294 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1295 unsigned char key, unsigned char *oldkey, 1296 bool nq, bool mr, bool mc); 1297 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1298 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1299 unsigned char *key); 1300 1301 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1302 unsigned long bits, unsigned long value); 1303 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1304 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1305 unsigned long *oldpte, unsigned long *oldpgste); 1306 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1307 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1308 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1309 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1310 1311 #define pgprot_writecombine pgprot_writecombine 1312 pgprot_t pgprot_writecombine(pgprot_t prot); 1313 1314 #define pgprot_writethrough pgprot_writethrough 1315 pgprot_t pgprot_writethrough(pgprot_t prot); 1316 1317 /* 1318 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1319 * are within the same folio, PMD and VMA. 1320 */ 1321 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1322 pte_t *ptep, pte_t entry, unsigned int nr) 1323 { 1324 if (pte_present(entry)) 1325 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1326 if (mm_has_pgste(mm)) { 1327 for (;;) { 1328 ptep_set_pte_at(mm, addr, ptep, entry); 1329 if (--nr == 0) 1330 break; 1331 ptep++; 1332 entry = __pte(pte_val(entry) + PAGE_SIZE); 1333 addr += PAGE_SIZE; 1334 } 1335 } else { 1336 for (;;) { 1337 set_pte(ptep, entry); 1338 if (--nr == 0) 1339 break; 1340 ptep++; 1341 entry = __pte(pte_val(entry) + PAGE_SIZE); 1342 } 1343 } 1344 } 1345 #define set_ptes set_ptes 1346 1347 /* 1348 * Conversion functions: convert a page and protection to a page entry, 1349 * and a page entry and page directory to the page they refer to. 1350 */ 1351 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1352 { 1353 pte_t __pte; 1354 1355 __pte = __pte(physpage | pgprot_val(pgprot)); 1356 if (!MACHINE_HAS_NX) 1357 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1358 return pte_mkyoung(__pte); 1359 } 1360 1361 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1362 { 1363 unsigned long physpage = page_to_phys(page); 1364 pte_t __pte = mk_pte_phys(physpage, pgprot); 1365 1366 if (pte_write(__pte) && PageDirty(page)) 1367 __pte = pte_mkdirty(__pte); 1368 return __pte; 1369 } 1370 1371 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1372 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1373 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1374 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1375 1376 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1377 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1378 1379 static inline unsigned long pmd_deref(pmd_t pmd) 1380 { 1381 unsigned long origin_mask; 1382 1383 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1384 if (pmd_large(pmd)) 1385 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1386 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1387 } 1388 1389 static inline unsigned long pmd_pfn(pmd_t pmd) 1390 { 1391 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1392 } 1393 1394 static inline unsigned long pud_deref(pud_t pud) 1395 { 1396 unsigned long origin_mask; 1397 1398 origin_mask = _REGION_ENTRY_ORIGIN; 1399 if (pud_large(pud)) 1400 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1401 return (unsigned long)__va(pud_val(pud) & origin_mask); 1402 } 1403 1404 static inline unsigned long pud_pfn(pud_t pud) 1405 { 1406 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1407 } 1408 1409 /* 1410 * The pgd_offset function *always* adds the index for the top-level 1411 * region/segment table. This is done to get a sequence like the 1412 * following to work: 1413 * pgdp = pgd_offset(current->mm, addr); 1414 * pgd = READ_ONCE(*pgdp); 1415 * p4dp = p4d_offset(&pgd, addr); 1416 * ... 1417 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1418 * only add an index if they dereferenced the pointer. 1419 */ 1420 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1421 { 1422 unsigned long rste; 1423 unsigned int shift; 1424 1425 /* Get the first entry of the top level table */ 1426 rste = pgd_val(*pgd); 1427 /* Pick up the shift from the table type of the first entry */ 1428 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1429 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1430 } 1431 1432 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1433 1434 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1435 { 1436 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1437 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1438 return (p4d_t *) pgdp; 1439 } 1440 #define p4d_offset_lockless p4d_offset_lockless 1441 1442 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1443 { 1444 return p4d_offset_lockless(pgdp, *pgdp, address); 1445 } 1446 1447 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1448 { 1449 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1450 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1451 return (pud_t *) p4dp; 1452 } 1453 #define pud_offset_lockless pud_offset_lockless 1454 1455 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1456 { 1457 return pud_offset_lockless(p4dp, *p4dp, address); 1458 } 1459 #define pud_offset pud_offset 1460 1461 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1462 { 1463 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1464 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1465 return (pmd_t *) pudp; 1466 } 1467 #define pmd_offset_lockless pmd_offset_lockless 1468 1469 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1470 { 1471 return pmd_offset_lockless(pudp, *pudp, address); 1472 } 1473 #define pmd_offset pmd_offset 1474 1475 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1476 { 1477 return (unsigned long) pmd_deref(pmd); 1478 } 1479 1480 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1481 { 1482 return end <= current->mm->context.asce_limit; 1483 } 1484 #define gup_fast_permitted gup_fast_permitted 1485 1486 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1487 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1488 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1489 1490 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1491 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1492 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1493 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1494 1495 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1496 { 1497 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1498 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1499 } 1500 1501 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1502 { 1503 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1504 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1505 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1506 return pmd; 1507 } 1508 1509 static inline pmd_t pmd_mkclean(pmd_t pmd) 1510 { 1511 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1512 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1513 } 1514 1515 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1516 { 1517 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1518 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1519 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1520 return pmd; 1521 } 1522 1523 static inline pud_t pud_wrprotect(pud_t pud) 1524 { 1525 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1526 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1527 } 1528 1529 static inline pud_t pud_mkwrite(pud_t pud) 1530 { 1531 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1532 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1533 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1534 return pud; 1535 } 1536 1537 static inline pud_t pud_mkclean(pud_t pud) 1538 { 1539 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1540 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1541 } 1542 1543 static inline pud_t pud_mkdirty(pud_t pud) 1544 { 1545 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1546 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1547 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1548 return pud; 1549 } 1550 1551 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1552 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1553 { 1554 /* 1555 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1556 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1557 */ 1558 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1559 return pgprot_val(SEGMENT_NONE); 1560 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1561 return pgprot_val(SEGMENT_RO); 1562 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1563 return pgprot_val(SEGMENT_RX); 1564 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1565 return pgprot_val(SEGMENT_RW); 1566 return pgprot_val(SEGMENT_RWX); 1567 } 1568 1569 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1570 { 1571 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1572 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1573 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1574 return pmd; 1575 } 1576 1577 static inline pmd_t pmd_mkold(pmd_t pmd) 1578 { 1579 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1580 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1581 } 1582 1583 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1584 { 1585 unsigned long mask; 1586 1587 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1588 mask |= _SEGMENT_ENTRY_DIRTY; 1589 mask |= _SEGMENT_ENTRY_YOUNG; 1590 mask |= _SEGMENT_ENTRY_LARGE; 1591 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1592 pmd = __pmd(pmd_val(pmd) & mask); 1593 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1594 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1595 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1596 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1597 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1598 return pmd; 1599 } 1600 1601 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1602 { 1603 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1604 } 1605 1606 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1607 1608 static inline void __pmdp_csp(pmd_t *pmdp) 1609 { 1610 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1611 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1612 } 1613 1614 #define IDTE_GLOBAL 0 1615 #define IDTE_LOCAL 1 1616 1617 #define IDTE_PTOA 0x0800 1618 #define IDTE_NODAT 0x1000 1619 #define IDTE_GUEST_ASCE 0x2000 1620 1621 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1622 unsigned long opt, unsigned long asce, 1623 int local) 1624 { 1625 unsigned long sto; 1626 1627 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1628 if (__builtin_constant_p(opt) && opt == 0) { 1629 /* flush without guest asce */ 1630 asm volatile( 1631 " idte %[r1],0,%[r2],%[m4]" 1632 : "+m" (*pmdp) 1633 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1634 [m4] "i" (local) 1635 : "cc" ); 1636 } else { 1637 /* flush with guest asce */ 1638 asm volatile( 1639 " idte %[r1],%[r3],%[r2],%[m4]" 1640 : "+m" (*pmdp) 1641 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1642 [r3] "a" (asce), [m4] "i" (local) 1643 : "cc" ); 1644 } 1645 } 1646 1647 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1648 unsigned long opt, unsigned long asce, 1649 int local) 1650 { 1651 unsigned long r3o; 1652 1653 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1654 r3o |= _ASCE_TYPE_REGION3; 1655 if (__builtin_constant_p(opt) && opt == 0) { 1656 /* flush without guest asce */ 1657 asm volatile( 1658 " idte %[r1],0,%[r2],%[m4]" 1659 : "+m" (*pudp) 1660 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1661 [m4] "i" (local) 1662 : "cc"); 1663 } else { 1664 /* flush with guest asce */ 1665 asm volatile( 1666 " idte %[r1],%[r3],%[r2],%[m4]" 1667 : "+m" (*pudp) 1668 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1669 [r3] "a" (asce), [m4] "i" (local) 1670 : "cc" ); 1671 } 1672 } 1673 1674 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1675 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1676 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1677 1678 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1679 1680 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1681 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1682 pgtable_t pgtable); 1683 1684 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1685 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1686 1687 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1688 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1689 unsigned long addr, pmd_t *pmdp, 1690 pmd_t entry, int dirty) 1691 { 1692 VM_BUG_ON(addr & ~HPAGE_MASK); 1693 1694 entry = pmd_mkyoung(entry); 1695 if (dirty) 1696 entry = pmd_mkdirty(entry); 1697 if (pmd_val(*pmdp) == pmd_val(entry)) 1698 return 0; 1699 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1700 return 1; 1701 } 1702 1703 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1704 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1705 unsigned long addr, pmd_t *pmdp) 1706 { 1707 pmd_t pmd = *pmdp; 1708 1709 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1710 return pmd_young(pmd); 1711 } 1712 1713 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1714 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1715 unsigned long addr, pmd_t *pmdp) 1716 { 1717 VM_BUG_ON(addr & ~HPAGE_MASK); 1718 return pmdp_test_and_clear_young(vma, addr, pmdp); 1719 } 1720 1721 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1722 pmd_t *pmdp, pmd_t entry) 1723 { 1724 if (!MACHINE_HAS_NX) 1725 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1726 set_pmd(pmdp, entry); 1727 } 1728 1729 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1730 { 1731 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1732 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1733 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1734 } 1735 1736 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1737 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1738 unsigned long addr, pmd_t *pmdp) 1739 { 1740 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1741 } 1742 1743 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1744 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1745 unsigned long addr, 1746 pmd_t *pmdp, int full) 1747 { 1748 if (full) { 1749 pmd_t pmd = *pmdp; 1750 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1751 return pmd; 1752 } 1753 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1754 } 1755 1756 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1757 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1758 unsigned long addr, pmd_t *pmdp) 1759 { 1760 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1761 } 1762 1763 #define __HAVE_ARCH_PMDP_INVALIDATE 1764 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1765 unsigned long addr, pmd_t *pmdp) 1766 { 1767 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1768 1769 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1770 } 1771 1772 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1773 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1774 unsigned long addr, pmd_t *pmdp) 1775 { 1776 pmd_t pmd = *pmdp; 1777 1778 if (pmd_write(pmd)) 1779 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1780 } 1781 1782 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1783 unsigned long address, 1784 pmd_t *pmdp) 1785 { 1786 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1787 } 1788 #define pmdp_collapse_flush pmdp_collapse_flush 1789 1790 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1791 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1792 1793 static inline int pmd_trans_huge(pmd_t pmd) 1794 { 1795 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1796 } 1797 1798 #define has_transparent_hugepage has_transparent_hugepage 1799 static inline int has_transparent_hugepage(void) 1800 { 1801 return MACHINE_HAS_EDAT1 ? 1 : 0; 1802 } 1803 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1804 1805 /* 1806 * 64 bit swap entry format: 1807 * A page-table entry has some bits we have to treat in a special way. 1808 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1809 * as invalid. 1810 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1811 * | offset |E11XX|type |S0| 1812 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1813 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1814 * 1815 * Bits 0-51 store the offset. 1816 * Bit 52 (E) is used to remember PG_anon_exclusive. 1817 * Bits 57-61 store the type. 1818 * Bit 62 (S) is used for softdirty tracking. 1819 * Bits 55 and 56 (X) are unused. 1820 */ 1821 1822 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1823 #define __SWP_OFFSET_SHIFT 12 1824 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1825 #define __SWP_TYPE_SHIFT 2 1826 1827 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1828 { 1829 unsigned long pteval; 1830 1831 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1832 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1833 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1834 return __pte(pteval); 1835 } 1836 1837 static inline unsigned long __swp_type(swp_entry_t entry) 1838 { 1839 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1840 } 1841 1842 static inline unsigned long __swp_offset(swp_entry_t entry) 1843 { 1844 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1845 } 1846 1847 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1848 { 1849 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1850 } 1851 1852 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1853 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1854 1855 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1856 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1857 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1858 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1859 extern void vmem_unmap_4k_page(unsigned long addr); 1860 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1861 extern int s390_enable_sie(void); 1862 extern int s390_enable_skey(void); 1863 extern void s390_reset_cmma(struct mm_struct *mm); 1864 1865 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1866 #define HAVE_ARCH_UNMAPPED_AREA 1867 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1868 1869 #define pmd_pgtable(pmd) \ 1870 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1871 1872 #endif /* _S390_PAGE_H */ 1873