1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  S390 version
4  *
5  *  Derived from "include/asm-i386/mmu_context.h"
6  */
7 
8 #ifndef __S390_MMU_CONTEXT_H
9 #define __S390_MMU_CONTEXT_H
10 
11 #include <asm/pgalloc.h>
12 #include <linux/uaccess.h>
13 #include <linux/mm_types.h>
14 #include <asm/tlbflush.h>
15 #include <asm/ctl_reg.h>
16 #include <asm-generic/mm_hooks.h>
17 
18 static inline int init_new_context(struct task_struct *tsk,
19 				   struct mm_struct *mm)
20 {
21 	unsigned long asce_type, init_entry;
22 
23 	spin_lock_init(&mm->context.lock);
24 	INIT_LIST_HEAD(&mm->context.pgtable_list);
25 	INIT_LIST_HEAD(&mm->context.gmap_list);
26 	cpumask_clear(&mm->context.cpu_attach_mask);
27 	atomic_set(&mm->context.flush_count, 0);
28 	atomic_set(&mm->context.is_protected, 0);
29 	mm->context.gmap_asce = 0;
30 	mm->context.flush_mm = 0;
31 #ifdef CONFIG_PGSTE
32 	mm->context.alloc_pgste = page_table_allocate_pgste ||
33 		test_thread_flag(TIF_PGSTE) ||
34 		(current->mm && current->mm->context.alloc_pgste);
35 	mm->context.has_pgste = 0;
36 	mm->context.uses_skeys = 0;
37 	mm->context.uses_cmm = 0;
38 	mm->context.allow_gmap_hpage_1m = 0;
39 #endif
40 	switch (mm->context.asce_limit) {
41 	default:
42 		/*
43 		 * context created by exec, the value of asce_limit can
44 		 * only be zero in this case
45 		 */
46 		VM_BUG_ON(mm->context.asce_limit);
47 		/* continue as 3-level task */
48 		mm->context.asce_limit = _REGION2_SIZE;
49 		fallthrough;
50 	case _REGION2_SIZE:
51 		/* forked 3-level task */
52 		init_entry = _REGION3_ENTRY_EMPTY;
53 		asce_type = _ASCE_TYPE_REGION3;
54 		break;
55 	case TASK_SIZE_MAX:
56 		/* forked 5-level task */
57 		init_entry = _REGION1_ENTRY_EMPTY;
58 		asce_type = _ASCE_TYPE_REGION1;
59 		break;
60 	case _REGION1_SIZE:
61 		/* forked 4-level task */
62 		init_entry = _REGION2_ENTRY_EMPTY;
63 		asce_type = _ASCE_TYPE_REGION2;
64 		break;
65 	}
66 	mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
67 			   _ASCE_USER_BITS | asce_type;
68 	crst_table_init((unsigned long *) mm->pgd, init_entry);
69 	return 0;
70 }
71 
72 #define destroy_context(mm)             do { } while (0)
73 
74 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
75 			     struct task_struct *tsk)
76 {
77 	int cpu = smp_processor_id();
78 
79 	if (next == &init_mm)
80 		S390_lowcore.user_asce = s390_invalid_asce;
81 	else
82 		S390_lowcore.user_asce = next->context.asce;
83 	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
84 	/* Clear previous user-ASCE from CR7 */
85 	__ctl_load(s390_invalid_asce, 7, 7);
86 	if (prev != next)
87 		cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
88 }
89 
90 #define finish_arch_post_lock_switch finish_arch_post_lock_switch
91 static inline void finish_arch_post_lock_switch(void)
92 {
93 	struct task_struct *tsk = current;
94 	struct mm_struct *mm = tsk->mm;
95 
96 	if (mm) {
97 		preempt_disable();
98 		while (atomic_read(&mm->context.flush_count))
99 			cpu_relax();
100 		cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
101 		__tlb_flush_mm_lazy(mm);
102 		preempt_enable();
103 	}
104 	__ctl_load(S390_lowcore.user_asce, 7, 7);
105 }
106 
107 #define enter_lazy_tlb(mm,tsk)	do { } while (0)
108 #define deactivate_mm(tsk,mm)	do { } while (0)
109 
110 static inline void activate_mm(struct mm_struct *prev,
111                                struct mm_struct *next)
112 {
113 	switch_mm(prev, next, current);
114 	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
115 	__ctl_load(S390_lowcore.user_asce, 7, 7);
116 }
117 
118 #endif /* __S390_MMU_CONTEXT_H */
119