1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  S390 version
4  *
5  *  Derived from "include/asm-i386/mmu_context.h"
6  */
7 
8 #ifndef __S390_MMU_CONTEXT_H
9 #define __S390_MMU_CONTEXT_H
10 
11 #include <asm/pgalloc.h>
12 #include <linux/uaccess.h>
13 #include <linux/mm_types.h>
14 #include <asm/tlbflush.h>
15 #include <asm/ctl_reg.h>
16 #include <asm-generic/mm_hooks.h>
17 
18 #define init_new_context init_new_context
19 static inline int init_new_context(struct task_struct *tsk,
20 				   struct mm_struct *mm)
21 {
22 	unsigned long asce_type, init_entry;
23 
24 	spin_lock_init(&mm->context.lock);
25 	INIT_LIST_HEAD(&mm->context.pgtable_list);
26 	INIT_LIST_HEAD(&mm->context.gmap_list);
27 	cpumask_clear(&mm->context.cpu_attach_mask);
28 	atomic_set(&mm->context.flush_count, 0);
29 	atomic_set(&mm->context.protected_count, 0);
30 	mm->context.gmap_asce = 0;
31 	mm->context.flush_mm = 0;
32 #ifdef CONFIG_PGSTE
33 	mm->context.alloc_pgste = page_table_allocate_pgste ||
34 		test_thread_flag(TIF_PGSTE) ||
35 		(current->mm && current->mm->context.alloc_pgste);
36 	mm->context.has_pgste = 0;
37 	mm->context.uses_skeys = 0;
38 	mm->context.uses_cmm = 0;
39 	mm->context.allow_cow_sharing = 1;
40 	mm->context.allow_gmap_hpage_1m = 0;
41 #endif
42 	switch (mm->context.asce_limit) {
43 	default:
44 		/*
45 		 * context created by exec, the value of asce_limit can
46 		 * only be zero in this case
47 		 */
48 		VM_BUG_ON(mm->context.asce_limit);
49 		/* continue as 3-level task */
50 		mm->context.asce_limit = _REGION2_SIZE;
51 		fallthrough;
52 	case _REGION2_SIZE:
53 		/* forked 3-level task */
54 		init_entry = _REGION3_ENTRY_EMPTY;
55 		asce_type = _ASCE_TYPE_REGION3;
56 		break;
57 	case TASK_SIZE_MAX:
58 		/* forked 5-level task */
59 		init_entry = _REGION1_ENTRY_EMPTY;
60 		asce_type = _ASCE_TYPE_REGION1;
61 		break;
62 	case _REGION1_SIZE:
63 		/* forked 4-level task */
64 		init_entry = _REGION2_ENTRY_EMPTY;
65 		asce_type = _ASCE_TYPE_REGION2;
66 		break;
67 	}
68 	mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
69 			   _ASCE_USER_BITS | asce_type;
70 	crst_table_init((unsigned long *) mm->pgd, init_entry);
71 	return 0;
72 }
73 
74 static inline void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
75 				      struct task_struct *tsk)
76 {
77 	int cpu = smp_processor_id();
78 
79 	if (next == &init_mm)
80 		S390_lowcore.user_asce = s390_invalid_asce;
81 	else
82 		S390_lowcore.user_asce = next->context.asce;
83 	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
84 	/* Clear previous user-ASCE from CR7 */
85 	__ctl_load(s390_invalid_asce, 7, 7);
86 	if (prev != next)
87 		cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
88 }
89 #define switch_mm_irqs_off switch_mm_irqs_off
90 
91 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
92 			     struct task_struct *tsk)
93 {
94 	unsigned long flags;
95 
96 	local_irq_save(flags);
97 	switch_mm_irqs_off(prev, next, tsk);
98 	local_irq_restore(flags);
99 }
100 
101 #define finish_arch_post_lock_switch finish_arch_post_lock_switch
102 static inline void finish_arch_post_lock_switch(void)
103 {
104 	struct task_struct *tsk = current;
105 	struct mm_struct *mm = tsk->mm;
106 
107 	if (mm) {
108 		preempt_disable();
109 		while (atomic_read(&mm->context.flush_count))
110 			cpu_relax();
111 		cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
112 		__tlb_flush_mm_lazy(mm);
113 		preempt_enable();
114 	}
115 	__ctl_load(S390_lowcore.user_asce, 7, 7);
116 }
117 
118 #define activate_mm activate_mm
119 static inline void activate_mm(struct mm_struct *prev,
120                                struct mm_struct *next)
121 {
122 	switch_mm(prev, next, current);
123 	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
124 	__ctl_load(S390_lowcore.user_asce, 7, 7);
125 }
126 
127 #include <asm-generic/mmu_context.h>
128 
129 #endif /* __S390_MMU_CONTEXT_H */
130