1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Adjunct processor (AP) interfaces 4 * 5 * Copyright IBM Corp. 2017 6 * 7 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com> 8 * Martin Schwidefsky <schwidefsky@de.ibm.com> 9 * Harald Freudenberger <freude@de.ibm.com> 10 */ 11 12 #ifndef _ASM_S390_AP_H_ 13 #define _ASM_S390_AP_H_ 14 15 /** 16 * The ap_qid_t identifier of an ap queue. 17 * If the AP facilities test (APFT) facility is available, 18 * card and queue index are 8 bit values, otherwise 19 * card index is 6 bit and queue index a 4 bit value. 20 */ 21 typedef unsigned int ap_qid_t; 22 23 #define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff)) 24 #define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff) 25 #define AP_QID_QUEUE(_qid) ((_qid) & 0xff) 26 27 /** 28 * struct ap_queue_status - Holds the AP queue status. 29 * @queue_empty: Shows if queue is empty 30 * @replies_waiting: Waiting replies 31 * @queue_full: Is 1 if the queue is full 32 * @irq_enabled: Shows if interrupts are enabled for the AP 33 * @response_code: Holds the 8 bit response code 34 * 35 * The ap queue status word is returned by all three AP functions 36 * (PQAP, NQAP and DQAP). There's a set of flags in the first 37 * byte, followed by a 1 byte response code. 38 */ 39 struct ap_queue_status { 40 unsigned int queue_empty : 1; 41 unsigned int replies_waiting : 1; 42 unsigned int queue_full : 1; 43 unsigned int _pad1 : 4; 44 unsigned int irq_enabled : 1; 45 unsigned int response_code : 8; 46 unsigned int _pad2 : 16; 47 }; 48 49 /** 50 * ap_intructions_available() - Test if AP instructions are available. 51 * 52 * Returns true if the AP instructions are installed, otherwise false. 53 */ 54 static inline bool ap_instructions_available(void) 55 { 56 unsigned long reg0 = AP_MKQID(0, 0); 57 unsigned long reg1 = 0; 58 59 asm volatile( 60 " lgr 0,%[reg0]\n" /* qid into gr0 */ 61 " lghi 1,0\n" /* 0 into gr1 */ 62 " lghi 2,0\n" /* 0 into gr2 */ 63 " .long 0xb2af0000\n" /* PQAP(TAPQ) */ 64 "0: la %[reg1],1\n" /* 1 into reg1 */ 65 "1:\n" 66 EX_TABLE(0b, 1b) 67 : [reg1] "+&d" (reg1) 68 : [reg0] "d" (reg0) 69 : "cc", "0", "1", "2"); 70 return reg1 != 0; 71 } 72 73 /** 74 * ap_tapq(): Test adjunct processor queue. 75 * @qid: The AP queue number 76 * @info: Pointer to queue descriptor 77 * 78 * Returns AP queue status structure. 79 */ 80 static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info) 81 { 82 struct ap_queue_status reg1; 83 unsigned long reg2; 84 85 asm volatile( 86 " lgr 0,%[qid]\n" /* qid into gr0 */ 87 " lghi 2,0\n" /* 0 into gr2 */ 88 " .long 0xb2af0000\n" /* PQAP(TAPQ) */ 89 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 90 " lgr %[reg2],2\n" /* gr2 into reg2 */ 91 : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2) 92 : [qid] "d" (qid) 93 : "cc", "0", "1", "2"); 94 if (info) 95 *info = reg2; 96 return reg1; 97 } 98 99 /** 100 * ap_test_queue(): Test adjunct processor queue. 101 * @qid: The AP queue number 102 * @tbit: Test facilities bit 103 * @info: Pointer to queue descriptor 104 * 105 * Returns AP queue status structure. 106 */ 107 static inline struct ap_queue_status ap_test_queue(ap_qid_t qid, 108 int tbit, 109 unsigned long *info) 110 { 111 if (tbit) 112 qid |= 1UL << 23; /* set T bit*/ 113 return ap_tapq(qid, info); 114 } 115 116 /** 117 * ap_pqap_rapq(): Reset adjunct processor queue. 118 * @qid: The AP queue number 119 * 120 * Returns AP queue status structure. 121 */ 122 static inline struct ap_queue_status ap_rapq(ap_qid_t qid) 123 { 124 unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */ 125 struct ap_queue_status reg1; 126 127 asm volatile( 128 " lgr 0,%[reg0]\n" /* qid arg into gr0 */ 129 " .long 0xb2af0000\n" /* PQAP(RAPQ) */ 130 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 131 : [reg1] "=&d" (reg1) 132 : [reg0] "d" (reg0) 133 : "cc", "0", "1"); 134 return reg1; 135 } 136 137 /** 138 * ap_pqap_zapq(): Reset and zeroize adjunct processor queue. 139 * @qid: The AP queue number 140 * 141 * Returns AP queue status structure. 142 */ 143 static inline struct ap_queue_status ap_zapq(ap_qid_t qid) 144 { 145 unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */ 146 struct ap_queue_status reg1; 147 148 asm volatile( 149 " lgr 0,%[reg0]\n" /* qid arg into gr0 */ 150 " .long 0xb2af0000\n" /* PQAP(ZAPQ) */ 151 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 152 : [reg1] "=&d" (reg1) 153 : [reg0] "d" (reg0) 154 : "cc", "0", "1"); 155 return reg1; 156 } 157 158 /** 159 * struct ap_config_info - convenience struct for AP crypto 160 * config info as returned by the ap_qci() function. 161 */ 162 struct ap_config_info { 163 unsigned int apsc : 1; /* S bit */ 164 unsigned int apxa : 1; /* N bit */ 165 unsigned int qact : 1; /* C bit */ 166 unsigned int rc8a : 1; /* R bit */ 167 unsigned char _reserved1 : 4; 168 unsigned char _reserved2[3]; 169 unsigned char Na; /* max # of APs - 1 */ 170 unsigned char Nd; /* max # of Domains - 1 */ 171 unsigned char _reserved3[10]; 172 unsigned int apm[8]; /* AP ID mask */ 173 unsigned int aqm[8]; /* AP (usage) queue mask */ 174 unsigned int adm[8]; /* AP (control) domain mask */ 175 unsigned char _reserved4[16]; 176 } __aligned(8); 177 178 /** 179 * ap_qci(): Get AP configuration data 180 * 181 * Returns 0 on success, or -EOPNOTSUPP. 182 */ 183 static inline int ap_qci(struct ap_config_info *config) 184 { 185 unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */ 186 unsigned long reg1 = -EOPNOTSUPP; 187 struct ap_config_info *reg2 = config; 188 189 asm volatile( 190 " lgr 0,%[reg0]\n" /* QCI fc into gr0 */ 191 " lgr 2,%[reg2]\n" /* ptr to config into gr2 */ 192 " .long 0xb2af0000\n" /* PQAP(QCI) */ 193 "0: la %[reg1],0\n" /* good case, QCI fc available */ 194 "1:\n" 195 EX_TABLE(0b, 1b) 196 : [reg1] "+&d" (reg1) 197 : [reg0] "d" (reg0), [reg2] "d" (reg2) 198 : "cc", "memory", "0", "2"); 199 200 return reg1; 201 } 202 203 /* 204 * struct ap_qirq_ctrl - convenient struct for easy invocation 205 * of the ap_aqic() function. This struct is passed as GR1 206 * parameter to the PQAP(AQIC) instruction. For details please 207 * see the AR documentation. 208 */ 209 struct ap_qirq_ctrl { 210 unsigned int _res1 : 8; 211 unsigned int zone : 8; /* zone info */ 212 unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */ 213 unsigned int _res2 : 4; 214 unsigned int gisc : 3; /* guest isc field */ 215 unsigned int _res3 : 6; 216 unsigned int gf : 2; /* gisa format */ 217 unsigned int _res4 : 1; 218 unsigned int gisa : 27; /* gisa origin */ 219 unsigned int _res5 : 1; 220 unsigned int isc : 3; /* irq sub class */ 221 }; 222 223 /** 224 * ap_aqic(): Control interruption for a specific AP. 225 * @qid: The AP queue number 226 * @qirqctrl: struct ap_qirq_ctrl (64 bit value) 227 * @ind: The notification indicator byte 228 * 229 * Returns AP queue status. 230 */ 231 static inline struct ap_queue_status ap_aqic(ap_qid_t qid, 232 struct ap_qirq_ctrl qirqctrl, 233 void *ind) 234 { 235 unsigned long reg0 = qid | (3UL << 24); /* fc 3UL is AQIC */ 236 union { 237 unsigned long value; 238 struct ap_qirq_ctrl qirqctrl; 239 struct ap_queue_status status; 240 } reg1; 241 void *reg2 = ind; 242 243 reg1.qirqctrl = qirqctrl; 244 245 asm volatile( 246 " lgr 0,%[reg0]\n" /* qid param into gr0 */ 247 " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */ 248 " lgr 2,%[reg2]\n" /* ni addr into gr2 */ 249 " .long 0xb2af0000\n" /* PQAP(AQIC) */ 250 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 251 : [reg1] "+&d" (reg1) 252 : [reg0] "d" (reg0), [reg2] "d" (reg2) 253 : "cc", "0", "1", "2"); 254 255 return reg1.status; 256 } 257 258 /* 259 * union ap_qact_ap_info - used together with the 260 * ap_aqic() function to provide a convenient way 261 * to handle the ap info needed by the qact function. 262 */ 263 union ap_qact_ap_info { 264 unsigned long val; 265 struct { 266 unsigned int : 3; 267 unsigned int mode : 3; 268 unsigned int : 26; 269 unsigned int cat : 8; 270 unsigned int : 8; 271 unsigned char ver[2]; 272 }; 273 }; 274 275 /** 276 * ap_qact(): Query AP combatibility type. 277 * @qid: The AP queue number 278 * @apinfo: On input the info about the AP queue. On output the 279 * alternate AP queue info provided by the qact function 280 * in GR2 is stored in. 281 * 282 * Returns AP queue status. Check response_code field for failures. 283 */ 284 static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit, 285 union ap_qact_ap_info *apinfo) 286 { 287 unsigned long reg0 = qid | (5UL << 24) | ((ifbit & 0x01) << 22); 288 union { 289 unsigned long value; 290 struct ap_queue_status status; 291 } reg1; 292 unsigned long reg2; 293 294 reg1.value = apinfo->val; 295 296 asm volatile( 297 " lgr 0,%[reg0]\n" /* qid param into gr0 */ 298 " lgr 1,%[reg1]\n" /* qact in info into gr1 */ 299 " .long 0xb2af0000\n" /* PQAP(QACT) */ 300 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 301 " lgr %[reg2],2\n" /* qact out info into reg2 */ 302 : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2) 303 : [reg0] "d" (reg0) 304 : "cc", "0", "1", "2"); 305 apinfo->val = reg2; 306 return reg1.status; 307 } 308 309 /** 310 * ap_nqap(): Send message to adjunct processor queue. 311 * @qid: The AP queue number 312 * @psmid: The program supplied message identifier 313 * @msg: The message text 314 * @length: The message length 315 * 316 * Returns AP queue status structure. 317 * Condition code 1 on NQAP can't happen because the L bit is 1. 318 * Condition code 2 on NQAP also means the send is incomplete, 319 * because a segment boundary was reached. The NQAP is repeated. 320 */ 321 static inline struct ap_queue_status ap_nqap(ap_qid_t qid, 322 unsigned long long psmid, 323 void *msg, size_t length) 324 { 325 unsigned long reg0 = qid | 0x40000000UL; /* 0x4... is last msg part */ 326 union register_pair nqap_r1, nqap_r2; 327 struct ap_queue_status reg1; 328 329 nqap_r1.even = (unsigned int)(psmid >> 32); 330 nqap_r1.odd = psmid & 0xffffffff; 331 nqap_r2.even = (unsigned long)msg; 332 nqap_r2.odd = (unsigned long)length; 333 334 asm volatile ( 335 " lgr 0,%[reg0]\n" /* qid param in gr0 */ 336 "0: .insn rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n" 337 " brc 2,0b\n" /* handle partial completion */ 338 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 339 : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1), 340 [nqap_r2] "+&d" (nqap_r2.pair) 341 : [nqap_r1] "d" (nqap_r1.pair) 342 : "cc", "memory", "0", "1"); 343 return reg1; 344 } 345 346 /** 347 * ap_dqap(): Receive message from adjunct processor queue. 348 * @qid: The AP queue number 349 * @psmid: Pointer to program supplied message identifier 350 * @msg: The message text 351 * @length: The message length 352 * @reslength: Resitual length on return 353 * @resgr0: input: gr0 value (only used if != 0), output: resitual gr0 content 354 * 355 * Returns AP queue status structure. 356 * Condition code 1 on DQAP means the receive has taken place 357 * but only partially. The response is incomplete, hence the 358 * DQAP is repeated. 359 * Condition code 2 on DQAP also means the receive is incomplete, 360 * this time because a segment boundary was reached. Again, the 361 * DQAP is repeated. 362 * Note that gpr2 is used by the DQAP instruction to keep track of 363 * any 'residual' length, in case the instruction gets interrupted. 364 * Hence it gets zeroed before the instruction. 365 * If the message does not fit into the buffer, this function will 366 * return with a truncated message and the reply in the firmware queue 367 * is not removed. This is indicated to the caller with an 368 * ap_queue_status response_code value of all bits on (0xFF) and (if 369 * the reslength ptr is given) the remaining length is stored in 370 * *reslength and (if the resgr0 ptr is given) the updated gr0 value 371 * for further processing of this msg entry is stored in *resgr0. The 372 * caller needs to detect this situation and should invoke ap_dqap 373 * with a valid resgr0 ptr and a value in there != 0 to indicate that 374 * *resgr0 is to be used instead of qid to further process this entry. 375 */ 376 static inline struct ap_queue_status ap_dqap(ap_qid_t qid, 377 unsigned long long *psmid, 378 void *msg, size_t length, 379 size_t *reslength, 380 unsigned long *resgr0) 381 { 382 unsigned long reg0 = resgr0 && *resgr0 ? *resgr0 : qid | 0x80000000UL; 383 struct ap_queue_status reg1; 384 unsigned long reg2; 385 union register_pair rp1, rp2; 386 387 rp1.even = 0UL; 388 rp1.odd = 0UL; 389 rp2.even = (unsigned long)msg; 390 rp2.odd = (unsigned long)length; 391 392 asm volatile( 393 " lgr 0,%[reg0]\n" /* qid param into gr0 */ 394 " lghi 2,0\n" /* 0 into gr2 (res length) */ 395 "0: ltgr %N[rp2],%N[rp2]\n" /* check buf len */ 396 " jz 2f\n" /* go out if buf len is 0 */ 397 "1: .insn rre,0xb2ae0000,%[rp1],%[rp2]\n" 398 " brc 6,0b\n" /* handle partial complete */ 399 "2: lgr %[reg0],0\n" /* gr0 (qid + info) into reg0 */ 400 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ 401 " lgr %[reg2],2\n" /* gr2 (res length) into reg2 */ 402 : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1), [reg2] "=&d" (reg2), 403 [rp1] "+&d" (rp1.pair), [rp2] "+&d" (rp2.pair) 404 : 405 : "cc", "memory", "0", "1", "2"); 406 407 if (reslength) 408 *reslength = reg2; 409 if (reg2 != 0 && rp2.odd == 0) { 410 /* 411 * Partially complete, status in gr1 is not set. 412 * Signal the caller that this dqap is only partially received 413 * with a special status response code 0xFF and *resgr0 updated 414 */ 415 reg1.response_code = 0xFF; 416 if (resgr0) 417 *resgr0 = reg0; 418 } else { 419 *psmid = (((unsigned long long)rp1.even) << 32) + rp1.odd; 420 if (resgr0) 421 *resgr0 = 0; 422 } 423 424 return reg1; 425 } 426 427 /* 428 * Interface to tell the AP bus code that a configuration 429 * change has happened. The bus code should at least do 430 * an ap bus resource rescan. 431 */ 432 #if IS_ENABLED(CONFIG_ZCRYPT) 433 void ap_bus_cfg_chg(void); 434 #else 435 static inline void ap_bus_cfg_chg(void){} 436 #endif 437 438 #endif /* _ASM_S390_AP_H_ */ 439