1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Hardware-accelerated CRC-32 variants for Linux on z Systems 4 * 5 * Use the z/Architecture Vector Extension Facility to accelerate the 6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet 7 * and Castagnoli. 8 * 9 * This CRC-32 implementation algorithm is bitreflected and processes 10 * the least-significant bit first (Little-Endian). 11 * 12 * Copyright IBM Corp. 2015 13 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> 14 */ 15 16#include <linux/linkage.h> 17#include <asm/vx-insn.h> 18 19/* Vector register range containing CRC-32 constants */ 20#define CONST_PERM_LE2BE %v9 21#define CONST_R2R1 %v10 22#define CONST_R4R3 %v11 23#define CONST_R5 %v12 24#define CONST_RU_POLY %v13 25#define CONST_CRC_POLY %v14 26 27.data 28.align 8 29 30/* 31 * The CRC-32 constant block contains reduction constants to fold and 32 * process particular chunks of the input data stream in parallel. 33 * 34 * For the CRC-32 variants, the constants are precomputed according to 35 * these definitions: 36 * 37 * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1 38 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1 39 * R3 = [(x128+32 mod P'(x) << 32)]' << 1 40 * R4 = [(x128-32 mod P'(x) << 32)]' << 1 41 * R5 = [(x64 mod P'(x) << 32)]' << 1 42 * R6 = [(x32 mod P'(x) << 32)]' << 1 43 * 44 * The bitreflected Barret reduction constant, u', is defined as 45 * the bit reversal of floor(x**64 / P(x)). 46 * 47 * where P(x) is the polynomial in the normal domain and the P'(x) is the 48 * polynomial in the reversed (bitreflected) domain. 49 * 50 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials: 51 * 52 * P(x) = 0x04C11DB7 53 * P'(x) = 0xEDB88320 54 * 55 * CRC-32C (Castagnoli) polynomials: 56 * 57 * P(x) = 0x1EDC6F41 58 * P'(x) = 0x82F63B78 59 */ 60 61.Lconstants_CRC_32_LE: 62 .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask 63 .quad 0x1c6e41596, 0x154442bd4 # R2, R1 64 .quad 0x0ccaa009e, 0x1751997d0 # R4, R3 65 .octa 0x163cd6124 # R5 66 .octa 0x1F7011641 # u' 67 .octa 0x1DB710641 # P'(x) << 1 68 69.Lconstants_CRC_32C_LE: 70 .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask 71 .quad 0x09e4addf8, 0x740eef02 # R2, R1 72 .quad 0x14cd00bd6, 0xf20c0dfe # R4, R3 73 .octa 0x0dd45aab8 # R5 74 .octa 0x0dea713f1 # u' 75 .octa 0x105ec76f0 # P'(x) << 1 76 77.previous 78 79 80.text 81 82/* 83 * The CRC-32 functions use these calling conventions: 84 * 85 * Parameters: 86 * 87 * %r2: Initial CRC value, typically ~0; and final CRC (return) value. 88 * %r3: Input buffer pointer, performance might be improved if the 89 * buffer is on a doubleword boundary. 90 * %r4: Length of the buffer, must be 64 bytes or greater. 91 * 92 * Register usage: 93 * 94 * %r5: CRC-32 constant pool base pointer. 95 * V0: Initial CRC value and intermediate constants and results. 96 * V1..V4: Data for CRC computation. 97 * V5..V8: Next data chunks that are fetched from the input buffer. 98 * V9: Constant for BE->LE conversion and shift operations 99 * 100 * V10..V14: CRC-32 constants. 101 */ 102 103ENTRY(crc32_le_vgfm_16) 104 larl %r5,.Lconstants_CRC_32_LE 105 j crc32_le_vgfm_generic 106 107ENTRY(crc32c_le_vgfm_16) 108 larl %r5,.Lconstants_CRC_32C_LE 109 j crc32_le_vgfm_generic 110 111 112crc32_le_vgfm_generic: 113 /* Load CRC-32 constants */ 114 VLM CONST_PERM_LE2BE,CONST_CRC_POLY,0,%r5 115 116 /* 117 * Load the initial CRC value. 118 * 119 * The CRC value is loaded into the rightmost word of the 120 * vector register and is later XORed with the LSB portion 121 * of the loaded input data. 122 */ 123 VZERO %v0 /* Clear V0 */ 124 VLVGF %v0,%r2,3 /* Load CRC into rightmost word */ 125 126 /* Load a 64-byte data chunk and XOR with CRC */ 127 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */ 128 VPERM %v1,%v1,%v1,CONST_PERM_LE2BE 129 VPERM %v2,%v2,%v2,CONST_PERM_LE2BE 130 VPERM %v3,%v3,%v3,CONST_PERM_LE2BE 131 VPERM %v4,%v4,%v4,CONST_PERM_LE2BE 132 133 VX %v1,%v0,%v1 /* V1 ^= CRC */ 134 aghi %r3,64 /* BUF = BUF + 64 */ 135 aghi %r4,-64 /* LEN = LEN - 64 */ 136 137 cghi %r4,64 138 jl .Lless_than_64bytes 139 140.Lfold_64bytes_loop: 141 /* Load the next 64-byte data chunk into V5 to V8 */ 142 VLM %v5,%v8,0,%r3 143 VPERM %v5,%v5,%v5,CONST_PERM_LE2BE 144 VPERM %v6,%v6,%v6,CONST_PERM_LE2BE 145 VPERM %v7,%v7,%v7,CONST_PERM_LE2BE 146 VPERM %v8,%v8,%v8,CONST_PERM_LE2BE 147 148 /* 149 * Perform a GF(2) multiplication of the doublewords in V1 with 150 * the R1 and R2 reduction constants in V0. The intermediate result 151 * is then folded (accumulated) with the next data chunk in V5 and 152 * stored in V1. Repeat this step for the register contents 153 * in V2, V3, and V4 respectively. 154 */ 155 VGFMAG %v1,CONST_R2R1,%v1,%v5 156 VGFMAG %v2,CONST_R2R1,%v2,%v6 157 VGFMAG %v3,CONST_R2R1,%v3,%v7 158 VGFMAG %v4,CONST_R2R1,%v4,%v8 159 160 aghi %r3,64 /* BUF = BUF + 64 */ 161 aghi %r4,-64 /* LEN = LEN - 64 */ 162 163 cghi %r4,64 164 jnl .Lfold_64bytes_loop 165 166.Lless_than_64bytes: 167 /* 168 * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3 169 * and R4 and accumulating the next 128-bit chunk until a single 128-bit 170 * value remains. 171 */ 172 VGFMAG %v1,CONST_R4R3,%v1,%v2 173 VGFMAG %v1,CONST_R4R3,%v1,%v3 174 VGFMAG %v1,CONST_R4R3,%v1,%v4 175 176 cghi %r4,16 177 jl .Lfinal_fold 178 179.Lfold_16bytes_loop: 180 181 VL %v2,0,,%r3 /* Load next data chunk */ 182 VPERM %v2,%v2,%v2,CONST_PERM_LE2BE 183 VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */ 184 185 aghi %r3,16 186 aghi %r4,-16 187 188 cghi %r4,16 189 jnl .Lfold_16bytes_loop 190 191.Lfinal_fold: 192 /* 193 * Set up a vector register for byte shifts. The shift value must 194 * be loaded in bits 1-4 in byte element 7 of a vector register. 195 * Shift by 8 bytes: 0x40 196 * Shift by 4 bytes: 0x20 197 */ 198 VLEIB %v9,0x40,7 199 200 /* 201 * Prepare V0 for the next GF(2) multiplication: shift V0 by 8 bytes 202 * to move R4 into the rightmost doubleword and set the leftmost 203 * doubleword to 0x1. 204 */ 205 VSRLB %v0,CONST_R4R3,%v9 206 VLEIG %v0,1,0 207 208 /* 209 * Compute GF(2) product of V1 and V0. The rightmost doubleword 210 * of V1 is multiplied with R4. The leftmost doubleword of V1 is 211 * multiplied by 0x1 and is then XORed with rightmost product. 212 * Implicitly, the intermediate leftmost product becomes padded 213 */ 214 VGFMG %v1,%v0,%v1 215 216 /* 217 * Now do the final 32-bit fold by multiplying the rightmost word 218 * in V1 with R5 and XOR the result with the remaining bits in V1. 219 * 220 * To achieve this by a single VGFMAG, right shift V1 by a word 221 * and store the result in V2 which is then accumulated. Use the 222 * vector unpack instruction to load the rightmost half of the 223 * doubleword into the rightmost doubleword element of V1; the other 224 * half is loaded in the leftmost doubleword. 225 * The vector register with CONST_R5 contains the R5 constant in the 226 * rightmost doubleword and the leftmost doubleword is zero to ignore 227 * the leftmost product of V1. 228 */ 229 VLEIB %v9,0x20,7 /* Shift by words */ 230 VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */ 231 VUPLLF %v1,%v1 /* Split rightmost doubleword */ 232 VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */ 233 234 /* 235 * Apply a Barret reduction to compute the final 32-bit CRC value. 236 * 237 * The input values to the Barret reduction are the degree-63 polynomial 238 * in V1 (R(x)), degree-32 generator polynomial, and the reduction 239 * constant u. The Barret reduction result is the CRC value of R(x) mod 240 * P(x). 241 * 242 * The Barret reduction algorithm is defined as: 243 * 244 * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u 245 * 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x) 246 * 3. C(x) = R(x) XOR T2(x) mod x^32 247 * 248 * Note: The leftmost doubleword of vector register containing 249 * CONST_RU_POLY is zero and, thus, the intermediate GF(2) product 250 * is zero and does not contribute to the final result. 251 */ 252 253 /* T1(x) = floor( R(x) / x^32 ) GF2MUL u */ 254 VUPLLF %v2,%v1 255 VGFMG %v2,CONST_RU_POLY,%v2 256 257 /* 258 * Compute the GF(2) product of the CRC polynomial with T1(x) in 259 * V2 and XOR the intermediate result, T2(x), with the value in V1. 260 * The final result is stored in word element 2 of V2. 261 */ 262 VUPLLF %v2,%v2 263 VGFMAG %v2,CONST_CRC_POLY,%v2,%v1 264 265.Ldone: 266 VLGVF %r2,%v2,2 267 br %r14 268 269.previous 270