1834979c2SHeiko Carstens // SPDX-License-Identifier: GPL-2.0 2834979c2SHeiko Carstens 3834979c2SHeiko Carstens #include <linux/compat.h> 4834979c2SHeiko Carstens #include <linux/ptrace.h> 5834979c2SHeiko Carstens #include <asm/cio.h> 6834979c2SHeiko Carstens #include <asm/asm-offsets.h> 7834979c2SHeiko Carstens #include "boot.h" 8834979c2SHeiko Carstens 9834979c2SHeiko Carstens #define CCW0(cmd, addr, cnt, flg) \ 10834979c2SHeiko Carstens { .cmd_code = cmd, .cda = addr, .count = cnt, .flags = flg, } 11834979c2SHeiko Carstens 12834979c2SHeiko Carstens #define PSW_MASK_DISABLED (PSW_MASK_WAIT | PSW_MASK_EA | PSW_MASK_BA) 13834979c2SHeiko Carstens 14834979c2SHeiko Carstens struct ipl_lowcore { 15834979c2SHeiko Carstens psw_t32 ipl_psw; /* 0x0000 */ 16834979c2SHeiko Carstens struct ccw0 ccwpgm[2]; /* 0x0008 */ 17834979c2SHeiko Carstens u8 fill[56]; /* 0x0018 */ 18834979c2SHeiko Carstens struct ccw0 ccwpgmcc[20]; /* 0x0050 */ 19834979c2SHeiko Carstens u8 pad_0xf0[0x01a0-0x00f0]; /* 0x00f0 */ 20834979c2SHeiko Carstens psw_t restart_psw; /* 0x01a0 */ 21834979c2SHeiko Carstens psw_t external_new_psw; /* 0x01b0 */ 22834979c2SHeiko Carstens psw_t svc_new_psw; /* 0x01c0 */ 23834979c2SHeiko Carstens psw_t program_new_psw; /* 0x01d0 */ 24834979c2SHeiko Carstens psw_t mcck_new_psw; /* 0x01e0 */ 25834979c2SHeiko Carstens psw_t io_new_psw; /* 0x01f0 */ 26834979c2SHeiko Carstens }; 27834979c2SHeiko Carstens 28834979c2SHeiko Carstens /* 29834979c2SHeiko Carstens * Initial lowcore for IPL: the first 24 bytes are loaded by IPL to 30834979c2SHeiko Carstens * addresses 0-23 (a PSW and two CCWs). Bytes 24-79 are discarded. 31834979c2SHeiko Carstens * The next 160 bytes are loaded to addresses 0x18-0xb7. They form 32834979c2SHeiko Carstens * the continuation of the CCW program started by IPL and load the 33834979c2SHeiko Carstens * range 0x0f0-0x730 from the image to the range 0x0f0-0x730 in 34834979c2SHeiko Carstens * memory. At the end of the channel program the PSW at location 0 is 35834979c2SHeiko Carstens * loaded. 36834979c2SHeiko Carstens * Initial processing starts at 0x200 = iplstart. 37834979c2SHeiko Carstens * 38834979c2SHeiko Carstens * The restart psw points to iplstart which allows to load a kernel 39834979c2SHeiko Carstens * image into memory and starting it by a psw restart on any cpu. All 40834979c2SHeiko Carstens * other default psw new locations contain a disabled wait psw where 41834979c2SHeiko Carstens * the address indicates which psw was loaded. 42834979c2SHeiko Carstens * 43834979c2SHeiko Carstens * Note that the 'file' utility can detect s390 kernel images. For 44834979c2SHeiko Carstens * that to succeed the two initial CCWs, and the 0x40 fill bytes must 45834979c2SHeiko Carstens * be present. 46834979c2SHeiko Carstens */ 47*f84d88edSHeiko Carstens static struct ipl_lowcore ipl_lowcore __used __section(".ipldata") = { 48834979c2SHeiko Carstens .ipl_psw = { .mask = PSW32_MASK_BASE, .addr = PSW32_ADDR_AMODE | IPL_START }, 49834979c2SHeiko Carstens .ccwpgm = { 50834979c2SHeiko Carstens [ 0] = CCW0(CCW_CMD_READ_IPL, 0x018, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 51834979c2SHeiko Carstens [ 1] = CCW0(CCW_CMD_READ_IPL, 0x068, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 52834979c2SHeiko Carstens }, 53834979c2SHeiko Carstens .fill = { 54834979c2SHeiko Carstens [ 0 ... 55] = 0x40, 55834979c2SHeiko Carstens }, 56834979c2SHeiko Carstens .ccwpgmcc = { 57834979c2SHeiko Carstens [ 0] = CCW0(CCW_CMD_READ_IPL, 0x0f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 58834979c2SHeiko Carstens [ 1] = CCW0(CCW_CMD_READ_IPL, 0x140, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 59834979c2SHeiko Carstens [ 2] = CCW0(CCW_CMD_READ_IPL, 0x190, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 60834979c2SHeiko Carstens [ 3] = CCW0(CCW_CMD_READ_IPL, 0x1e0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 61834979c2SHeiko Carstens [ 4] = CCW0(CCW_CMD_READ_IPL, 0x230, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 62834979c2SHeiko Carstens [ 5] = CCW0(CCW_CMD_READ_IPL, 0x280, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 63834979c2SHeiko Carstens [ 6] = CCW0(CCW_CMD_READ_IPL, 0x2d0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 64834979c2SHeiko Carstens [ 7] = CCW0(CCW_CMD_READ_IPL, 0x320, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 65834979c2SHeiko Carstens [ 8] = CCW0(CCW_CMD_READ_IPL, 0x370, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 66834979c2SHeiko Carstens [ 9] = CCW0(CCW_CMD_READ_IPL, 0x3c0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 67834979c2SHeiko Carstens [10] = CCW0(CCW_CMD_READ_IPL, 0x410, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 68834979c2SHeiko Carstens [11] = CCW0(CCW_CMD_READ_IPL, 0x460, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 69834979c2SHeiko Carstens [12] = CCW0(CCW_CMD_READ_IPL, 0x4b0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 70834979c2SHeiko Carstens [13] = CCW0(CCW_CMD_READ_IPL, 0x500, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 71834979c2SHeiko Carstens [14] = CCW0(CCW_CMD_READ_IPL, 0x550, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 72834979c2SHeiko Carstens [15] = CCW0(CCW_CMD_READ_IPL, 0x5a0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 73834979c2SHeiko Carstens [16] = CCW0(CCW_CMD_READ_IPL, 0x5f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 74834979c2SHeiko Carstens [17] = CCW0(CCW_CMD_READ_IPL, 0x640, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 75834979c2SHeiko Carstens [18] = CCW0(CCW_CMD_READ_IPL, 0x690, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 76834979c2SHeiko Carstens [19] = CCW0(CCW_CMD_READ_IPL, 0x6e0, 0x50, CCW_FLAG_SLI), 77834979c2SHeiko Carstens }, 78834979c2SHeiko Carstens .restart_psw = { .mask = 0, .addr = IPL_START, }, 79834979c2SHeiko Carstens .external_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_EXT_NEW_PSW, }, 80834979c2SHeiko Carstens .svc_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_SVC_NEW_PSW, }, 81834979c2SHeiko Carstens .program_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_PGM_NEW_PSW, }, 82834979c2SHeiko Carstens .mcck_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_MCK_NEW_PSW, }, 83834979c2SHeiko Carstens .io_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_IO_NEW_PSW, }, 84834979c2SHeiko Carstens }; 85