xref: /openbmc/linux/arch/s390/boot/head.S (revision f84d88ed) 
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright IBM Corp. 1999, 2010
4 *
5 *    Author(s): Hartmut Penner <hp@de.ibm.com>
6 *		 Martin Schwidefsky <schwidefsky@de.ibm.com>
7 *		 Rob van der Heij <rvdhei@iae.nl>
8 *
9 * There are 5 different IPL methods
10 *  1) load the image directly into ram at address 0 and do an PSW restart
11 *  2) linload will load the image from address 0x10000 to memory 0x10000
12 *     and start the code thru LPSW 0x0008000080010000 (VM only, deprecated)
13 *  3) generate the tape ipl header, store the generated image on a tape
14 *     and ipl from it
15 *     In case of SL tape you need to IPL 5 times to get past VOL1 etc
16 *  4) generate the vm reader ipl header, move the generated image to the
17 *     VM reader (use option NOH!) and do a ipl from reader (VM only)
18 *  5) direct call of start by the SALIPL loader
19 *  We use the cpuid to distinguish between VM and native ipl
20 *  params for kernel are pushed to 0x10400 (see setup.h)
21 *
22 */
23
24#include <linux/init.h>
25#include <linux/linkage.h>
26#include <asm/asm-offsets.h>
27#include <asm/page.h>
28#include <asm/ptrace.h>
29#include <asm/sclp.h>
30#include "boot.h"
31
32#define ARCH_OFFSET	4
33
34#define EP_OFFSET	0x10008
35#define EP_STRING	"S390EP"
36#define IPL_BS		0x730
37
38__HEAD
39ipl_start:
40	j	.Liplcont
41#
42# subroutine to wait for end I/O
43#
44.Lirqwait:
45	mvc	__LC_IO_NEW_PSW(16),.Lnewpsw	# set up IO interrupt psw
46	lpsw	.Lwaitpsw
47.Lioint:
48	br	%r14
49	.align	8
50.Lnewpsw:
51	.quad	0x0000000080000000,.Lioint
52.Lwaitpsw:
53	.long	0x020a0000,0x80000000+.Lioint
54
55#
56# subroutine for loading cards from the reader
57#
58.Lloader:
59	la	%r4,0(%r14)
60	la	%r3,.Lorb		# r2 = address of orb into r2
61	la	%r5,.Lirb		# r4 = address of irb
62	la	%r6,.Lccws
63	la	%r7,20
64.Linit:
65	st	%r2,4(%r6)		# initialize CCW data addresses
66	la	%r2,0x50(%r2)
67	la	%r6,8(%r6)
68	bct	7,.Linit
69
70	lctl	%c6,%c6,.Lcr6		# set IO subclass mask
71	slr	%r2,%r2
72.Lldlp:
73	ssch	0(%r3)			# load chunk of 1600 bytes
74	bnz	.Llderr
75.Lwait4irq:
76	bas	%r14,.Lirqwait
77	c	%r1,__LC_SUBCHANNEL_ID	# compare subchannel number
78	bne	.Lwait4irq
79	tsch	0(%r5)
80
81	slr	%r0,%r0
82	ic	%r0,8(%r5)		# get device status
83	chi	%r0,8			# channel end ?
84	be	.Lcont
85	chi	%r0,12			# channel end + device end ?
86	be	.Lcont
87
88	l	%r0,4(%r5)
89	s	%r0,8(%r3)		# r0/8 = number of ccws executed
90	mhi	%r0,10			# *10 = number of bytes in ccws
91	lh	%r3,10(%r5)		# get residual count
92	sr	%r0,%r3 		# #ccws*80-residual=#bytes read
93	ar	%r2,%r0
94
95	br	%r4			# r2 contains the total size
96
97.Lcont:
98	ahi	%r2,0x640		# add 0x640 to total size
99	la	%r6,.Lccws
100	la	%r7,20
101.Lincr:
102	l	%r0,4(%r6)		# update CCW data addresses
103	ahi	%r0,0x640
104	st	%r0,4(%r6)
105	ahi	%r6,8
106	bct	7,.Lincr
107
108	b	.Lldlp
109.Llderr:
110	lpsw	.Lcrash
111
112	.align	8
113.Lorb:	.long	0x00000000,0x0080ff00,.Lccws
114.Lirb:	.long	0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
115.Lcr6:	.long	0xff000000
116.Lloadp:.long	0,0
117	.align	8
118.Lcrash:.long	0x000a0000,0x00000000
119
120	.align	8
121.Lccws: .rept	19
122	.long	0x02600050,0x00000000
123	.endr
124	.long	0x02200050,0x00000000
125
126.Liplcont:
127	mvi	__LC_AR_MODE_ID,1	# set esame flag
128	slr	%r0,%r0			# set cpuid to zero
129	lhi	%r1,2			# mode 2 = esame (dump)
130	sigp	%r1,%r0,0x12		# switch to esame mode
131	bras	%r13,0f
132	.fill	16,4,0x0
1330:	lmh	%r0,%r15,0(%r13)	# clear high-order half of gprs
134	sam31				# switch to 31 bit addressing mode
135	lh	%r1,__LC_SUBCHANNEL_ID	# test if subchannel number
136	bct	%r1,.Lnoload		#  is valid
137	l	%r1,__LC_SUBCHANNEL_ID	# load ipl subchannel number
138	la	%r2,IPL_BS		# load start address
139	bas	%r14,.Lloader		# load rest of ipl image
140	l	%r12,.Lparm		# pointer to parameter area
141	st	%r1,IPL_DEVICE+ARCH_OFFSET-PARMAREA(%r12) # save ipl device number
142
143#
144# load parameter file from ipl device
145#
146.Lagain1:
147	l	%r2,.Linitrd		# ramdisk loc. is temp
148	bas	%r14,.Lloader		# load parameter file
149	ltr	%r2,%r2 		# got anything ?
150	bz	.Lnopf
151	l	%r3,MAX_COMMAND_LINE_SIZE+ARCH_OFFSET-PARMAREA(%r12)
152	ahi	%r3,-1
153	clr	%r2,%r3
154	bl	.Lnotrunc
155	lr	%r2,%r3
156.Lnotrunc:
157	l	%r4,.Linitrd
158	clc	0(3,%r4),.L_hdr		# if it is HDRx
159	bz	.Lagain1		# skip dataset header
160	clc	0(3,%r4),.L_eof		# if it is EOFx
161	bz	.Lagain1		# skip dateset trailer
162
163	lr	%r5,%r2
164	la	%r6,COMMAND_LINE-PARMAREA(%r12)
165	lr	%r7,%r2
166	ahi	%r7,1
167	mvcl	%r6,%r4
168.Lnopf:
169
170#
171# load ramdisk from ipl device
172#
173.Lagain2:
174	l	%r2,.Linitrd		# addr of ramdisk
175	st	%r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12)
176	bas	%r14,.Lloader		# load ramdisk
177	st	%r2,INITRD_SIZE+ARCH_OFFSET-PARMAREA(%r12) # store size of rd
178	ltr	%r2,%r2
179	bnz	.Lrdcont
180	st	%r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) # no ramdisk found
181.Lrdcont:
182	l	%r2,.Linitrd
183
184	clc	0(3,%r2),.L_hdr		# skip HDRx and EOFx
185	bz	.Lagain2
186	clc	0(3,%r2),.L_eof
187	bz	.Lagain2
188
189#
190# reset files in VM reader
191#
192	stidp	.Lcpuid			# store cpuid
193	tm	.Lcpuid,0xff		# running VM ?
194	bno	.Lnoreset
195	la	%r2,.Lreset
196	lhi	%r3,26
197	diag	%r2,%r3,8
198	la	%r5,.Lirb
199	stsch	0(%r5)			# check if irq is pending
200	tm	30(%r5),0x0f		# by verifying if any of the
201	bnz	.Lwaitforirq		# activity or status control
202	tm	31(%r5),0xff		# bits is set in the schib
203	bz	.Lnoreset
204.Lwaitforirq:
205	bas	%r14,.Lirqwait		# wait for IO interrupt
206	c	%r1,__LC_SUBCHANNEL_ID	# compare subchannel number
207	bne	.Lwaitforirq
208	la	%r5,.Lirb
209	tsch	0(%r5)
210.Lnoreset:
211	b	.Lnoload
212
213#
214# everything loaded, go for it
215#
216.Lnoload:
217	l	%r1,.Lstartup
218	br	%r1
219
220.Linitrd:.long _end			# default address of initrd
221.Lparm:	.long  PARMAREA
222.Lstartup: .long startup
223.Lreset:.byte	0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40
224	.byte	0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6
225	.byte	0xc8,0xd6,0xd3,0xc4	# "change rdr all keep nohold"
226.L_eof: .long	0xc5d6c600	 /* C'EOF' */
227.L_hdr: .long	0xc8c4d900	 /* C'HDR' */
228	.align	8
229.Lcpuid:.fill	8,1,0
230
231#
232# normal startup-code, running in absolute addressing mode
233# this is called either by the ipl loader or directly by PSW restart
234# or linload or SALIPL
235#
236	.org	STARTUP_NORMAL_OFFSET - IPL_START
237SYM_CODE_START(startup)
238	j	startup_normal
239	.org	EP_OFFSET - IPL_START
240#
241# This is a list of s390 kernel entry points. At address 0x1000f the number of
242# valid entry points is stored.
243#
244# IMPORTANT: Do not change this table, it is s390 kernel ABI!
245#
246	.ascii	EP_STRING
247	.byte	0x00,0x01
248#
249# kdump startup-code, running in 64 bit absolute addressing mode
250#
251	.org	STARTUP_KDUMP_OFFSET - IPL_START
252	j	startup_kdump
253SYM_CODE_END(startup)
254SYM_CODE_START_LOCAL(startup_normal)
255	mvi	__LC_AR_MODE_ID,1	# set esame flag
256	slr	%r0,%r0 		# set cpuid to zero
257	lhi	%r1,2			# mode 2 = esame (dump)
258	sigp	%r1,%r0,0x12		# switch to esame mode
259	bras	%r13,0f
260	.fill	16,4,0x0
2610:	lmh	%r0,%r15,0(%r13)	# clear high-order half of gprs
262	sam64				# switch to 64 bit addressing mode
263	basr	%r13,0			# get base
264.LPG0:
265	mvc	__LC_EXT_NEW_PSW(16),.Lext_new_psw-.LPG0(%r13)
266	mvc	__LC_PGM_NEW_PSW(16),.Lpgm_new_psw-.LPG0(%r13)
267	mvc	__LC_IO_NEW_PSW(16),.Lio_new_psw-.LPG0(%r13)
268	xc	0x200(256),0x200	# partially clear lowcore
269	xc	0x300(256),0x300
270	xc	0xe00(256),0xe00
271	xc	0xf00(256),0xf00
272	lctlg	%c0,%c15,.Lctl-.LPG0(%r13)	# load control registers
273	stcke	__LC_BOOT_CLOCK
274	mvc	__LC_LAST_UPDATE_CLOCK(8),__LC_BOOT_CLOCK+1
275	spt	6f-.LPG0(%r13)
276	mvc	__LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13)
277	larl	%r15,_stack_end-STACK_FRAME_OVERHEAD
278	brasl	%r14,sclp_early_setup_buffer
279	brasl	%r14,verify_facilities
280	brasl	%r14,startup_kernel
281SYM_CODE_END(startup_normal)
282
283	.align	8
2846:	.long	0x7fffffff,0xffffffff
285.Lext_new_psw:
286	.quad	0x0002000180000000,0x1b0	# disabled wait
287.Lpgm_new_psw:
288	.quad	0x0000000180000000,startup_pgm_check_handler
289.Lio_new_psw:
290	.quad	0x0002000180000000,0x1f0	# disabled wait
291.Lctl:	.quad	0x04040000		# cr0: AFP registers & secondary space
292	.quad	0			# cr1: primary space segment table
293	.quad	0			# cr2: dispatchable unit control table
294	.quad	0			# cr3: instruction authorization
295	.quad	0xffff			# cr4: instruction authorization
296	.quad	0			# cr5: primary-aste origin
297	.quad	0			# cr6:	I/O interrupts
298	.quad	0			# cr7:	secondary space segment table
299	.quad	0x0000000000008000	# cr8:	access registers translation
300	.quad	0			# cr9:	tracing off
301	.quad	0			# cr10: tracing off
302	.quad	0			# cr11: tracing off
303	.quad	0			# cr12: tracing off
304	.quad	0			# cr13: home space segment table
305	.quad	0xc0000000		# cr14: machine check handling off
306	.quad	0			# cr15: linkage stack operations
307
308#include "head_kdump.S"
309
310#
311# This program check is active immediately after kernel start
312# and until early_pgm_check_handler is set in kernel/early.c
313# It simply saves general/control registers and psw in
314# the save area and does disabled wait with a faulty address.
315#
316SYM_CODE_START_LOCAL(startup_pgm_check_handler)
317	stmg	%r8,%r15,__LC_SAVE_AREA_SYNC
318	la	%r8,4095
319	stctg	%c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8)
320	stmg	%r0,%r7,__LC_GPREGS_SAVE_AREA-4095(%r8)
321	mvc	__LC_GPREGS_SAVE_AREA-4095+64(64,%r8),__LC_SAVE_AREA_SYNC
322	mvc	__LC_PSW_SAVE_AREA-4095(16,%r8),__LC_PGM_OLD_PSW
323	mvc	__LC_RETURN_PSW(16),__LC_PGM_OLD_PSW
324	ni	__LC_RETURN_PSW,0xfc	# remove IO and EX bits
325	ni	__LC_RETURN_PSW+1,0xfb	# remove MCHK bit
326	oi	__LC_RETURN_PSW+1,0x2	# set wait state bit
327	larl	%r9,.Lold_psw_disabled_wait
328	stg	%r9,__LC_PGM_NEW_PSW+8
329	larl	%r15,_dump_info_stack_end-STACK_FRAME_OVERHEAD
330	brasl	%r14,print_pgm_check_info
331.Lold_psw_disabled_wait:
332	la	%r8,4095
333	lmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r8)
334	lpswe	__LC_RETURN_PSW		# disabled wait
335SYM_CODE_END(startup_pgm_check_handler)
336