1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright IBM Corp. 1999, 2010 4 * 5 * Author(s): Hartmut Penner <hp@de.ibm.com> 6 * Martin Schwidefsky <schwidefsky@de.ibm.com> 7 * Rob van der Heij <rvdhei@iae.nl> 8 * 9 * There are 5 different IPL methods 10 * 1) load the image directly into ram at address 0 and do an PSW restart 11 * 2) linload will load the image from address 0x10000 to memory 0x10000 12 * and start the code thru LPSW 0x0008000080010000 (VM only, deprecated) 13 * 3) generate the tape ipl header, store the generated image on a tape 14 * and ipl from it 15 * In case of SL tape you need to IPL 5 times to get past VOL1 etc 16 * 4) generate the vm reader ipl header, move the generated image to the 17 * VM reader (use option NOH!) and do a ipl from reader (VM only) 18 * 5) direct call of start by the SALIPL loader 19 * We use the cpuid to distinguish between VM and native ipl 20 * params for kernel are pushed to 0x10400 (see setup.h) 21 * 22 */ 23 24#include <linux/init.h> 25#include <linux/linkage.h> 26#include <asm/asm-offsets.h> 27#include <asm/page.h> 28#include <asm/ptrace.h> 29#include <asm/sclp.h> 30 31#define ARCH_OFFSET 4 32 33#define EP_OFFSET 0x10008 34#define EP_STRING "S390EP" 35 36#define IPL_START 0x200 37 38__HEAD 39 40#define IPL_BS 0x730 41 .org 0 42 .long 0x00080000,0x80000000+IPL_START # The first 24 bytes are loaded 43 .long 0x02000018,0x60000050 # by ipl to addresses 0-23. 44 .long 0x02000068,0x60000050 # (a PSW and two CCWs). 45 .fill 80-24,1,0x40 # bytes 24-79 are discarded !! 46 .long 0x020000f0,0x60000050 # The next 160 byte are loaded 47 .long 0x02000140,0x60000050 # to addresses 0x18-0xb7 48 .long 0x02000190,0x60000050 # They form the continuation 49 .long 0x020001e0,0x60000050 # of the CCW program started 50 .long 0x02000230,0x60000050 # by ipl and load the range 51 .long 0x02000280,0x60000050 # 0x0f0-0x730 from the image 52 .long 0x020002d0,0x60000050 # to the range 0x0f0-0x730 53 .long 0x02000320,0x60000050 # in memory. At the end of 54 .long 0x02000370,0x60000050 # the channel program the PSW 55 .long 0x020003c0,0x60000050 # at location 0 is loaded. 56 .long 0x02000410,0x60000050 # Initial processing starts 57 .long 0x02000460,0x60000050 # at 0x200 = iplstart. 58 .long 0x020004b0,0x60000050 59 .long 0x02000500,0x60000050 60 .long 0x02000550,0x60000050 61 .long 0x020005a0,0x60000050 62 .long 0x020005f0,0x60000050 63 .long 0x02000640,0x60000050 64 .long 0x02000690,0x60000050 65 .long 0x020006e0,0x20000050 66 67# The restart psw points to ipl_entry, which allows to load a kernel image 68# into memory and starting it by a psw restart on any cpu. 69# All other default psw new locations contain a disabled wait psw where the 70# address indicates which psw was loaded. 71 .org __LC_RST_NEW_PSW 72 .quad 0,IPL_START 73 .org __LC_EXT_NEW_PSW 74 .quad 0x0002000180000000,__LC_EXT_NEW_PSW 75 .org __LC_SVC_NEW_PSW 76 .quad 0x0002000180000000,__LC_SVC_NEW_PSW 77 .org __LC_PGM_NEW_PSW 78 .quad 0x0002000180000000,__LC_PGM_NEW_PSW 79 .org __LC_MCK_NEW_PSW 80 .quad 0x0002000180000000,__LC_MCK_NEW_PSW 81 .org __LC_IO_NEW_PSW 82 .quad 0x0002000180000000,__LC_IO_NEW_PSW 83 84 .org IPL_START 85ipl_start: 86 j .Liplcont 87# 88# subroutine to wait for end I/O 89# 90.Lirqwait: 91 mvc __LC_IO_NEW_PSW(16),.Lnewpsw # set up IO interrupt psw 92 lpsw .Lwaitpsw 93.Lioint: 94 br %r14 95 .align 8 96.Lnewpsw: 97 .quad 0x0000000080000000,.Lioint 98.Lwaitpsw: 99 .long 0x020a0000,0x80000000+.Lioint 100 101# 102# subroutine for loading cards from the reader 103# 104.Lloader: 105 la %r4,0(%r14) 106 la %r3,.Lorb # r2 = address of orb into r2 107 la %r5,.Lirb # r4 = address of irb 108 la %r6,.Lccws 109 la %r7,20 110.Linit: 111 st %r2,4(%r6) # initialize CCW data addresses 112 la %r2,0x50(%r2) 113 la %r6,8(%r6) 114 bct 7,.Linit 115 116 lctl %c6,%c6,.Lcr6 # set IO subclass mask 117 slr %r2,%r2 118.Lldlp: 119 ssch 0(%r3) # load chunk of 1600 bytes 120 bnz .Llderr 121.Lwait4irq: 122 bas %r14,.Lirqwait 123 c %r1,__LC_SUBCHANNEL_ID # compare subchannel number 124 bne .Lwait4irq 125 tsch 0(%r5) 126 127 slr %r0,%r0 128 ic %r0,8(%r5) # get device status 129 chi %r0,8 # channel end ? 130 be .Lcont 131 chi %r0,12 # channel end + device end ? 132 be .Lcont 133 134 l %r0,4(%r5) 135 s %r0,8(%r3) # r0/8 = number of ccws executed 136 mhi %r0,10 # *10 = number of bytes in ccws 137 lh %r3,10(%r5) # get residual count 138 sr %r0,%r3 # #ccws*80-residual=#bytes read 139 ar %r2,%r0 140 141 br %r4 # r2 contains the total size 142 143.Lcont: 144 ahi %r2,0x640 # add 0x640 to total size 145 la %r6,.Lccws 146 la %r7,20 147.Lincr: 148 l %r0,4(%r6) # update CCW data addresses 149 ahi %r0,0x640 150 st %r0,4(%r6) 151 ahi %r6,8 152 bct 7,.Lincr 153 154 b .Lldlp 155.Llderr: 156 lpsw .Lcrash 157 158 .align 8 159.Lorb: .long 0x00000000,0x0080ff00,.Lccws 160.Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 161.Lcr6: .long 0xff000000 162.Lloadp:.long 0,0 163 .align 8 164.Lcrash:.long 0x000a0000,0x00000000 165 166 .align 8 167.Lccws: .rept 19 168 .long 0x02600050,0x00000000 169 .endr 170 .long 0x02200050,0x00000000 171 172.Liplcont: 173 mvi __LC_AR_MODE_ID,1 # set esame flag 174 slr %r0,%r0 # set cpuid to zero 175 lhi %r1,2 # mode 2 = esame (dump) 176 sigp %r1,%r0,0x12 # switch to esame mode 177 bras %r13,0f 178 .fill 16,4,0x0 1790: lmh %r0,%r15,0(%r13) # clear high-order half of gprs 180 sam31 # switch to 31 bit addressing mode 181 lh %r1,__LC_SUBCHANNEL_ID # test if subchannel number 182 bct %r1,.Lnoload # is valid 183 l %r1,__LC_SUBCHANNEL_ID # load ipl subchannel number 184 la %r2,IPL_BS # load start address 185 bas %r14,.Lloader # load rest of ipl image 186 l %r12,.Lparm # pointer to parameter area 187 st %r1,IPL_DEVICE+ARCH_OFFSET-PARMAREA(%r12) # save ipl device number 188 189# 190# load parameter file from ipl device 191# 192.Lagain1: 193 l %r2,.Linitrd # ramdisk loc. is temp 194 bas %r14,.Lloader # load parameter file 195 ltr %r2,%r2 # got anything ? 196 bz .Lnopf 197 l %r3,MAX_COMMAND_LINE_SIZE+ARCH_OFFSET-PARMAREA(%r12) 198 ahi %r3,-1 199 clr %r2,%r3 200 bl .Lnotrunc 201 lr %r2,%r3 202.Lnotrunc: 203 l %r4,.Linitrd 204 clc 0(3,%r4),.L_hdr # if it is HDRx 205 bz .Lagain1 # skip dataset header 206 clc 0(3,%r4),.L_eof # if it is EOFx 207 bz .Lagain1 # skip dateset trailer 208 209 lr %r5,%r2 210 la %r6,COMMAND_LINE-PARMAREA(%r12) 211 lr %r7,%r2 212 ahi %r7,1 213 mvcl %r6,%r4 214.Lnopf: 215 216# 217# load ramdisk from ipl device 218# 219.Lagain2: 220 l %r2,.Linitrd # addr of ramdisk 221 st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) 222 bas %r14,.Lloader # load ramdisk 223 st %r2,INITRD_SIZE+ARCH_OFFSET-PARMAREA(%r12) # store size of rd 224 ltr %r2,%r2 225 bnz .Lrdcont 226 st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) # no ramdisk found 227.Lrdcont: 228 l %r2,.Linitrd 229 230 clc 0(3,%r2),.L_hdr # skip HDRx and EOFx 231 bz .Lagain2 232 clc 0(3,%r2),.L_eof 233 bz .Lagain2 234 235# 236# reset files in VM reader 237# 238 stidp .Lcpuid # store cpuid 239 tm .Lcpuid,0xff # running VM ? 240 bno .Lnoreset 241 la %r2,.Lreset 242 lhi %r3,26 243 diag %r2,%r3,8 244 la %r5,.Lirb 245 stsch 0(%r5) # check if irq is pending 246 tm 30(%r5),0x0f # by verifying if any of the 247 bnz .Lwaitforirq # activity or status control 248 tm 31(%r5),0xff # bits is set in the schib 249 bz .Lnoreset 250.Lwaitforirq: 251 bas %r14,.Lirqwait # wait for IO interrupt 252 c %r1,__LC_SUBCHANNEL_ID # compare subchannel number 253 bne .Lwaitforirq 254 la %r5,.Lirb 255 tsch 0(%r5) 256.Lnoreset: 257 b .Lnoload 258 259# 260# everything loaded, go for it 261# 262.Lnoload: 263 l %r1,.Lstartup 264 br %r1 265 266.Linitrd:.long _end # default address of initrd 267.Lparm: .long PARMAREA 268.Lstartup: .long startup 269.Lreset:.byte 0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40 270 .byte 0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6 271 .byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold" 272.L_eof: .long 0xc5d6c600 /* C'EOF' */ 273.L_hdr: .long 0xc8c4d900 /* C'HDR' */ 274 .align 8 275.Lcpuid:.fill 8,1,0 276 277# 278# normal startup-code, running in absolute addressing mode 279# this is called either by the ipl loader or directly by PSW restart 280# or linload or SALIPL 281# 282 .org STARTUP_NORMAL_OFFSET 283SYM_CODE_START(startup) 284 j startup_normal 285 .org EP_OFFSET 286# 287# This is a list of s390 kernel entry points. At address 0x1000f the number of 288# valid entry points is stored. 289# 290# IMPORTANT: Do not change this table, it is s390 kernel ABI! 291# 292 .ascii EP_STRING 293 .byte 0x00,0x01 294# 295# kdump startup-code, running in 64 bit absolute addressing mode 296# 297 .org STARTUP_KDUMP_OFFSET 298 j startup_kdump 299SYM_CODE_END(startup) 300SYM_CODE_START_LOCAL(startup_normal) 301 mvi __LC_AR_MODE_ID,1 # set esame flag 302 slr %r0,%r0 # set cpuid to zero 303 lhi %r1,2 # mode 2 = esame (dump) 304 sigp %r1,%r0,0x12 # switch to esame mode 305 bras %r13,0f 306 .fill 16,4,0x0 3070: lmh %r0,%r15,0(%r13) # clear high-order half of gprs 308 sam64 # switch to 64 bit addressing mode 309 basr %r13,0 # get base 310.LPG0: 311 mvc __LC_EXT_NEW_PSW(16),.Lext_new_psw-.LPG0(%r13) 312 mvc __LC_PGM_NEW_PSW(16),.Lpgm_new_psw-.LPG0(%r13) 313 mvc __LC_IO_NEW_PSW(16),.Lio_new_psw-.LPG0(%r13) 314 xc 0x200(256),0x200 # partially clear lowcore 315 xc 0x300(256),0x300 316 xc 0xe00(256),0xe00 317 xc 0xf00(256),0xf00 318 lctlg %c0,%c15,.Lctl-.LPG0(%r13) # load control registers 319 stcke __LC_BOOT_CLOCK 320 mvc __LC_LAST_UPDATE_CLOCK(8),__LC_BOOT_CLOCK+1 321 spt 6f-.LPG0(%r13) 322 mvc __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13) 323 larl %r15,_stack_end-STACK_FRAME_OVERHEAD 324 brasl %r14,sclp_early_setup_buffer 325 brasl %r14,verify_facilities 326 brasl %r14,startup_kernel 327SYM_CODE_END(startup_normal) 328 329 .align 8 3306: .long 0x7fffffff,0xffffffff 331.Lext_new_psw: 332 .quad 0x0002000180000000,0x1b0 # disabled wait 333.Lpgm_new_psw: 334 .quad 0x0000000180000000,startup_pgm_check_handler 335.Lio_new_psw: 336 .quad 0x0002000180000000,0x1f0 # disabled wait 337.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space 338 .quad 0 # cr1: primary space segment table 339 .quad 0 # cr2: dispatchable unit control table 340 .quad 0 # cr3: instruction authorization 341 .quad 0xffff # cr4: instruction authorization 342 .quad 0 # cr5: primary-aste origin 343 .quad 0 # cr6: I/O interrupts 344 .quad 0 # cr7: secondary space segment table 345 .quad 0x0000000000008000 # cr8: access registers translation 346 .quad 0 # cr9: tracing off 347 .quad 0 # cr10: tracing off 348 .quad 0 # cr11: tracing off 349 .quad 0 # cr12: tracing off 350 .quad 0 # cr13: home space segment table 351 .quad 0xc0000000 # cr14: machine check handling off 352 .quad 0 # cr15: linkage stack operations 353 354#include "head_kdump.S" 355 356# 357# This program check is active immediately after kernel start 358# and until early_pgm_check_handler is set in kernel/early.c 359# It simply saves general/control registers and psw in 360# the save area and does disabled wait with a faulty address. 361# 362SYM_CODE_START_LOCAL(startup_pgm_check_handler) 363 stmg %r8,%r15,__LC_SAVE_AREA_SYNC 364 la %r8,4095 365 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8) 366 stmg %r0,%r7,__LC_GPREGS_SAVE_AREA-4095(%r8) 367 mvc __LC_GPREGS_SAVE_AREA-4095+64(64,%r8),__LC_SAVE_AREA_SYNC 368 mvc __LC_PSW_SAVE_AREA-4095(16,%r8),__LC_PGM_OLD_PSW 369 mvc __LC_RETURN_PSW(16),__LC_PGM_OLD_PSW 370 ni __LC_RETURN_PSW,0xfc # remove IO and EX bits 371 ni __LC_RETURN_PSW+1,0xfb # remove MCHK bit 372 oi __LC_RETURN_PSW+1,0x2 # set wait state bit 373 larl %r9,.Lold_psw_disabled_wait 374 stg %r9,__LC_PGM_NEW_PSW+8 375 larl %r15,_dump_info_stack_end-STACK_FRAME_OVERHEAD 376 brasl %r14,print_pgm_check_info 377.Lold_psw_disabled_wait: 378 la %r8,4095 379 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r8) 380 lpswe __LC_RETURN_PSW # disabled wait 381SYM_CODE_END(startup_pgm_check_handler) 382 383# 384# params at 10400 (setup.h) 385# Must be keept in sync with struct parmarea in setup.h 386# 387 .org PARMAREA 388SYM_DATA_START(parmarea) 389 .quad 0 # IPL_DEVICE 390 .quad 0 # INITRD_START 391 .quad 0 # INITRD_SIZE 392 .quad 0 # OLDMEM_BASE 393 .quad 0 # OLDMEM_SIZE 394 .quad kernel_version # points to kernel version string 395 .quad COMMAND_LINE_SIZE 396 397 .org COMMAND_LINE 398 .byte "root=/dev/ram0 ro" 399 .byte 0 400 .org PARMAREA+__PARMAREA_SIZE 401SYM_DATA_END(parmarea) 402