1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright IBM Corp. 1999, 2010 4 * 5 * Author(s): Hartmut Penner <hp@de.ibm.com> 6 * Martin Schwidefsky <schwidefsky@de.ibm.com> 7 * Rob van der Heij <rvdhei@iae.nl> 8 * 9 * There are 5 different IPL methods 10 * 1) load the image directly into ram at address 0 and do an PSW restart 11 * 2) linload will load the image from address 0x10000 to memory 0x10000 12 * and start the code thru LPSW 0x0008000080010000 (VM only, deprecated) 13 * 3) generate the tape ipl header, store the generated image on a tape 14 * and ipl from it 15 * In case of SL tape you need to IPL 5 times to get past VOL1 etc 16 * 4) generate the vm reader ipl header, move the generated image to the 17 * VM reader (use option NOH!) and do a ipl from reader (VM only) 18 * 5) direct call of start by the SALIPL loader 19 * We use the cpuid to distinguish between VM and native ipl 20 * params for kernel are pushed to 0x10400 (see setup.h) 21 * 22 */ 23 24#include <linux/init.h> 25#include <linux/linkage.h> 26#include <asm/asm-offsets.h> 27#include <asm/page.h> 28#include <asm/ptrace.h> 29#include <asm/sclp.h> 30 31#define ARCH_OFFSET 4 32 33#define EP_OFFSET 0x10008 34#define EP_STRING "S390EP" 35 36#define IPL_START 0x200 37 38__HEAD 39 40#define IPL_BS 0x730 41 .org 0 42 .long 0x00080000,0x80000000+IPL_START # The first 24 bytes are loaded 43 .long 0x02000018,0x60000050 # by ipl to addresses 0-23. 44 .long 0x02000068,0x60000050 # (a PSW and two CCWs). 45 .fill 80-24,1,0x40 # bytes 24-79 are discarded !! 46 .long 0x020000f0,0x60000050 # The next 160 byte are loaded 47 .long 0x02000140,0x60000050 # to addresses 0x18-0xb7 48 .long 0x02000190,0x60000050 # They form the continuation 49 .long 0x020001e0,0x60000050 # of the CCW program started 50 .long 0x02000230,0x60000050 # by ipl and load the range 51 .long 0x02000280,0x60000050 # 0x0f0-0x730 from the image 52 .long 0x020002d0,0x60000050 # to the range 0x0f0-0x730 53 .long 0x02000320,0x60000050 # in memory. At the end of 54 .long 0x02000370,0x60000050 # the channel program the PSW 55 .long 0x020003c0,0x60000050 # at location 0 is loaded. 56 .long 0x02000410,0x60000050 # Initial processing starts 57 .long 0x02000460,0x60000050 # at 0x200 = iplstart. 58 .long 0x020004b0,0x60000050 59 .long 0x02000500,0x60000050 60 .long 0x02000550,0x60000050 61 .long 0x020005a0,0x60000050 62 .long 0x020005f0,0x60000050 63 .long 0x02000640,0x60000050 64 .long 0x02000690,0x60000050 65 .long 0x020006e0,0x20000050 66 67 .org __LC_RST_NEW_PSW # 0x1a0 68 .quad 0,IPL_START 69 .org __LC_EXT_NEW_PSW # 0x1b0 70 .quad 0x0002000180000000,0x1b0 # disabled wait 71 .org __LC_PGM_NEW_PSW # 0x1d0 72 .quad 0x0000000180000000,startup_pgm_check_handler 73 .org __LC_IO_NEW_PSW # 0x1f0 74 .quad 0x0002000180000000,0x1f0 # disabled wait 75 76 .org IPL_START 77ipl_start: 78 j .Liplcont 79# 80# subroutine to wait for end I/O 81# 82.Lirqwait: 83 mvc __LC_IO_NEW_PSW(16),.Lnewpsw # set up IO interrupt psw 84 lpsw .Lwaitpsw 85.Lioint: 86 br %r14 87 .align 8 88.Lnewpsw: 89 .quad 0x0000000080000000,.Lioint 90.Lwaitpsw: 91 .long 0x020a0000,0x80000000+.Lioint 92 93# 94# subroutine for loading cards from the reader 95# 96.Lloader: 97 la %r4,0(%r14) 98 la %r3,.Lorb # r2 = address of orb into r2 99 la %r5,.Lirb # r4 = address of irb 100 la %r6,.Lccws 101 la %r7,20 102.Linit: 103 st %r2,4(%r6) # initialize CCW data addresses 104 la %r2,0x50(%r2) 105 la %r6,8(%r6) 106 bct 7,.Linit 107 108 lctl %c6,%c6,.Lcr6 # set IO subclass mask 109 slr %r2,%r2 110.Lldlp: 111 ssch 0(%r3) # load chunk of 1600 bytes 112 bnz .Llderr 113.Lwait4irq: 114 bas %r14,.Lirqwait 115 c %r1,__LC_SUBCHANNEL_ID # compare subchannel number 116 bne .Lwait4irq 117 tsch 0(%r5) 118 119 slr %r0,%r0 120 ic %r0,8(%r5) # get device status 121 chi %r0,8 # channel end ? 122 be .Lcont 123 chi %r0,12 # channel end + device end ? 124 be .Lcont 125 126 l %r0,4(%r5) 127 s %r0,8(%r3) # r0/8 = number of ccws executed 128 mhi %r0,10 # *10 = number of bytes in ccws 129 lh %r3,10(%r5) # get residual count 130 sr %r0,%r3 # #ccws*80-residual=#bytes read 131 ar %r2,%r0 132 133 br %r4 # r2 contains the total size 134 135.Lcont: 136 ahi %r2,0x640 # add 0x640 to total size 137 la %r6,.Lccws 138 la %r7,20 139.Lincr: 140 l %r0,4(%r6) # update CCW data addresses 141 ahi %r0,0x640 142 st %r0,4(%r6) 143 ahi %r6,8 144 bct 7,.Lincr 145 146 b .Lldlp 147.Llderr: 148 lpsw .Lcrash 149 150 .align 8 151.Lorb: .long 0x00000000,0x0080ff00,.Lccws 152.Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 153.Lcr6: .long 0xff000000 154.Lloadp:.long 0,0 155 .align 8 156.Lcrash:.long 0x000a0000,0x00000000 157 158 .align 8 159.Lccws: .rept 19 160 .long 0x02600050,0x00000000 161 .endr 162 .long 0x02200050,0x00000000 163 164.Liplcont: 165 mvi __LC_AR_MODE_ID,1 # set esame flag 166 slr %r0,%r0 # set cpuid to zero 167 lhi %r1,2 # mode 2 = esame (dump) 168 sigp %r1,%r0,0x12 # switch to esame mode 169 bras %r13,0f 170 .fill 16,4,0x0 1710: lmh %r0,%r15,0(%r13) # clear high-order half of gprs 172 sam31 # switch to 31 bit addressing mode 173 lh %r1,__LC_SUBCHANNEL_ID # test if subchannel number 174 bct %r1,.Lnoload # is valid 175 l %r1,__LC_SUBCHANNEL_ID # load ipl subchannel number 176 la %r2,IPL_BS # load start address 177 bas %r14,.Lloader # load rest of ipl image 178 l %r12,.Lparm # pointer to parameter area 179 st %r1,IPL_DEVICE+ARCH_OFFSET-PARMAREA(%r12) # save ipl device number 180 181# 182# load parameter file from ipl device 183# 184.Lagain1: 185 l %r2,.Linitrd # ramdisk loc. is temp 186 bas %r14,.Lloader # load parameter file 187 ltr %r2,%r2 # got anything ? 188 bz .Lnopf 189 l %r3,MAX_COMMAND_LINE_SIZE+ARCH_OFFSET-PARMAREA(%r12) 190 ahi %r3,-1 191 clr %r2,%r3 192 bl .Lnotrunc 193 lr %r2,%r3 194.Lnotrunc: 195 l %r4,.Linitrd 196 clc 0(3,%r4),.L_hdr # if it is HDRx 197 bz .Lagain1 # skip dataset header 198 clc 0(3,%r4),.L_eof # if it is EOFx 199 bz .Lagain1 # skip dateset trailer 200 201 lr %r5,%r2 202 la %r6,COMMAND_LINE-PARMAREA(%r12) 203 lr %r7,%r2 204 ahi %r7,1 205 mvcl %r6,%r4 206.Lnopf: 207 208# 209# load ramdisk from ipl device 210# 211.Lagain2: 212 l %r2,.Linitrd # addr of ramdisk 213 st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) 214 bas %r14,.Lloader # load ramdisk 215 st %r2,INITRD_SIZE+ARCH_OFFSET-PARMAREA(%r12) # store size of rd 216 ltr %r2,%r2 217 bnz .Lrdcont 218 st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) # no ramdisk found 219.Lrdcont: 220 l %r2,.Linitrd 221 222 clc 0(3,%r2),.L_hdr # skip HDRx and EOFx 223 bz .Lagain2 224 clc 0(3,%r2),.L_eof 225 bz .Lagain2 226 227# 228# reset files in VM reader 229# 230 stidp .Lcpuid # store cpuid 231 tm .Lcpuid,0xff # running VM ? 232 bno .Lnoreset 233 la %r2,.Lreset 234 lhi %r3,26 235 diag %r2,%r3,8 236 la %r5,.Lirb 237 stsch 0(%r5) # check if irq is pending 238 tm 30(%r5),0x0f # by verifying if any of the 239 bnz .Lwaitforirq # activity or status control 240 tm 31(%r5),0xff # bits is set in the schib 241 bz .Lnoreset 242.Lwaitforirq: 243 bas %r14,.Lirqwait # wait for IO interrupt 244 c %r1,__LC_SUBCHANNEL_ID # compare subchannel number 245 bne .Lwaitforirq 246 la %r5,.Lirb 247 tsch 0(%r5) 248.Lnoreset: 249 b .Lnoload 250 251# 252# everything loaded, go for it 253# 254.Lnoload: 255 l %r1,.Lstartup 256 br %r1 257 258.Linitrd:.long _end # default address of initrd 259.Lparm: .long PARMAREA 260.Lstartup: .long startup 261.Lreset:.byte 0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40 262 .byte 0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6 263 .byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold" 264.L_eof: .long 0xc5d6c600 /* C'EOF' */ 265.L_hdr: .long 0xc8c4d900 /* C'HDR' */ 266 .align 8 267.Lcpuid:.fill 8,1,0 268 269# 270# normal startup-code, running in absolute addressing mode 271# this is called either by the ipl loader or directly by PSW restart 272# or linload or SALIPL 273# 274 .org STARTUP_NORMAL_OFFSET 275SYM_CODE_START(startup) 276 j startup_normal 277 .org EP_OFFSET 278# 279# This is a list of s390 kernel entry points. At address 0x1000f the number of 280# valid entry points is stored. 281# 282# IMPORTANT: Do not change this table, it is s390 kernel ABI! 283# 284 .ascii EP_STRING 285 .byte 0x00,0x01 286# 287# kdump startup-code, running in 64 bit absolute addressing mode 288# 289 .org STARTUP_KDUMP_OFFSET 290 j startup_kdump 291SYM_CODE_END(startup) 292SYM_CODE_START_LOCAL(startup_normal) 293 mvi __LC_AR_MODE_ID,1 # set esame flag 294 slr %r0,%r0 # set cpuid to zero 295 lhi %r1,2 # mode 2 = esame (dump) 296 sigp %r1,%r0,0x12 # switch to esame mode 297 bras %r13,0f 298 .fill 16,4,0x0 2990: lmh %r0,%r15,0(%r13) # clear high-order half of gprs 300 sam64 # switch to 64 bit addressing mode 301 basr %r13,0 # get base 302.LPG0: 303 mvc __LC_EXT_NEW_PSW(16),.Lext_new_psw-.LPG0(%r13) 304 mvc __LC_PGM_NEW_PSW(16),.Lpgm_new_psw-.LPG0(%r13) 305 mvc __LC_IO_NEW_PSW(16),.Lio_new_psw-.LPG0(%r13) 306 xc 0x200(256),0x200 # partially clear lowcore 307 xc 0x300(256),0x300 308 xc 0xe00(256),0xe00 309 xc 0xf00(256),0xf00 310 lctlg %c0,%c15,.Lctl-.LPG0(%r13) # load control registers 311 stcke __LC_BOOT_CLOCK 312 mvc __LC_LAST_UPDATE_CLOCK(8),__LC_BOOT_CLOCK+1 313 spt 6f-.LPG0(%r13) 314 mvc __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13) 315 larl %r15,_stack_end-STACK_FRAME_OVERHEAD 316 brasl %r14,sclp_early_setup_buffer 317 brasl %r14,verify_facilities 318 brasl %r14,startup_kernel 319SYM_CODE_END(startup_normal) 320 321 .align 8 3226: .long 0x7fffffff,0xffffffff 323.Lext_new_psw: 324 .quad 0x0002000180000000,0x1b0 # disabled wait 325.Lpgm_new_psw: 326 .quad 0x0000000180000000,startup_pgm_check_handler 327.Lio_new_psw: 328 .quad 0x0002000180000000,0x1f0 # disabled wait 329.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space 330 .quad 0 # cr1: primary space segment table 331 .quad 0 # cr2: dispatchable unit control table 332 .quad 0 # cr3: instruction authorization 333 .quad 0xffff # cr4: instruction authorization 334 .quad 0 # cr5: primary-aste origin 335 .quad 0 # cr6: I/O interrupts 336 .quad 0 # cr7: secondary space segment table 337 .quad 0x0000000000008000 # cr8: access registers translation 338 .quad 0 # cr9: tracing off 339 .quad 0 # cr10: tracing off 340 .quad 0 # cr11: tracing off 341 .quad 0 # cr12: tracing off 342 .quad 0 # cr13: home space segment table 343 .quad 0xc0000000 # cr14: machine check handling off 344 .quad 0 # cr15: linkage stack operations 345 346#include "head_kdump.S" 347 348# 349# This program check is active immediately after kernel start 350# and until early_pgm_check_handler is set in kernel/early.c 351# It simply saves general/control registers and psw in 352# the save area and does disabled wait with a faulty address. 353# 354SYM_CODE_START_LOCAL(startup_pgm_check_handler) 355 stmg %r8,%r15,__LC_SAVE_AREA_SYNC 356 la %r8,4095 357 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8) 358 stmg %r0,%r7,__LC_GPREGS_SAVE_AREA-4095(%r8) 359 mvc __LC_GPREGS_SAVE_AREA-4095+64(64,%r8),__LC_SAVE_AREA_SYNC 360 mvc __LC_PSW_SAVE_AREA-4095(16,%r8),__LC_PGM_OLD_PSW 361 mvc __LC_RETURN_PSW(16),__LC_PGM_OLD_PSW 362 ni __LC_RETURN_PSW,0xfc # remove IO and EX bits 363 ni __LC_RETURN_PSW+1,0xfb # remove MCHK bit 364 oi __LC_RETURN_PSW+1,0x2 # set wait state bit 365 larl %r9,.Lold_psw_disabled_wait 366 stg %r9,__LC_PGM_NEW_PSW+8 367 larl %r15,_dump_info_stack_end-STACK_FRAME_OVERHEAD 368 brasl %r14,print_pgm_check_info 369.Lold_psw_disabled_wait: 370 la %r8,4095 371 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r8) 372 lpswe __LC_RETURN_PSW # disabled wait 373SYM_CODE_END(startup_pgm_check_handler) 374 375# 376# params at 10400 (setup.h) 377# Must be keept in sync with struct parmarea in setup.h 378# 379 .org PARMAREA 380SYM_DATA_START(parmarea) 381 .quad 0 # IPL_DEVICE 382 .quad 0 # INITRD_START 383 .quad 0 # INITRD_SIZE 384 .quad 0 # OLDMEM_BASE 385 .quad 0 # OLDMEM_SIZE 386 .quad kernel_version # points to kernel version string 387 .quad COMMAND_LINE_SIZE 388 389 .org COMMAND_LINE 390 .byte "root=/dev/ram0 ro" 391 .byte 0 392 .org PARMAREA+__PARMAREA_SIZE 393SYM_DATA_END(parmarea) 394