1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * RISC-V specific functions to support DMA for non-coherent devices 4 * 5 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 6 */ 7 8 #include <linux/dma-direct.h> 9 #include <linux/dma-map-ops.h> 10 #include <linux/mm.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <asm/cacheflush.h> 14 15 unsigned int riscv_cbom_block_size; 16 EXPORT_SYMBOL_GPL(riscv_cbom_block_size); 17 18 static bool noncoherent_supported; 19 20 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, 21 enum dma_data_direction dir) 22 { 23 void *vaddr = phys_to_virt(paddr); 24 25 switch (dir) { 26 case DMA_TO_DEVICE: 27 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); 28 break; 29 case DMA_FROM_DEVICE: 30 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); 31 break; 32 case DMA_BIDIRECTIONAL: 33 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); 34 break; 35 default: 36 break; 37 } 38 } 39 40 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, 41 enum dma_data_direction dir) 42 { 43 void *vaddr = phys_to_virt(paddr); 44 45 switch (dir) { 46 case DMA_TO_DEVICE: 47 break; 48 case DMA_FROM_DEVICE: 49 case DMA_BIDIRECTIONAL: 50 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); 51 break; 52 default: 53 break; 54 } 55 } 56 57 void arch_dma_prep_coherent(struct page *page, size_t size) 58 { 59 void *flush_addr = page_address(page); 60 61 ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); 62 } 63 64 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, 65 const struct iommu_ops *iommu, bool coherent) 66 { 67 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, 68 TAINT_CPU_OUT_OF_SPEC, 69 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", 70 dev_driver_string(dev), dev_name(dev), 71 ARCH_DMA_MINALIGN, riscv_cbom_block_size); 72 73 WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC, 74 "%s %s: device non-coherent but no non-coherent operations supported", 75 dev_driver_string(dev), dev_name(dev)); 76 77 dev->dma_coherent = coherent; 78 } 79 80 #ifdef CONFIG_RISCV_ISA_ZICBOM 81 void riscv_init_cbom_blocksize(void) 82 { 83 struct device_node *node; 84 unsigned long cbom_hartid; 85 u32 val, probed_block_size; 86 int ret; 87 88 probed_block_size = 0; 89 for_each_of_cpu_node(node) { 90 unsigned long hartid; 91 92 ret = riscv_of_processor_hartid(node, &hartid); 93 if (ret) 94 continue; 95 96 /* set block-size for cbom extension if available */ 97 ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); 98 if (ret) 99 continue; 100 101 if (!probed_block_size) { 102 probed_block_size = val; 103 cbom_hartid = hartid; 104 } else { 105 if (probed_block_size != val) 106 pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", 107 cbom_hartid, hartid); 108 } 109 } 110 111 if (probed_block_size) 112 riscv_cbom_block_size = probed_block_size; 113 } 114 #endif 115 116 void riscv_noncoherent_supported(void) 117 { 118 WARN(!riscv_cbom_block_size, 119 "Non-coherent DMA support enabled without a block size\n"); 120 noncoherent_supported = true; 121 } 122