1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9#include <linux/linkage.h> 10#include <asm/asm.h> 11#include <asm/asm-offsets.h> 12#include <asm/csr.h> 13 14 .text 15 .altmacro 16 .option norelax 17 18ENTRY(__kvm_riscv_switch_to) 19 /* Save Host GPRs (except A0 and T0-T6) */ 20 REG_S ra, (KVM_ARCH_HOST_RA)(a0) 21 REG_S sp, (KVM_ARCH_HOST_SP)(a0) 22 REG_S gp, (KVM_ARCH_HOST_GP)(a0) 23 REG_S tp, (KVM_ARCH_HOST_TP)(a0) 24 REG_S s0, (KVM_ARCH_HOST_S0)(a0) 25 REG_S s1, (KVM_ARCH_HOST_S1)(a0) 26 REG_S a1, (KVM_ARCH_HOST_A1)(a0) 27 REG_S a2, (KVM_ARCH_HOST_A2)(a0) 28 REG_S a3, (KVM_ARCH_HOST_A3)(a0) 29 REG_S a4, (KVM_ARCH_HOST_A4)(a0) 30 REG_S a5, (KVM_ARCH_HOST_A5)(a0) 31 REG_S a6, (KVM_ARCH_HOST_A6)(a0) 32 REG_S a7, (KVM_ARCH_HOST_A7)(a0) 33 REG_S s2, (KVM_ARCH_HOST_S2)(a0) 34 REG_S s3, (KVM_ARCH_HOST_S3)(a0) 35 REG_S s4, (KVM_ARCH_HOST_S4)(a0) 36 REG_S s5, (KVM_ARCH_HOST_S5)(a0) 37 REG_S s6, (KVM_ARCH_HOST_S6)(a0) 38 REG_S s7, (KVM_ARCH_HOST_S7)(a0) 39 REG_S s8, (KVM_ARCH_HOST_S8)(a0) 40 REG_S s9, (KVM_ARCH_HOST_S9)(a0) 41 REG_S s10, (KVM_ARCH_HOST_S10)(a0) 42 REG_S s11, (KVM_ARCH_HOST_S11)(a0) 43 44 /* Save Host and Restore Guest SSTATUS */ 45 REG_L t0, (KVM_ARCH_GUEST_SSTATUS)(a0) 46 csrrw t0, CSR_SSTATUS, t0 47 REG_S t0, (KVM_ARCH_HOST_SSTATUS)(a0) 48 49 /* Save Host and Restore Guest HSTATUS */ 50 REG_L t1, (KVM_ARCH_GUEST_HSTATUS)(a0) 51 csrrw t1, CSR_HSTATUS, t1 52 REG_S t1, (KVM_ARCH_HOST_HSTATUS)(a0) 53 54 /* Save Host and Restore Guest SCOUNTEREN */ 55 REG_L t2, (KVM_ARCH_GUEST_SCOUNTEREN)(a0) 56 csrrw t2, CSR_SCOUNTEREN, t2 57 REG_S t2, (KVM_ARCH_HOST_SCOUNTEREN)(a0) 58 59 /* Save Host SSCRATCH and change it to struct kvm_vcpu_arch pointer */ 60 csrrw t3, CSR_SSCRATCH, a0 61 REG_S t3, (KVM_ARCH_HOST_SSCRATCH)(a0) 62 63 /* Save Host STVEC and change it to return path */ 64 la t4, __kvm_switch_return 65 csrrw t4, CSR_STVEC, t4 66 REG_S t4, (KVM_ARCH_HOST_STVEC)(a0) 67 68 /* Restore Guest SEPC */ 69 REG_L t0, (KVM_ARCH_GUEST_SEPC)(a0) 70 csrw CSR_SEPC, t0 71 72 /* Restore Guest GPRs (except A0) */ 73 REG_L ra, (KVM_ARCH_GUEST_RA)(a0) 74 REG_L sp, (KVM_ARCH_GUEST_SP)(a0) 75 REG_L gp, (KVM_ARCH_GUEST_GP)(a0) 76 REG_L tp, (KVM_ARCH_GUEST_TP)(a0) 77 REG_L t0, (KVM_ARCH_GUEST_T0)(a0) 78 REG_L t1, (KVM_ARCH_GUEST_T1)(a0) 79 REG_L t2, (KVM_ARCH_GUEST_T2)(a0) 80 REG_L s0, (KVM_ARCH_GUEST_S0)(a0) 81 REG_L s1, (KVM_ARCH_GUEST_S1)(a0) 82 REG_L a1, (KVM_ARCH_GUEST_A1)(a0) 83 REG_L a2, (KVM_ARCH_GUEST_A2)(a0) 84 REG_L a3, (KVM_ARCH_GUEST_A3)(a0) 85 REG_L a4, (KVM_ARCH_GUEST_A4)(a0) 86 REG_L a5, (KVM_ARCH_GUEST_A5)(a0) 87 REG_L a6, (KVM_ARCH_GUEST_A6)(a0) 88 REG_L a7, (KVM_ARCH_GUEST_A7)(a0) 89 REG_L s2, (KVM_ARCH_GUEST_S2)(a0) 90 REG_L s3, (KVM_ARCH_GUEST_S3)(a0) 91 REG_L s4, (KVM_ARCH_GUEST_S4)(a0) 92 REG_L s5, (KVM_ARCH_GUEST_S5)(a0) 93 REG_L s6, (KVM_ARCH_GUEST_S6)(a0) 94 REG_L s7, (KVM_ARCH_GUEST_S7)(a0) 95 REG_L s8, (KVM_ARCH_GUEST_S8)(a0) 96 REG_L s9, (KVM_ARCH_GUEST_S9)(a0) 97 REG_L s10, (KVM_ARCH_GUEST_S10)(a0) 98 REG_L s11, (KVM_ARCH_GUEST_S11)(a0) 99 REG_L t3, (KVM_ARCH_GUEST_T3)(a0) 100 REG_L t4, (KVM_ARCH_GUEST_T4)(a0) 101 REG_L t5, (KVM_ARCH_GUEST_T5)(a0) 102 REG_L t6, (KVM_ARCH_GUEST_T6)(a0) 103 104 /* Restore Guest A0 */ 105 REG_L a0, (KVM_ARCH_GUEST_A0)(a0) 106 107 /* Resume Guest */ 108 sret 109 110 /* Back to Host */ 111 .align 2 112__kvm_switch_return: 113 /* Swap Guest A0 with SSCRATCH */ 114 csrrw a0, CSR_SSCRATCH, a0 115 116 /* Save Guest GPRs (except A0) */ 117 REG_S ra, (KVM_ARCH_GUEST_RA)(a0) 118 REG_S sp, (KVM_ARCH_GUEST_SP)(a0) 119 REG_S gp, (KVM_ARCH_GUEST_GP)(a0) 120 REG_S tp, (KVM_ARCH_GUEST_TP)(a0) 121 REG_S t0, (KVM_ARCH_GUEST_T0)(a0) 122 REG_S t1, (KVM_ARCH_GUEST_T1)(a0) 123 REG_S t2, (KVM_ARCH_GUEST_T2)(a0) 124 REG_S s0, (KVM_ARCH_GUEST_S0)(a0) 125 REG_S s1, (KVM_ARCH_GUEST_S1)(a0) 126 REG_S a1, (KVM_ARCH_GUEST_A1)(a0) 127 REG_S a2, (KVM_ARCH_GUEST_A2)(a0) 128 REG_S a3, (KVM_ARCH_GUEST_A3)(a0) 129 REG_S a4, (KVM_ARCH_GUEST_A4)(a0) 130 REG_S a5, (KVM_ARCH_GUEST_A5)(a0) 131 REG_S a6, (KVM_ARCH_GUEST_A6)(a0) 132 REG_S a7, (KVM_ARCH_GUEST_A7)(a0) 133 REG_S s2, (KVM_ARCH_GUEST_S2)(a0) 134 REG_S s3, (KVM_ARCH_GUEST_S3)(a0) 135 REG_S s4, (KVM_ARCH_GUEST_S4)(a0) 136 REG_S s5, (KVM_ARCH_GUEST_S5)(a0) 137 REG_S s6, (KVM_ARCH_GUEST_S6)(a0) 138 REG_S s7, (KVM_ARCH_GUEST_S7)(a0) 139 REG_S s8, (KVM_ARCH_GUEST_S8)(a0) 140 REG_S s9, (KVM_ARCH_GUEST_S9)(a0) 141 REG_S s10, (KVM_ARCH_GUEST_S10)(a0) 142 REG_S s11, (KVM_ARCH_GUEST_S11)(a0) 143 REG_S t3, (KVM_ARCH_GUEST_T3)(a0) 144 REG_S t4, (KVM_ARCH_GUEST_T4)(a0) 145 REG_S t5, (KVM_ARCH_GUEST_T5)(a0) 146 REG_S t6, (KVM_ARCH_GUEST_T6)(a0) 147 148 /* Save Guest SEPC */ 149 csrr t0, CSR_SEPC 150 REG_S t0, (KVM_ARCH_GUEST_SEPC)(a0) 151 152 /* Restore Host STVEC */ 153 REG_L t1, (KVM_ARCH_HOST_STVEC)(a0) 154 csrw CSR_STVEC, t1 155 156 /* Save Guest A0 and Restore Host SSCRATCH */ 157 REG_L t2, (KVM_ARCH_HOST_SSCRATCH)(a0) 158 csrrw t2, CSR_SSCRATCH, t2 159 REG_S t2, (KVM_ARCH_GUEST_A0)(a0) 160 161 /* Save Guest and Restore Host SCOUNTEREN */ 162 REG_L t3, (KVM_ARCH_HOST_SCOUNTEREN)(a0) 163 csrrw t3, CSR_SCOUNTEREN, t3 164 REG_S t3, (KVM_ARCH_GUEST_SCOUNTEREN)(a0) 165 166 /* Save Guest and Restore Host HSTATUS */ 167 REG_L t4, (KVM_ARCH_HOST_HSTATUS)(a0) 168 csrrw t4, CSR_HSTATUS, t4 169 REG_S t4, (KVM_ARCH_GUEST_HSTATUS)(a0) 170 171 /* Save Guest and Restore Host SSTATUS */ 172 REG_L t5, (KVM_ARCH_HOST_SSTATUS)(a0) 173 csrrw t5, CSR_SSTATUS, t5 174 REG_S t5, (KVM_ARCH_GUEST_SSTATUS)(a0) 175 176 /* Restore Host GPRs (except A0 and T0-T6) */ 177 REG_L ra, (KVM_ARCH_HOST_RA)(a0) 178 REG_L sp, (KVM_ARCH_HOST_SP)(a0) 179 REG_L gp, (KVM_ARCH_HOST_GP)(a0) 180 REG_L tp, (KVM_ARCH_HOST_TP)(a0) 181 REG_L s0, (KVM_ARCH_HOST_S0)(a0) 182 REG_L s1, (KVM_ARCH_HOST_S1)(a0) 183 REG_L a1, (KVM_ARCH_HOST_A1)(a0) 184 REG_L a2, (KVM_ARCH_HOST_A2)(a0) 185 REG_L a3, (KVM_ARCH_HOST_A3)(a0) 186 REG_L a4, (KVM_ARCH_HOST_A4)(a0) 187 REG_L a5, (KVM_ARCH_HOST_A5)(a0) 188 REG_L a6, (KVM_ARCH_HOST_A6)(a0) 189 REG_L a7, (KVM_ARCH_HOST_A7)(a0) 190 REG_L s2, (KVM_ARCH_HOST_S2)(a0) 191 REG_L s3, (KVM_ARCH_HOST_S3)(a0) 192 REG_L s4, (KVM_ARCH_HOST_S4)(a0) 193 REG_L s5, (KVM_ARCH_HOST_S5)(a0) 194 REG_L s6, (KVM_ARCH_HOST_S6)(a0) 195 REG_L s7, (KVM_ARCH_HOST_S7)(a0) 196 REG_L s8, (KVM_ARCH_HOST_S8)(a0) 197 REG_L s9, (KVM_ARCH_HOST_S9)(a0) 198 REG_L s10, (KVM_ARCH_HOST_S10)(a0) 199 REG_L s11, (KVM_ARCH_HOST_S11)(a0) 200 201 /* Return to C code */ 202 ret 203ENDPROC(__kvm_riscv_switch_to) 204 205ENTRY(__kvm_riscv_unpriv_trap) 206 /* 207 * We assume that faulting unpriv load/store instruction is 208 * 4-byte long and blindly increment SEPC by 4. 209 * 210 * The trap details will be saved at address pointed by 'A0' 211 * register and we use 'A1' register as temporary. 212 */ 213 csrr a1, CSR_SEPC 214 REG_S a1, (KVM_ARCH_TRAP_SEPC)(a0) 215 addi a1, a1, 4 216 csrw CSR_SEPC, a1 217 csrr a1, CSR_SCAUSE 218 REG_S a1, (KVM_ARCH_TRAP_SCAUSE)(a0) 219 csrr a1, CSR_STVAL 220 REG_S a1, (KVM_ARCH_TRAP_STVAL)(a0) 221 csrr a1, CSR_HTVAL 222 REG_S a1, (KVM_ARCH_TRAP_HTVAL)(a0) 223 csrr a1, CSR_HTINST 224 REG_S a1, (KVM_ARCH_TRAP_HTINST)(a0) 225 sret 226ENDPROC(__kvm_riscv_unpriv_trap) 227