1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/errno.h> 11 #include <linux/err.h> 12 #include <linux/kdebug.h> 13 #include <linux/module.h> 14 #include <linux/percpu.h> 15 #include <linux/uaccess.h> 16 #include <linux/vmalloc.h> 17 #include <linux/sched/signal.h> 18 #include <linux/fs.h> 19 #include <linux/kvm_host.h> 20 #include <asm/csr.h> 21 #include <asm/hwcap.h> 22 23 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 24 KVM_GENERIC_VCPU_STATS(), 25 STATS_DESC_COUNTER(VCPU, ecall_exit_stat), 26 STATS_DESC_COUNTER(VCPU, wfi_exit_stat), 27 STATS_DESC_COUNTER(VCPU, mmio_exit_user), 28 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel), 29 STATS_DESC_COUNTER(VCPU, csr_exit_user), 30 STATS_DESC_COUNTER(VCPU, csr_exit_kernel), 31 STATS_DESC_COUNTER(VCPU, exits) 32 }; 33 34 const struct kvm_stats_header kvm_vcpu_stats_header = { 35 .name_size = KVM_STATS_NAME_SIZE, 36 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 37 .id_offset = sizeof(struct kvm_stats_header), 38 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 39 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 40 sizeof(kvm_vcpu_stats_desc), 41 }; 42 43 #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) 44 45 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */ 46 static const unsigned long kvm_isa_ext_arr[] = { 47 RISCV_ISA_EXT_a, 48 RISCV_ISA_EXT_c, 49 RISCV_ISA_EXT_d, 50 RISCV_ISA_EXT_f, 51 RISCV_ISA_EXT_h, 52 RISCV_ISA_EXT_i, 53 RISCV_ISA_EXT_m, 54 RISCV_ISA_EXT_SVPBMT, 55 }; 56 57 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) 58 { 59 unsigned long i; 60 61 for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { 62 if (kvm_isa_ext_arr[i] == base_ext) 63 return i; 64 } 65 66 return KVM_RISCV_ISA_EXT_MAX; 67 } 68 69 static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) 70 { 71 switch (ext) { 72 case KVM_RISCV_ISA_EXT_H: 73 return false; 74 default: 75 break; 76 } 77 78 return true; 79 } 80 81 static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 82 { 83 switch (ext) { 84 case KVM_RISCV_ISA_EXT_A: 85 case KVM_RISCV_ISA_EXT_C: 86 case KVM_RISCV_ISA_EXT_I: 87 case KVM_RISCV_ISA_EXT_M: 88 return false; 89 default: 90 break; 91 } 92 93 return true; 94 } 95 96 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) 97 { 98 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 99 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 100 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 101 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; 102 bool loaded; 103 104 /** 105 * The preemption should be disabled here because it races with 106 * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which 107 * also calls vcpu_load/put. 108 */ 109 get_cpu(); 110 loaded = (vcpu->cpu != -1); 111 if (loaded) 112 kvm_arch_vcpu_put(vcpu); 113 114 vcpu->arch.last_exit_cpu = -1; 115 116 memcpy(csr, reset_csr, sizeof(*csr)); 117 118 memcpy(cntx, reset_cntx, sizeof(*cntx)); 119 120 kvm_riscv_vcpu_fp_reset(vcpu); 121 122 kvm_riscv_vcpu_timer_reset(vcpu); 123 124 WRITE_ONCE(vcpu->arch.irqs_pending, 0); 125 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); 126 127 vcpu->arch.hfence_head = 0; 128 vcpu->arch.hfence_tail = 0; 129 memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); 130 131 /* Reset the guest CSRs for hotplug usecase */ 132 if (loaded) 133 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 134 put_cpu(); 135 } 136 137 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 138 { 139 return 0; 140 } 141 142 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 143 { 144 struct kvm_cpu_context *cntx; 145 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 146 unsigned long host_isa, i; 147 148 /* Mark this VCPU never ran */ 149 vcpu->arch.ran_atleast_once = false; 150 vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO; 151 bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX); 152 153 /* Setup ISA features available to VCPU */ 154 for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) { 155 host_isa = kvm_isa_ext_arr[i]; 156 if (__riscv_isa_extension_available(NULL, host_isa) && 157 kvm_riscv_vcpu_isa_enable_allowed(i)) 158 set_bit(host_isa, vcpu->arch.isa); 159 } 160 161 /* Setup VCPU hfence queue */ 162 spin_lock_init(&vcpu->arch.hfence_lock); 163 164 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ 165 cntx = &vcpu->arch.guest_reset_context; 166 cntx->sstatus = SR_SPP | SR_SPIE; 167 cntx->hstatus = 0; 168 cntx->hstatus |= HSTATUS_VTW; 169 cntx->hstatus |= HSTATUS_SPVP; 170 cntx->hstatus |= HSTATUS_SPV; 171 172 /* By default, make CY, TM, and IR counters accessible in VU mode */ 173 reset_csr->scounteren = 0x7; 174 175 /* Setup VCPU timer */ 176 kvm_riscv_vcpu_timer_init(vcpu); 177 178 /* Reset VCPU */ 179 kvm_riscv_reset_vcpu(vcpu); 180 181 return 0; 182 } 183 184 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 185 { 186 /** 187 * vcpu with id 0 is the designated boot cpu. 188 * Keep all vcpus with non-zero id in power-off state so that 189 * they can be brought up using SBI HSM extension. 190 */ 191 if (vcpu->vcpu_idx != 0) 192 kvm_riscv_vcpu_power_off(vcpu); 193 } 194 195 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 196 { 197 /* Cleanup VCPU timer */ 198 kvm_riscv_vcpu_timer_deinit(vcpu); 199 200 /* Free unused pages pre-allocated for G-stage page table mappings */ 201 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); 202 } 203 204 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 205 { 206 return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER); 207 } 208 209 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 210 { 211 } 212 213 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 214 { 215 } 216 217 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 218 { 219 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) && 220 !vcpu->arch.power_off && !vcpu->arch.pause); 221 } 222 223 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 224 { 225 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 226 } 227 228 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 229 { 230 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; 231 } 232 233 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 234 { 235 return VM_FAULT_SIGBUS; 236 } 237 238 static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, 239 const struct kvm_one_reg *reg) 240 { 241 unsigned long __user *uaddr = 242 (unsigned long __user *)(unsigned long)reg->addr; 243 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 244 KVM_REG_SIZE_MASK | 245 KVM_REG_RISCV_CONFIG); 246 unsigned long reg_val; 247 248 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 249 return -EINVAL; 250 251 switch (reg_num) { 252 case KVM_REG_RISCV_CONFIG_REG(isa): 253 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; 254 break; 255 default: 256 return -EINVAL; 257 } 258 259 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 260 return -EFAULT; 261 262 return 0; 263 } 264 265 static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, 266 const struct kvm_one_reg *reg) 267 { 268 unsigned long __user *uaddr = 269 (unsigned long __user *)(unsigned long)reg->addr; 270 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 271 KVM_REG_SIZE_MASK | 272 KVM_REG_RISCV_CONFIG); 273 unsigned long i, isa_ext, reg_val; 274 275 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 276 return -EINVAL; 277 278 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 279 return -EFAULT; 280 281 /* This ONE REG interface is only defined for single letter extensions */ 282 if (fls(reg_val) >= RISCV_ISA_EXT_BASE) 283 return -EINVAL; 284 285 switch (reg_num) { 286 case KVM_REG_RISCV_CONFIG_REG(isa): 287 if (!vcpu->arch.ran_atleast_once) { 288 /* Ignore the enable/disable request for certain extensions */ 289 for (i = 0; i < RISCV_ISA_EXT_BASE; i++) { 290 isa_ext = kvm_riscv_vcpu_base2isa_ext(i); 291 if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) { 292 reg_val &= ~BIT(i); 293 continue; 294 } 295 if (!kvm_riscv_vcpu_isa_enable_allowed(isa_ext)) 296 if (reg_val & BIT(i)) 297 reg_val &= ~BIT(i); 298 if (!kvm_riscv_vcpu_isa_disable_allowed(isa_ext)) 299 if (!(reg_val & BIT(i))) 300 reg_val |= BIT(i); 301 } 302 reg_val &= riscv_isa_extension_base(NULL); 303 /* Do not modify anything beyond single letter extensions */ 304 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | 305 (reg_val & KVM_RISCV_BASE_ISA_MASK); 306 vcpu->arch.isa[0] = reg_val; 307 kvm_riscv_vcpu_fp_reset(vcpu); 308 } else { 309 return -EOPNOTSUPP; 310 } 311 break; 312 default: 313 return -EINVAL; 314 } 315 316 return 0; 317 } 318 319 static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu, 320 const struct kvm_one_reg *reg) 321 { 322 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 323 unsigned long __user *uaddr = 324 (unsigned long __user *)(unsigned long)reg->addr; 325 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 326 KVM_REG_SIZE_MASK | 327 KVM_REG_RISCV_CORE); 328 unsigned long reg_val; 329 330 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 331 return -EINVAL; 332 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) 333 return -EINVAL; 334 335 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) 336 reg_val = cntx->sepc; 337 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && 338 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) 339 reg_val = ((unsigned long *)cntx)[reg_num]; 340 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) 341 reg_val = (cntx->sstatus & SR_SPP) ? 342 KVM_RISCV_MODE_S : KVM_RISCV_MODE_U; 343 else 344 return -EINVAL; 345 346 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 347 return -EFAULT; 348 349 return 0; 350 } 351 352 static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu, 353 const struct kvm_one_reg *reg) 354 { 355 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 356 unsigned long __user *uaddr = 357 (unsigned long __user *)(unsigned long)reg->addr; 358 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 359 KVM_REG_SIZE_MASK | 360 KVM_REG_RISCV_CORE); 361 unsigned long reg_val; 362 363 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 364 return -EINVAL; 365 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) 366 return -EINVAL; 367 368 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 369 return -EFAULT; 370 371 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) 372 cntx->sepc = reg_val; 373 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && 374 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) 375 ((unsigned long *)cntx)[reg_num] = reg_val; 376 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) { 377 if (reg_val == KVM_RISCV_MODE_S) 378 cntx->sstatus |= SR_SPP; 379 else 380 cntx->sstatus &= ~SR_SPP; 381 } else 382 return -EINVAL; 383 384 return 0; 385 } 386 387 static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, 388 const struct kvm_one_reg *reg) 389 { 390 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 391 unsigned long __user *uaddr = 392 (unsigned long __user *)(unsigned long)reg->addr; 393 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 394 KVM_REG_SIZE_MASK | 395 KVM_REG_RISCV_CSR); 396 unsigned long reg_val; 397 398 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 399 return -EINVAL; 400 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) 401 return -EINVAL; 402 403 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { 404 kvm_riscv_vcpu_flush_interrupts(vcpu); 405 reg_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; 406 } else 407 reg_val = ((unsigned long *)csr)[reg_num]; 408 409 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 410 return -EFAULT; 411 412 return 0; 413 } 414 415 static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, 416 const struct kvm_one_reg *reg) 417 { 418 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 419 unsigned long __user *uaddr = 420 (unsigned long __user *)(unsigned long)reg->addr; 421 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 422 KVM_REG_SIZE_MASK | 423 KVM_REG_RISCV_CSR); 424 unsigned long reg_val; 425 426 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 427 return -EINVAL; 428 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) 429 return -EINVAL; 430 431 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 432 return -EFAULT; 433 434 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { 435 reg_val &= VSIP_VALID_MASK; 436 reg_val <<= VSIP_TO_HVIP_SHIFT; 437 } 438 439 ((unsigned long *)csr)[reg_num] = reg_val; 440 441 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) 442 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); 443 444 return 0; 445 } 446 447 static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu, 448 const struct kvm_one_reg *reg) 449 { 450 unsigned long __user *uaddr = 451 (unsigned long __user *)(unsigned long)reg->addr; 452 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 453 KVM_REG_SIZE_MASK | 454 KVM_REG_RISCV_ISA_EXT); 455 unsigned long reg_val = 0; 456 unsigned long host_isa_ext; 457 458 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 459 return -EINVAL; 460 461 if (reg_num >= KVM_RISCV_ISA_EXT_MAX || 462 reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) 463 return -EINVAL; 464 465 host_isa_ext = kvm_isa_ext_arr[reg_num]; 466 if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) 467 reg_val = 1; /* Mark the given extension as available */ 468 469 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 470 return -EFAULT; 471 472 return 0; 473 } 474 475 static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, 476 const struct kvm_one_reg *reg) 477 { 478 unsigned long __user *uaddr = 479 (unsigned long __user *)(unsigned long)reg->addr; 480 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 481 KVM_REG_SIZE_MASK | 482 KVM_REG_RISCV_ISA_EXT); 483 unsigned long reg_val; 484 unsigned long host_isa_ext; 485 486 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 487 return -EINVAL; 488 489 if (reg_num >= KVM_RISCV_ISA_EXT_MAX || 490 reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) 491 return -EINVAL; 492 493 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 494 return -EFAULT; 495 496 host_isa_ext = kvm_isa_ext_arr[reg_num]; 497 if (!__riscv_isa_extension_available(NULL, host_isa_ext)) 498 return -EOPNOTSUPP; 499 500 if (!vcpu->arch.ran_atleast_once) { 501 /* 502 * All multi-letter extension and a few single letter 503 * extension can be disabled 504 */ 505 if (reg_val == 1 && 506 kvm_riscv_vcpu_isa_enable_allowed(reg_num)) 507 set_bit(host_isa_ext, vcpu->arch.isa); 508 else if (!reg_val && 509 kvm_riscv_vcpu_isa_disable_allowed(reg_num)) 510 clear_bit(host_isa_ext, vcpu->arch.isa); 511 else 512 return -EINVAL; 513 kvm_riscv_vcpu_fp_reset(vcpu); 514 } else { 515 return -EOPNOTSUPP; 516 } 517 518 return 0; 519 } 520 521 static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, 522 const struct kvm_one_reg *reg) 523 { 524 if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG) 525 return kvm_riscv_vcpu_set_reg_config(vcpu, reg); 526 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE) 527 return kvm_riscv_vcpu_set_reg_core(vcpu, reg); 528 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) 529 return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); 530 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER) 531 return kvm_riscv_vcpu_set_reg_timer(vcpu, reg); 532 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) 533 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, 534 KVM_REG_RISCV_FP_F); 535 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) 536 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, 537 KVM_REG_RISCV_FP_D); 538 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT) 539 return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); 540 541 return -EINVAL; 542 } 543 544 static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, 545 const struct kvm_one_reg *reg) 546 { 547 if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG) 548 return kvm_riscv_vcpu_get_reg_config(vcpu, reg); 549 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE) 550 return kvm_riscv_vcpu_get_reg_core(vcpu, reg); 551 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR) 552 return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); 553 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER) 554 return kvm_riscv_vcpu_get_reg_timer(vcpu, reg); 555 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F) 556 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, 557 KVM_REG_RISCV_FP_F); 558 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D) 559 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, 560 KVM_REG_RISCV_FP_D); 561 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT) 562 return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); 563 564 return -EINVAL; 565 } 566 567 long kvm_arch_vcpu_async_ioctl(struct file *filp, 568 unsigned int ioctl, unsigned long arg) 569 { 570 struct kvm_vcpu *vcpu = filp->private_data; 571 void __user *argp = (void __user *)arg; 572 573 if (ioctl == KVM_INTERRUPT) { 574 struct kvm_interrupt irq; 575 576 if (copy_from_user(&irq, argp, sizeof(irq))) 577 return -EFAULT; 578 579 if (irq.irq == KVM_INTERRUPT_SET) 580 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT); 581 else 582 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT); 583 } 584 585 return -ENOIOCTLCMD; 586 } 587 588 long kvm_arch_vcpu_ioctl(struct file *filp, 589 unsigned int ioctl, unsigned long arg) 590 { 591 struct kvm_vcpu *vcpu = filp->private_data; 592 void __user *argp = (void __user *)arg; 593 long r = -EINVAL; 594 595 switch (ioctl) { 596 case KVM_SET_ONE_REG: 597 case KVM_GET_ONE_REG: { 598 struct kvm_one_reg reg; 599 600 r = -EFAULT; 601 if (copy_from_user(®, argp, sizeof(reg))) 602 break; 603 604 if (ioctl == KVM_SET_ONE_REG) 605 r = kvm_riscv_vcpu_set_reg(vcpu, ®); 606 else 607 r = kvm_riscv_vcpu_get_reg(vcpu, ®); 608 break; 609 } 610 default: 611 break; 612 } 613 614 return r; 615 } 616 617 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 618 struct kvm_sregs *sregs) 619 { 620 return -EINVAL; 621 } 622 623 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 624 struct kvm_sregs *sregs) 625 { 626 return -EINVAL; 627 } 628 629 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 630 { 631 return -EINVAL; 632 } 633 634 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 635 { 636 return -EINVAL; 637 } 638 639 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 640 struct kvm_translation *tr) 641 { 642 return -EINVAL; 643 } 644 645 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 646 { 647 return -EINVAL; 648 } 649 650 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 651 { 652 return -EINVAL; 653 } 654 655 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) 656 { 657 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 658 unsigned long mask, val; 659 660 if (READ_ONCE(vcpu->arch.irqs_pending_mask)) { 661 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask, 0); 662 val = READ_ONCE(vcpu->arch.irqs_pending) & mask; 663 664 csr->hvip &= ~mask; 665 csr->hvip |= val; 666 } 667 } 668 669 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) 670 { 671 unsigned long hvip; 672 struct kvm_vcpu_arch *v = &vcpu->arch; 673 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 674 675 /* Read current HVIP and VSIE CSRs */ 676 csr->vsie = csr_read(CSR_VSIE); 677 678 /* Sync-up HVIP.VSSIP bit changes does by Guest */ 679 hvip = csr_read(CSR_HVIP); 680 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { 681 if (hvip & (1UL << IRQ_VS_SOFT)) { 682 if (!test_and_set_bit(IRQ_VS_SOFT, 683 &v->irqs_pending_mask)) 684 set_bit(IRQ_VS_SOFT, &v->irqs_pending); 685 } else { 686 if (!test_and_set_bit(IRQ_VS_SOFT, 687 &v->irqs_pending_mask)) 688 clear_bit(IRQ_VS_SOFT, &v->irqs_pending); 689 } 690 } 691 } 692 693 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 694 { 695 if (irq != IRQ_VS_SOFT && 696 irq != IRQ_VS_TIMER && 697 irq != IRQ_VS_EXT) 698 return -EINVAL; 699 700 set_bit(irq, &vcpu->arch.irqs_pending); 701 smp_mb__before_atomic(); 702 set_bit(irq, &vcpu->arch.irqs_pending_mask); 703 704 kvm_vcpu_kick(vcpu); 705 706 return 0; 707 } 708 709 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 710 { 711 if (irq != IRQ_VS_SOFT && 712 irq != IRQ_VS_TIMER && 713 irq != IRQ_VS_EXT) 714 return -EINVAL; 715 716 clear_bit(irq, &vcpu->arch.irqs_pending); 717 smp_mb__before_atomic(); 718 set_bit(irq, &vcpu->arch.irqs_pending_mask); 719 720 return 0; 721 } 722 723 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask) 724 { 725 unsigned long ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK) 726 << VSIP_TO_HVIP_SHIFT) & mask; 727 728 return (READ_ONCE(vcpu->arch.irqs_pending) & ie) ? true : false; 729 } 730 731 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 732 { 733 vcpu->arch.power_off = true; 734 kvm_make_request(KVM_REQ_SLEEP, vcpu); 735 kvm_vcpu_kick(vcpu); 736 } 737 738 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 739 { 740 vcpu->arch.power_off = false; 741 kvm_vcpu_wake_up(vcpu); 742 } 743 744 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 745 struct kvm_mp_state *mp_state) 746 { 747 if (vcpu->arch.power_off) 748 mp_state->mp_state = KVM_MP_STATE_STOPPED; 749 else 750 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 751 752 return 0; 753 } 754 755 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 756 struct kvm_mp_state *mp_state) 757 { 758 int ret = 0; 759 760 switch (mp_state->mp_state) { 761 case KVM_MP_STATE_RUNNABLE: 762 vcpu->arch.power_off = false; 763 break; 764 case KVM_MP_STATE_STOPPED: 765 kvm_riscv_vcpu_power_off(vcpu); 766 break; 767 default: 768 ret = -EINVAL; 769 } 770 771 return ret; 772 } 773 774 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 775 struct kvm_guest_debug *dbg) 776 { 777 /* TODO; To be implemented later. */ 778 return -EINVAL; 779 } 780 781 static void kvm_riscv_vcpu_update_config(const unsigned long *isa) 782 { 783 u64 henvcfg = 0; 784 785 if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SVPBMT)) 786 henvcfg |= ENVCFG_PBMTE; 787 788 csr_write(CSR_HENVCFG, henvcfg); 789 #ifdef CONFIG_32BIT 790 csr_write(CSR_HENVCFGH, henvcfg >> 32); 791 #endif 792 } 793 794 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 795 { 796 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 797 798 csr_write(CSR_VSSTATUS, csr->vsstatus); 799 csr_write(CSR_VSIE, csr->vsie); 800 csr_write(CSR_VSTVEC, csr->vstvec); 801 csr_write(CSR_VSSCRATCH, csr->vsscratch); 802 csr_write(CSR_VSEPC, csr->vsepc); 803 csr_write(CSR_VSCAUSE, csr->vscause); 804 csr_write(CSR_VSTVAL, csr->vstval); 805 csr_write(CSR_HVIP, csr->hvip); 806 csr_write(CSR_VSATP, csr->vsatp); 807 808 kvm_riscv_vcpu_update_config(vcpu->arch.isa); 809 810 kvm_riscv_gstage_update_hgatp(vcpu); 811 812 kvm_riscv_vcpu_timer_restore(vcpu); 813 814 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); 815 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, 816 vcpu->arch.isa); 817 818 vcpu->cpu = cpu; 819 } 820 821 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 822 { 823 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 824 825 vcpu->cpu = -1; 826 827 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, 828 vcpu->arch.isa); 829 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); 830 831 csr->vsstatus = csr_read(CSR_VSSTATUS); 832 csr->vsie = csr_read(CSR_VSIE); 833 csr->vstvec = csr_read(CSR_VSTVEC); 834 csr->vsscratch = csr_read(CSR_VSSCRATCH); 835 csr->vsepc = csr_read(CSR_VSEPC); 836 csr->vscause = csr_read(CSR_VSCAUSE); 837 csr->vstval = csr_read(CSR_VSTVAL); 838 csr->hvip = csr_read(CSR_HVIP); 839 csr->vsatp = csr_read(CSR_VSATP); 840 } 841 842 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) 843 { 844 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu); 845 846 if (kvm_request_pending(vcpu)) { 847 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { 848 kvm_vcpu_srcu_read_unlock(vcpu); 849 rcuwait_wait_event(wait, 850 (!vcpu->arch.power_off) && (!vcpu->arch.pause), 851 TASK_INTERRUPTIBLE); 852 kvm_vcpu_srcu_read_lock(vcpu); 853 854 if (vcpu->arch.power_off || vcpu->arch.pause) { 855 /* 856 * Awaken to handle a signal, request to 857 * sleep again later. 858 */ 859 kvm_make_request(KVM_REQ_SLEEP, vcpu); 860 } 861 } 862 863 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) 864 kvm_riscv_reset_vcpu(vcpu); 865 866 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) 867 kvm_riscv_gstage_update_hgatp(vcpu); 868 869 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu)) 870 kvm_riscv_fence_i_process(vcpu); 871 872 /* 873 * The generic KVM_REQ_TLB_FLUSH is same as 874 * KVM_REQ_HFENCE_GVMA_VMID_ALL 875 */ 876 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu)) 877 kvm_riscv_hfence_gvma_vmid_all_process(vcpu); 878 879 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu)) 880 kvm_riscv_hfence_vvma_all_process(vcpu); 881 882 if (kvm_check_request(KVM_REQ_HFENCE, vcpu)) 883 kvm_riscv_hfence_process(vcpu); 884 } 885 } 886 887 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) 888 { 889 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 890 891 csr_write(CSR_HVIP, csr->hvip); 892 } 893 894 /* 895 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while 896 * the vCPU is running. 897 * 898 * This must be noinstr as instrumentation may make use of RCU, and this is not 899 * safe during the EQS. 900 */ 901 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) 902 { 903 guest_state_enter_irqoff(); 904 __kvm_riscv_switch_to(&vcpu->arch); 905 vcpu->arch.last_exit_cpu = vcpu->cpu; 906 guest_state_exit_irqoff(); 907 } 908 909 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 910 { 911 int ret; 912 struct kvm_cpu_trap trap; 913 struct kvm_run *run = vcpu->run; 914 915 /* Mark this VCPU ran at least once */ 916 vcpu->arch.ran_atleast_once = true; 917 918 kvm_vcpu_srcu_read_lock(vcpu); 919 920 switch (run->exit_reason) { 921 case KVM_EXIT_MMIO: 922 /* Process MMIO value returned from user-space */ 923 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); 924 break; 925 case KVM_EXIT_RISCV_SBI: 926 /* Process SBI value returned from user-space */ 927 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run); 928 break; 929 case KVM_EXIT_RISCV_CSR: 930 /* Process CSR value returned from user-space */ 931 ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run); 932 break; 933 default: 934 ret = 0; 935 break; 936 } 937 if (ret) { 938 kvm_vcpu_srcu_read_unlock(vcpu); 939 return ret; 940 } 941 942 if (run->immediate_exit) { 943 kvm_vcpu_srcu_read_unlock(vcpu); 944 return -EINTR; 945 } 946 947 vcpu_load(vcpu); 948 949 kvm_sigset_activate(vcpu); 950 951 ret = 1; 952 run->exit_reason = KVM_EXIT_UNKNOWN; 953 while (ret > 0) { 954 /* Check conditions before entering the guest */ 955 cond_resched(); 956 957 kvm_riscv_gstage_vmid_update(vcpu); 958 959 kvm_riscv_check_vcpu_requests(vcpu); 960 961 local_irq_disable(); 962 963 /* 964 * Exit if we have a signal pending so that we can deliver 965 * the signal to user space. 966 */ 967 if (signal_pending(current)) { 968 ret = -EINTR; 969 run->exit_reason = KVM_EXIT_INTR; 970 } 971 972 /* 973 * Ensure we set mode to IN_GUEST_MODE after we disable 974 * interrupts and before the final VCPU requests check. 975 * See the comment in kvm_vcpu_exiting_guest_mode() and 976 * Documentation/virt/kvm/vcpu-requests.rst 977 */ 978 vcpu->mode = IN_GUEST_MODE; 979 980 kvm_vcpu_srcu_read_unlock(vcpu); 981 smp_mb__after_srcu_read_unlock(); 982 983 /* 984 * We might have got VCPU interrupts updated asynchronously 985 * so update it in HW. 986 */ 987 kvm_riscv_vcpu_flush_interrupts(vcpu); 988 989 /* Update HVIP CSR for current CPU */ 990 kvm_riscv_update_hvip(vcpu); 991 992 if (ret <= 0 || 993 kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) || 994 kvm_request_pending(vcpu)) { 995 vcpu->mode = OUTSIDE_GUEST_MODE; 996 local_irq_enable(); 997 kvm_vcpu_srcu_read_lock(vcpu); 998 continue; 999 } 1000 1001 /* 1002 * Cleanup stale TLB enteries 1003 * 1004 * Note: This should be done after G-stage VMID has been 1005 * updated using kvm_riscv_gstage_vmid_ver_changed() 1006 */ 1007 kvm_riscv_local_tlb_sanitize(vcpu); 1008 1009 guest_timing_enter_irqoff(); 1010 1011 kvm_riscv_vcpu_enter_exit(vcpu); 1012 1013 vcpu->mode = OUTSIDE_GUEST_MODE; 1014 vcpu->stat.exits++; 1015 1016 /* 1017 * Save SCAUSE, STVAL, HTVAL, and HTINST because we might 1018 * get an interrupt between __kvm_riscv_switch_to() and 1019 * local_irq_enable() which can potentially change CSRs. 1020 */ 1021 trap.sepc = vcpu->arch.guest_context.sepc; 1022 trap.scause = csr_read(CSR_SCAUSE); 1023 trap.stval = csr_read(CSR_STVAL); 1024 trap.htval = csr_read(CSR_HTVAL); 1025 trap.htinst = csr_read(CSR_HTINST); 1026 1027 /* Syncup interrupts state with HW */ 1028 kvm_riscv_vcpu_sync_interrupts(vcpu); 1029 1030 preempt_disable(); 1031 1032 /* 1033 * We must ensure that any pending interrupts are taken before 1034 * we exit guest timing so that timer ticks are accounted as 1035 * guest time. Transiently unmask interrupts so that any 1036 * pending interrupts are taken. 1037 * 1038 * There's no barrier which ensures that pending interrupts are 1039 * recognised, so we just hope that the CPU takes any pending 1040 * interrupts between the enable and disable. 1041 */ 1042 local_irq_enable(); 1043 local_irq_disable(); 1044 1045 guest_timing_exit_irqoff(); 1046 1047 local_irq_enable(); 1048 1049 preempt_enable(); 1050 1051 kvm_vcpu_srcu_read_lock(vcpu); 1052 1053 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap); 1054 } 1055 1056 kvm_sigset_deactivate(vcpu); 1057 1058 vcpu_put(vcpu); 1059 1060 kvm_vcpu_srcu_read_unlock(vcpu); 1061 1062 return ret; 1063 } 1064