1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/entry-kvm.h> 11 #include <linux/errno.h> 12 #include <linux/err.h> 13 #include <linux/kdebug.h> 14 #include <linux/module.h> 15 #include <linux/percpu.h> 16 #include <linux/vmalloc.h> 17 #include <linux/sched/signal.h> 18 #include <linux/fs.h> 19 #include <linux/kvm_host.h> 20 #include <asm/csr.h> 21 #include <asm/cacheflush.h> 22 #include <asm/kvm_vcpu_vector.h> 23 24 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 25 KVM_GENERIC_VCPU_STATS(), 26 STATS_DESC_COUNTER(VCPU, ecall_exit_stat), 27 STATS_DESC_COUNTER(VCPU, wfi_exit_stat), 28 STATS_DESC_COUNTER(VCPU, mmio_exit_user), 29 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel), 30 STATS_DESC_COUNTER(VCPU, csr_exit_user), 31 STATS_DESC_COUNTER(VCPU, csr_exit_kernel), 32 STATS_DESC_COUNTER(VCPU, signal_exits), 33 STATS_DESC_COUNTER(VCPU, exits) 34 }; 35 36 const struct kvm_stats_header kvm_vcpu_stats_header = { 37 .name_size = KVM_STATS_NAME_SIZE, 38 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 39 .id_offset = sizeof(struct kvm_stats_header), 40 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 41 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 42 sizeof(kvm_vcpu_stats_desc), 43 }; 44 45 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) 46 { 47 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 48 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 49 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 50 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; 51 bool loaded; 52 53 /** 54 * The preemption should be disabled here because it races with 55 * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which 56 * also calls vcpu_load/put. 57 */ 58 get_cpu(); 59 loaded = (vcpu->cpu != -1); 60 if (loaded) 61 kvm_arch_vcpu_put(vcpu); 62 63 vcpu->arch.last_exit_cpu = -1; 64 65 memcpy(csr, reset_csr, sizeof(*csr)); 66 67 memcpy(cntx, reset_cntx, sizeof(*cntx)); 68 69 kvm_riscv_vcpu_fp_reset(vcpu); 70 71 kvm_riscv_vcpu_vector_reset(vcpu); 72 73 kvm_riscv_vcpu_timer_reset(vcpu); 74 75 kvm_riscv_vcpu_aia_reset(vcpu); 76 77 bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS); 78 bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS); 79 80 kvm_riscv_vcpu_pmu_reset(vcpu); 81 82 vcpu->arch.hfence_head = 0; 83 vcpu->arch.hfence_tail = 0; 84 memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); 85 86 /* Reset the guest CSRs for hotplug usecase */ 87 if (loaded) 88 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 89 put_cpu(); 90 } 91 92 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 93 { 94 return 0; 95 } 96 97 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 98 { 99 int rc; 100 struct kvm_cpu_context *cntx; 101 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 102 103 spin_lock_init(&vcpu->arch.mp_state_lock); 104 105 /* Mark this VCPU never ran */ 106 vcpu->arch.ran_atleast_once = false; 107 vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO; 108 bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX); 109 110 /* Setup ISA features available to VCPU */ 111 kvm_riscv_vcpu_setup_isa(vcpu); 112 113 /* Setup vendor, arch, and implementation details */ 114 vcpu->arch.mvendorid = sbi_get_mvendorid(); 115 vcpu->arch.marchid = sbi_get_marchid(); 116 vcpu->arch.mimpid = sbi_get_mimpid(); 117 118 /* Setup VCPU hfence queue */ 119 spin_lock_init(&vcpu->arch.hfence_lock); 120 121 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ 122 cntx = &vcpu->arch.guest_reset_context; 123 cntx->sstatus = SR_SPP | SR_SPIE; 124 cntx->hstatus = 0; 125 cntx->hstatus |= HSTATUS_VTW; 126 cntx->hstatus |= HSTATUS_SPVP; 127 cntx->hstatus |= HSTATUS_SPV; 128 129 if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx)) 130 return -ENOMEM; 131 132 /* By default, make CY, TM, and IR counters accessible in VU mode */ 133 reset_csr->scounteren = 0x7; 134 135 /* Setup VCPU timer */ 136 kvm_riscv_vcpu_timer_init(vcpu); 137 138 /* setup performance monitoring */ 139 kvm_riscv_vcpu_pmu_init(vcpu); 140 141 /* Setup VCPU AIA */ 142 rc = kvm_riscv_vcpu_aia_init(vcpu); 143 if (rc) 144 return rc; 145 146 /* Reset VCPU */ 147 kvm_riscv_reset_vcpu(vcpu); 148 149 return 0; 150 } 151 152 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 153 { 154 /** 155 * vcpu with id 0 is the designated boot cpu. 156 * Keep all vcpus with non-zero id in power-off state so that 157 * they can be brought up using SBI HSM extension. 158 */ 159 if (vcpu->vcpu_idx != 0) 160 kvm_riscv_vcpu_power_off(vcpu); 161 } 162 163 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 164 { 165 /* Cleanup VCPU AIA context */ 166 kvm_riscv_vcpu_aia_deinit(vcpu); 167 168 /* Cleanup VCPU timer */ 169 kvm_riscv_vcpu_timer_deinit(vcpu); 170 171 kvm_riscv_vcpu_pmu_deinit(vcpu); 172 173 /* Free unused pages pre-allocated for G-stage page table mappings */ 174 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); 175 176 /* Free vector context space for host and guest kernel */ 177 kvm_riscv_vcpu_free_vector_context(vcpu); 178 } 179 180 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 181 { 182 return kvm_riscv_vcpu_timer_pending(vcpu); 183 } 184 185 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 186 { 187 kvm_riscv_aia_wakeon_hgei(vcpu, true); 188 } 189 190 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 191 { 192 kvm_riscv_aia_wakeon_hgei(vcpu, false); 193 } 194 195 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 196 { 197 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) && 198 !kvm_riscv_vcpu_stopped(vcpu) && !vcpu->arch.pause); 199 } 200 201 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 202 { 203 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 204 } 205 206 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 207 { 208 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; 209 } 210 211 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 212 { 213 return VM_FAULT_SIGBUS; 214 } 215 216 long kvm_arch_vcpu_async_ioctl(struct file *filp, 217 unsigned int ioctl, unsigned long arg) 218 { 219 struct kvm_vcpu *vcpu = filp->private_data; 220 void __user *argp = (void __user *)arg; 221 222 if (ioctl == KVM_INTERRUPT) { 223 struct kvm_interrupt irq; 224 225 if (copy_from_user(&irq, argp, sizeof(irq))) 226 return -EFAULT; 227 228 if (irq.irq == KVM_INTERRUPT_SET) 229 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT); 230 else 231 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT); 232 } 233 234 return -ENOIOCTLCMD; 235 } 236 237 long kvm_arch_vcpu_ioctl(struct file *filp, 238 unsigned int ioctl, unsigned long arg) 239 { 240 struct kvm_vcpu *vcpu = filp->private_data; 241 void __user *argp = (void __user *)arg; 242 long r = -EINVAL; 243 244 switch (ioctl) { 245 case KVM_SET_ONE_REG: 246 case KVM_GET_ONE_REG: { 247 struct kvm_one_reg reg; 248 249 r = -EFAULT; 250 if (copy_from_user(®, argp, sizeof(reg))) 251 break; 252 253 if (ioctl == KVM_SET_ONE_REG) 254 r = kvm_riscv_vcpu_set_reg(vcpu, ®); 255 else 256 r = kvm_riscv_vcpu_get_reg(vcpu, ®); 257 break; 258 } 259 case KVM_GET_REG_LIST: { 260 struct kvm_reg_list __user *user_list = argp; 261 struct kvm_reg_list reg_list; 262 unsigned int n; 263 264 r = -EFAULT; 265 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 266 break; 267 n = reg_list.n; 268 reg_list.n = kvm_riscv_vcpu_num_regs(vcpu); 269 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 270 break; 271 r = -E2BIG; 272 if (n < reg_list.n) 273 break; 274 r = kvm_riscv_vcpu_copy_reg_indices(vcpu, user_list->reg); 275 break; 276 } 277 default: 278 break; 279 } 280 281 return r; 282 } 283 284 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 285 struct kvm_sregs *sregs) 286 { 287 return -EINVAL; 288 } 289 290 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 291 struct kvm_sregs *sregs) 292 { 293 return -EINVAL; 294 } 295 296 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 297 { 298 return -EINVAL; 299 } 300 301 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 302 { 303 return -EINVAL; 304 } 305 306 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 307 struct kvm_translation *tr) 308 { 309 return -EINVAL; 310 } 311 312 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 313 { 314 return -EINVAL; 315 } 316 317 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 318 { 319 return -EINVAL; 320 } 321 322 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) 323 { 324 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 325 unsigned long mask, val; 326 327 if (READ_ONCE(vcpu->arch.irqs_pending_mask[0])) { 328 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[0], 0); 329 val = READ_ONCE(vcpu->arch.irqs_pending[0]) & mask; 330 331 csr->hvip &= ~mask; 332 csr->hvip |= val; 333 } 334 335 /* Flush AIA high interrupts */ 336 kvm_riscv_vcpu_aia_flush_interrupts(vcpu); 337 } 338 339 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) 340 { 341 unsigned long hvip; 342 struct kvm_vcpu_arch *v = &vcpu->arch; 343 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 344 345 /* Read current HVIP and VSIE CSRs */ 346 csr->vsie = csr_read(CSR_VSIE); 347 348 /* Sync-up HVIP.VSSIP bit changes does by Guest */ 349 hvip = csr_read(CSR_HVIP); 350 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { 351 if (hvip & (1UL << IRQ_VS_SOFT)) { 352 if (!test_and_set_bit(IRQ_VS_SOFT, 353 v->irqs_pending_mask)) 354 set_bit(IRQ_VS_SOFT, v->irqs_pending); 355 } else { 356 if (!test_and_set_bit(IRQ_VS_SOFT, 357 v->irqs_pending_mask)) 358 clear_bit(IRQ_VS_SOFT, v->irqs_pending); 359 } 360 } 361 362 /* Sync-up AIA high interrupts */ 363 kvm_riscv_vcpu_aia_sync_interrupts(vcpu); 364 365 /* Sync-up timer CSRs */ 366 kvm_riscv_vcpu_timer_sync(vcpu); 367 } 368 369 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 370 { 371 /* 372 * We only allow VS-mode software, timer, and external 373 * interrupts when irq is one of the local interrupts 374 * defined by RISC-V privilege specification. 375 */ 376 if (irq < IRQ_LOCAL_MAX && 377 irq != IRQ_VS_SOFT && 378 irq != IRQ_VS_TIMER && 379 irq != IRQ_VS_EXT) 380 return -EINVAL; 381 382 set_bit(irq, vcpu->arch.irqs_pending); 383 smp_mb__before_atomic(); 384 set_bit(irq, vcpu->arch.irqs_pending_mask); 385 386 kvm_vcpu_kick(vcpu); 387 388 return 0; 389 } 390 391 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 392 { 393 /* 394 * We only allow VS-mode software, timer, and external 395 * interrupts when irq is one of the local interrupts 396 * defined by RISC-V privilege specification. 397 */ 398 if (irq < IRQ_LOCAL_MAX && 399 irq != IRQ_VS_SOFT && 400 irq != IRQ_VS_TIMER && 401 irq != IRQ_VS_EXT) 402 return -EINVAL; 403 404 clear_bit(irq, vcpu->arch.irqs_pending); 405 smp_mb__before_atomic(); 406 set_bit(irq, vcpu->arch.irqs_pending_mask); 407 408 return 0; 409 } 410 411 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask) 412 { 413 unsigned long ie; 414 415 ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK) 416 << VSIP_TO_HVIP_SHIFT) & (unsigned long)mask; 417 ie |= vcpu->arch.guest_csr.vsie & ~IRQ_LOCAL_MASK & 418 (unsigned long)mask; 419 if (READ_ONCE(vcpu->arch.irqs_pending[0]) & ie) 420 return true; 421 422 /* Check AIA high interrupts */ 423 return kvm_riscv_vcpu_aia_has_interrupts(vcpu, mask); 424 } 425 426 void __kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 427 { 428 WRITE_ONCE(vcpu->arch.mp_state.mp_state, KVM_MP_STATE_STOPPED); 429 kvm_make_request(KVM_REQ_SLEEP, vcpu); 430 kvm_vcpu_kick(vcpu); 431 } 432 433 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 434 { 435 spin_lock(&vcpu->arch.mp_state_lock); 436 __kvm_riscv_vcpu_power_off(vcpu); 437 spin_unlock(&vcpu->arch.mp_state_lock); 438 } 439 440 void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 441 { 442 WRITE_ONCE(vcpu->arch.mp_state.mp_state, KVM_MP_STATE_RUNNABLE); 443 kvm_vcpu_wake_up(vcpu); 444 } 445 446 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 447 { 448 spin_lock(&vcpu->arch.mp_state_lock); 449 __kvm_riscv_vcpu_power_on(vcpu); 450 spin_unlock(&vcpu->arch.mp_state_lock); 451 } 452 453 bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu) 454 { 455 return READ_ONCE(vcpu->arch.mp_state.mp_state) == KVM_MP_STATE_STOPPED; 456 } 457 458 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 459 struct kvm_mp_state *mp_state) 460 { 461 *mp_state = READ_ONCE(vcpu->arch.mp_state); 462 463 return 0; 464 } 465 466 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 467 struct kvm_mp_state *mp_state) 468 { 469 int ret = 0; 470 471 spin_lock(&vcpu->arch.mp_state_lock); 472 473 switch (mp_state->mp_state) { 474 case KVM_MP_STATE_RUNNABLE: 475 WRITE_ONCE(vcpu->arch.mp_state, *mp_state); 476 break; 477 case KVM_MP_STATE_STOPPED: 478 __kvm_riscv_vcpu_power_off(vcpu); 479 break; 480 default: 481 ret = -EINVAL; 482 } 483 484 spin_unlock(&vcpu->arch.mp_state_lock); 485 486 return ret; 487 } 488 489 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 490 struct kvm_guest_debug *dbg) 491 { 492 /* TODO; To be implemented later. */ 493 return -EINVAL; 494 } 495 496 static void kvm_riscv_vcpu_update_config(const unsigned long *isa) 497 { 498 u64 henvcfg = 0; 499 500 if (riscv_isa_extension_available(isa, SVPBMT)) 501 henvcfg |= ENVCFG_PBMTE; 502 503 if (riscv_isa_extension_available(isa, SSTC)) 504 henvcfg |= ENVCFG_STCE; 505 506 if (riscv_isa_extension_available(isa, ZICBOM)) 507 henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); 508 509 if (riscv_isa_extension_available(isa, ZICBOZ)) 510 henvcfg |= ENVCFG_CBZE; 511 512 csr_write(CSR_HENVCFG, henvcfg); 513 #ifdef CONFIG_32BIT 514 csr_write(CSR_HENVCFGH, henvcfg >> 32); 515 #endif 516 } 517 518 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 519 { 520 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 521 522 csr_write(CSR_VSSTATUS, csr->vsstatus); 523 csr_write(CSR_VSIE, csr->vsie); 524 csr_write(CSR_VSTVEC, csr->vstvec); 525 csr_write(CSR_VSSCRATCH, csr->vsscratch); 526 csr_write(CSR_VSEPC, csr->vsepc); 527 csr_write(CSR_VSCAUSE, csr->vscause); 528 csr_write(CSR_VSTVAL, csr->vstval); 529 csr_write(CSR_HVIP, csr->hvip); 530 csr_write(CSR_VSATP, csr->vsatp); 531 532 kvm_riscv_vcpu_update_config(vcpu->arch.isa); 533 534 kvm_riscv_gstage_update_hgatp(vcpu); 535 536 kvm_riscv_vcpu_timer_restore(vcpu); 537 538 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); 539 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, 540 vcpu->arch.isa); 541 kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context); 542 kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context, 543 vcpu->arch.isa); 544 545 kvm_riscv_vcpu_aia_load(vcpu, cpu); 546 547 vcpu->cpu = cpu; 548 } 549 550 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 551 { 552 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 553 554 vcpu->cpu = -1; 555 556 kvm_riscv_vcpu_aia_put(vcpu); 557 558 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, 559 vcpu->arch.isa); 560 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); 561 562 kvm_riscv_vcpu_timer_save(vcpu); 563 kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context, 564 vcpu->arch.isa); 565 kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context); 566 567 csr->vsstatus = csr_read(CSR_VSSTATUS); 568 csr->vsie = csr_read(CSR_VSIE); 569 csr->vstvec = csr_read(CSR_VSTVEC); 570 csr->vsscratch = csr_read(CSR_VSSCRATCH); 571 csr->vsepc = csr_read(CSR_VSEPC); 572 csr->vscause = csr_read(CSR_VSCAUSE); 573 csr->vstval = csr_read(CSR_VSTVAL); 574 csr->hvip = csr_read(CSR_HVIP); 575 csr->vsatp = csr_read(CSR_VSATP); 576 } 577 578 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) 579 { 580 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu); 581 582 if (kvm_request_pending(vcpu)) { 583 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { 584 kvm_vcpu_srcu_read_unlock(vcpu); 585 rcuwait_wait_event(wait, 586 (!kvm_riscv_vcpu_stopped(vcpu)) && (!vcpu->arch.pause), 587 TASK_INTERRUPTIBLE); 588 kvm_vcpu_srcu_read_lock(vcpu); 589 590 if (kvm_riscv_vcpu_stopped(vcpu) || vcpu->arch.pause) { 591 /* 592 * Awaken to handle a signal, request to 593 * sleep again later. 594 */ 595 kvm_make_request(KVM_REQ_SLEEP, vcpu); 596 } 597 } 598 599 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) 600 kvm_riscv_reset_vcpu(vcpu); 601 602 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) 603 kvm_riscv_gstage_update_hgatp(vcpu); 604 605 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu)) 606 kvm_riscv_fence_i_process(vcpu); 607 608 /* 609 * The generic KVM_REQ_TLB_FLUSH is same as 610 * KVM_REQ_HFENCE_GVMA_VMID_ALL 611 */ 612 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu)) 613 kvm_riscv_hfence_gvma_vmid_all_process(vcpu); 614 615 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu)) 616 kvm_riscv_hfence_vvma_all_process(vcpu); 617 618 if (kvm_check_request(KVM_REQ_HFENCE, vcpu)) 619 kvm_riscv_hfence_process(vcpu); 620 } 621 } 622 623 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) 624 { 625 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 626 627 csr_write(CSR_HVIP, csr->hvip); 628 kvm_riscv_vcpu_aia_update_hvip(vcpu); 629 } 630 631 /* 632 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while 633 * the vCPU is running. 634 * 635 * This must be noinstr as instrumentation may make use of RCU, and this is not 636 * safe during the EQS. 637 */ 638 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) 639 { 640 guest_state_enter_irqoff(); 641 __kvm_riscv_switch_to(&vcpu->arch); 642 vcpu->arch.last_exit_cpu = vcpu->cpu; 643 guest_state_exit_irqoff(); 644 } 645 646 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 647 { 648 int ret; 649 struct kvm_cpu_trap trap; 650 struct kvm_run *run = vcpu->run; 651 652 /* Mark this VCPU ran at least once */ 653 vcpu->arch.ran_atleast_once = true; 654 655 kvm_vcpu_srcu_read_lock(vcpu); 656 657 switch (run->exit_reason) { 658 case KVM_EXIT_MMIO: 659 /* Process MMIO value returned from user-space */ 660 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); 661 break; 662 case KVM_EXIT_RISCV_SBI: 663 /* Process SBI value returned from user-space */ 664 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run); 665 break; 666 case KVM_EXIT_RISCV_CSR: 667 /* Process CSR value returned from user-space */ 668 ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run); 669 break; 670 default: 671 ret = 0; 672 break; 673 } 674 if (ret) { 675 kvm_vcpu_srcu_read_unlock(vcpu); 676 return ret; 677 } 678 679 if (run->immediate_exit) { 680 kvm_vcpu_srcu_read_unlock(vcpu); 681 return -EINTR; 682 } 683 684 vcpu_load(vcpu); 685 686 kvm_sigset_activate(vcpu); 687 688 ret = 1; 689 run->exit_reason = KVM_EXIT_UNKNOWN; 690 while (ret > 0) { 691 /* Check conditions before entering the guest */ 692 ret = xfer_to_guest_mode_handle_work(vcpu); 693 if (ret) 694 continue; 695 ret = 1; 696 697 kvm_riscv_gstage_vmid_update(vcpu); 698 699 kvm_riscv_check_vcpu_requests(vcpu); 700 701 preempt_disable(); 702 703 /* Update AIA HW state before entering guest */ 704 ret = kvm_riscv_vcpu_aia_update(vcpu); 705 if (ret <= 0) { 706 preempt_enable(); 707 continue; 708 } 709 710 local_irq_disable(); 711 712 /* 713 * Ensure we set mode to IN_GUEST_MODE after we disable 714 * interrupts and before the final VCPU requests check. 715 * See the comment in kvm_vcpu_exiting_guest_mode() and 716 * Documentation/virt/kvm/vcpu-requests.rst 717 */ 718 vcpu->mode = IN_GUEST_MODE; 719 720 kvm_vcpu_srcu_read_unlock(vcpu); 721 smp_mb__after_srcu_read_unlock(); 722 723 /* 724 * We might have got VCPU interrupts updated asynchronously 725 * so update it in HW. 726 */ 727 kvm_riscv_vcpu_flush_interrupts(vcpu); 728 729 /* Update HVIP CSR for current CPU */ 730 kvm_riscv_update_hvip(vcpu); 731 732 if (ret <= 0 || 733 kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) || 734 kvm_request_pending(vcpu) || 735 xfer_to_guest_mode_work_pending()) { 736 vcpu->mode = OUTSIDE_GUEST_MODE; 737 local_irq_enable(); 738 preempt_enable(); 739 kvm_vcpu_srcu_read_lock(vcpu); 740 continue; 741 } 742 743 /* 744 * Cleanup stale TLB enteries 745 * 746 * Note: This should be done after G-stage VMID has been 747 * updated using kvm_riscv_gstage_vmid_ver_changed() 748 */ 749 kvm_riscv_local_tlb_sanitize(vcpu); 750 751 guest_timing_enter_irqoff(); 752 753 kvm_riscv_vcpu_enter_exit(vcpu); 754 755 vcpu->mode = OUTSIDE_GUEST_MODE; 756 vcpu->stat.exits++; 757 758 /* 759 * Save SCAUSE, STVAL, HTVAL, and HTINST because we might 760 * get an interrupt between __kvm_riscv_switch_to() and 761 * local_irq_enable() which can potentially change CSRs. 762 */ 763 trap.sepc = vcpu->arch.guest_context.sepc; 764 trap.scause = csr_read(CSR_SCAUSE); 765 trap.stval = csr_read(CSR_STVAL); 766 trap.htval = csr_read(CSR_HTVAL); 767 trap.htinst = csr_read(CSR_HTINST); 768 769 /* Syncup interrupts state with HW */ 770 kvm_riscv_vcpu_sync_interrupts(vcpu); 771 772 /* 773 * We must ensure that any pending interrupts are taken before 774 * we exit guest timing so that timer ticks are accounted as 775 * guest time. Transiently unmask interrupts so that any 776 * pending interrupts are taken. 777 * 778 * There's no barrier which ensures that pending interrupts are 779 * recognised, so we just hope that the CPU takes any pending 780 * interrupts between the enable and disable. 781 */ 782 local_irq_enable(); 783 local_irq_disable(); 784 785 guest_timing_exit_irqoff(); 786 787 local_irq_enable(); 788 789 preempt_enable(); 790 791 kvm_vcpu_srcu_read_lock(vcpu); 792 793 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap); 794 } 795 796 kvm_sigset_deactivate(vcpu); 797 798 vcpu_put(vcpu); 799 800 kvm_vcpu_srcu_read_unlock(vcpu); 801 802 return ret; 803 } 804