1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 * Copyright (C) 2014 Darius Rad <darius@bluespec.com> 5 * Copyright (C) 2017 SiFive 6 */ 7 8 #include <linux/syscalls.h> 9 #include <asm/unistd.h> 10 #include <asm/cacheflush.h> 11 #include <asm-generic/mman-common.h> 12 13 static long riscv_sys_mmap(unsigned long addr, unsigned long len, 14 unsigned long prot, unsigned long flags, 15 unsigned long fd, off_t offset, 16 unsigned long page_shift_offset) 17 { 18 if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) 19 return -EINVAL; 20 21 if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) 22 return -EINVAL; 23 24 return ksys_mmap_pgoff(addr, len, prot, flags, fd, 25 offset >> (PAGE_SHIFT - page_shift_offset)); 26 } 27 28 #ifdef CONFIG_64BIT 29 SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, 30 unsigned long, prot, unsigned long, flags, 31 unsigned long, fd, off_t, offset) 32 { 33 return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0); 34 } 35 #endif 36 37 #if defined(CONFIG_32BIT) || defined(CONFIG_COMPAT) 38 SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 39 unsigned long, prot, unsigned long, flags, 40 unsigned long, fd, off_t, offset) 41 { 42 /* 43 * Note that the shift for mmap2 is constant (12), 44 * regardless of PAGE_SIZE 45 */ 46 return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12); 47 } 48 #endif 49 50 /* 51 * Allows the instruction cache to be flushed from userspace. Despite RISC-V 52 * having a direct 'fence.i' instruction available to userspace (which we 53 * can't trap!), that's not actually viable when running on Linux because the 54 * kernel might schedule a process on another hart. There is no way for 55 * userspace to handle this without invoking the kernel (as it doesn't know the 56 * thread->hart mappings), so we've defined a RISC-V specific system call to 57 * flush the instruction cache. 58 * 59 * sys_riscv_flush_icache() is defined to flush the instruction cache over an 60 * address range, with the flush applying to either all threads or just the 61 * caller. We don't currently do anything with the address range, that's just 62 * in there for forwards compatibility. 63 */ 64 SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, 65 uintptr_t, flags) 66 { 67 /* Check the reserved flags. */ 68 if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) 69 return -EINVAL; 70 71 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); 72 73 return 0; 74 } 75