1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 * Copyright (C) 2014 Darius Rad <darius@bluespec.com> 5 * Copyright (C) 2017 SiFive 6 */ 7 8 #include <linux/syscalls.h> 9 #include <asm/unistd.h> 10 #include <asm/cacheflush.h> 11 #include <asm-generic/mman-common.h> 12 13 static long riscv_sys_mmap(unsigned long addr, unsigned long len, 14 unsigned long prot, unsigned long flags, 15 unsigned long fd, off_t offset, 16 unsigned long page_shift_offset) 17 { 18 if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) 19 return -EINVAL; 20 21 if ((prot & PROT_WRITE) && (prot & PROT_EXEC)) 22 if (unlikely(!(prot & PROT_READ))) 23 return -EINVAL; 24 25 return ksys_mmap_pgoff(addr, len, prot, flags, fd, 26 offset >> (PAGE_SHIFT - page_shift_offset)); 27 } 28 29 #ifdef CONFIG_64BIT 30 SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, 31 unsigned long, prot, unsigned long, flags, 32 unsigned long, fd, off_t, offset) 33 { 34 return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0); 35 } 36 #endif 37 38 #if defined(CONFIG_32BIT) || defined(CONFIG_COMPAT) 39 SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 40 unsigned long, prot, unsigned long, flags, 41 unsigned long, fd, off_t, offset) 42 { 43 /* 44 * Note that the shift for mmap2 is constant (12), 45 * regardless of PAGE_SIZE 46 */ 47 return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12); 48 } 49 #endif 50 51 /* 52 * Allows the instruction cache to be flushed from userspace. Despite RISC-V 53 * having a direct 'fence.i' instruction available to userspace (which we 54 * can't trap!), that's not actually viable when running on Linux because the 55 * kernel might schedule a process on another hart. There is no way for 56 * userspace to handle this without invoking the kernel (as it doesn't know the 57 * thread->hart mappings), so we've defined a RISC-V specific system call to 58 * flush the instruction cache. 59 * 60 * sys_riscv_flush_icache() is defined to flush the instruction cache over an 61 * address range, with the flush applying to either all threads or just the 62 * caller. We don't currently do anything with the address range, that's just 63 * in there for forwards compatibility. 64 */ 65 SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, 66 uintptr_t, flags) 67 { 68 /* Check the reserved flags. */ 69 if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) 70 return -EINVAL; 71 72 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); 73 74 return 0; 75 } 76