1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Tilera Corporation. All Rights Reserved. 4 * Copyright 2015 Regents of the University of California 5 * Copyright 2017 SiFive 6 * 7 * Copied from arch/tile/kernel/ptrace.c 8 */ 9 10 #include <asm/vector.h> 11 #include <asm/ptrace.h> 12 #include <asm/syscall.h> 13 #include <asm/thread_info.h> 14 #include <asm/switch_to.h> 15 #include <linux/audit.h> 16 #include <linux/compat.h> 17 #include <linux/ptrace.h> 18 #include <linux/elf.h> 19 #include <linux/regset.h> 20 #include <linux/sched.h> 21 #include <linux/sched/task_stack.h> 22 23 enum riscv_regset { 24 REGSET_X, 25 #ifdef CONFIG_FPU 26 REGSET_F, 27 #endif 28 #ifdef CONFIG_RISCV_ISA_V 29 REGSET_V, 30 #endif 31 }; 32 33 static int riscv_gpr_get(struct task_struct *target, 34 const struct user_regset *regset, 35 struct membuf to) 36 { 37 return membuf_write(&to, task_pt_regs(target), 38 sizeof(struct user_regs_struct)); 39 } 40 41 static int riscv_gpr_set(struct task_struct *target, 42 const struct user_regset *regset, 43 unsigned int pos, unsigned int count, 44 const void *kbuf, const void __user *ubuf) 45 { 46 struct pt_regs *regs; 47 48 regs = task_pt_regs(target); 49 return user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs, 0, -1); 50 } 51 52 #ifdef CONFIG_FPU 53 static int riscv_fpr_get(struct task_struct *target, 54 const struct user_regset *regset, 55 struct membuf to) 56 { 57 struct __riscv_d_ext_state *fstate = &target->thread.fstate; 58 59 if (target == current) 60 fstate_save(current, task_pt_regs(current)); 61 62 membuf_write(&to, fstate, offsetof(struct __riscv_d_ext_state, fcsr)); 63 membuf_store(&to, fstate->fcsr); 64 return membuf_zero(&to, 4); // explicitly pad 65 } 66 67 static int riscv_fpr_set(struct task_struct *target, 68 const struct user_regset *regset, 69 unsigned int pos, unsigned int count, 70 const void *kbuf, const void __user *ubuf) 71 { 72 int ret; 73 struct __riscv_d_ext_state *fstate = &target->thread.fstate; 74 75 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, fstate, 0, 76 offsetof(struct __riscv_d_ext_state, fcsr)); 77 if (!ret) { 78 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, fstate, 0, 79 offsetof(struct __riscv_d_ext_state, fcsr) + 80 sizeof(fstate->fcsr)); 81 } 82 83 return ret; 84 } 85 #endif 86 87 #ifdef CONFIG_RISCV_ISA_V 88 static int riscv_vr_get(struct task_struct *target, 89 const struct user_regset *regset, 90 struct membuf to) 91 { 92 struct __riscv_v_ext_state *vstate = &target->thread.vstate; 93 94 if (!riscv_v_vstate_query(task_pt_regs(target))) 95 return -EINVAL; 96 97 /* 98 * Ensure the vector registers have been saved to the memory before 99 * copying them to membuf. 100 */ 101 if (target == current) 102 riscv_v_vstate_save(current, task_pt_regs(current)); 103 104 /* Copy vector header from vstate. */ 105 membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap)); 106 membuf_zero(&to, sizeof(vstate->datap)); 107 108 /* Copy all the vector registers from vstate. */ 109 return membuf_write(&to, vstate->datap, riscv_v_vsize); 110 } 111 112 static int riscv_vr_set(struct task_struct *target, 113 const struct user_regset *regset, 114 unsigned int pos, unsigned int count, 115 const void *kbuf, const void __user *ubuf) 116 { 117 int ret, size; 118 struct __riscv_v_ext_state *vstate = &target->thread.vstate; 119 120 if (!riscv_v_vstate_query(task_pt_regs(target))) 121 return -EINVAL; 122 123 /* Copy rest of the vstate except datap */ 124 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0, 125 offsetof(struct __riscv_v_ext_state, datap)); 126 if (unlikely(ret)) 127 return ret; 128 129 /* Skip copy datap. */ 130 size = sizeof(vstate->datap); 131 count -= size; 132 ubuf += size; 133 134 /* Copy all the vector registers. */ 135 pos = 0; 136 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap, 137 0, riscv_v_vsize); 138 return ret; 139 } 140 #endif 141 142 static const struct user_regset riscv_user_regset[] = { 143 [REGSET_X] = { 144 .core_note_type = NT_PRSTATUS, 145 .n = ELF_NGREG, 146 .size = sizeof(elf_greg_t), 147 .align = sizeof(elf_greg_t), 148 .regset_get = riscv_gpr_get, 149 .set = riscv_gpr_set, 150 }, 151 #ifdef CONFIG_FPU 152 [REGSET_F] = { 153 .core_note_type = NT_PRFPREG, 154 .n = ELF_NFPREG, 155 .size = sizeof(elf_fpreg_t), 156 .align = sizeof(elf_fpreg_t), 157 .regset_get = riscv_fpr_get, 158 .set = riscv_fpr_set, 159 }, 160 #endif 161 #ifdef CONFIG_RISCV_ISA_V 162 [REGSET_V] = { 163 .core_note_type = NT_RISCV_VECTOR, 164 .align = 16, 165 .n = ((32 * RISCV_MAX_VLENB) + 166 sizeof(struct __riscv_v_ext_state)) / sizeof(__u32), 167 .size = sizeof(__u32), 168 .regset_get = riscv_vr_get, 169 .set = riscv_vr_set, 170 }, 171 #endif 172 }; 173 174 static const struct user_regset_view riscv_user_native_view = { 175 .name = "riscv", 176 .e_machine = EM_RISCV, 177 .regsets = riscv_user_regset, 178 .n = ARRAY_SIZE(riscv_user_regset), 179 }; 180 181 struct pt_regs_offset { 182 const char *name; 183 int offset; 184 }; 185 186 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 187 #define REG_OFFSET_END {.name = NULL, .offset = 0} 188 189 static const struct pt_regs_offset regoffset_table[] = { 190 REG_OFFSET_NAME(epc), 191 REG_OFFSET_NAME(ra), 192 REG_OFFSET_NAME(sp), 193 REG_OFFSET_NAME(gp), 194 REG_OFFSET_NAME(tp), 195 REG_OFFSET_NAME(t0), 196 REG_OFFSET_NAME(t1), 197 REG_OFFSET_NAME(t2), 198 REG_OFFSET_NAME(s0), 199 REG_OFFSET_NAME(s1), 200 REG_OFFSET_NAME(a0), 201 REG_OFFSET_NAME(a1), 202 REG_OFFSET_NAME(a2), 203 REG_OFFSET_NAME(a3), 204 REG_OFFSET_NAME(a4), 205 REG_OFFSET_NAME(a5), 206 REG_OFFSET_NAME(a6), 207 REG_OFFSET_NAME(a7), 208 REG_OFFSET_NAME(s2), 209 REG_OFFSET_NAME(s3), 210 REG_OFFSET_NAME(s4), 211 REG_OFFSET_NAME(s5), 212 REG_OFFSET_NAME(s6), 213 REG_OFFSET_NAME(s7), 214 REG_OFFSET_NAME(s8), 215 REG_OFFSET_NAME(s9), 216 REG_OFFSET_NAME(s10), 217 REG_OFFSET_NAME(s11), 218 REG_OFFSET_NAME(t3), 219 REG_OFFSET_NAME(t4), 220 REG_OFFSET_NAME(t5), 221 REG_OFFSET_NAME(t6), 222 REG_OFFSET_NAME(status), 223 REG_OFFSET_NAME(badaddr), 224 REG_OFFSET_NAME(cause), 225 REG_OFFSET_NAME(orig_a0), 226 REG_OFFSET_END, 227 }; 228 229 /** 230 * regs_query_register_offset() - query register offset from its name 231 * @name: the name of a register 232 * 233 * regs_query_register_offset() returns the offset of a register in struct 234 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 235 */ 236 int regs_query_register_offset(const char *name) 237 { 238 const struct pt_regs_offset *roff; 239 240 for (roff = regoffset_table; roff->name != NULL; roff++) 241 if (!strcmp(roff->name, name)) 242 return roff->offset; 243 return -EINVAL; 244 } 245 246 /** 247 * regs_within_kernel_stack() - check the address in the stack 248 * @regs: pt_regs which contains kernel stack pointer. 249 * @addr: address which is checked. 250 * 251 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 252 * If @addr is within the kernel stack, it returns true. If not, returns false. 253 */ 254 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 255 { 256 return (addr & ~(THREAD_SIZE - 1)) == 257 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)); 258 } 259 260 /** 261 * regs_get_kernel_stack_nth() - get Nth entry of the stack 262 * @regs: pt_regs which contains kernel stack pointer. 263 * @n: stack entry number. 264 * 265 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 266 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 267 * this returns 0. 268 */ 269 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 270 { 271 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 272 273 addr += n; 274 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 275 return *addr; 276 else 277 return 0; 278 } 279 280 void ptrace_disable(struct task_struct *child) 281 { 282 } 283 284 long arch_ptrace(struct task_struct *child, long request, 285 unsigned long addr, unsigned long data) 286 { 287 long ret = -EIO; 288 289 switch (request) { 290 default: 291 ret = ptrace_request(child, request, addr, data); 292 break; 293 } 294 295 return ret; 296 } 297 298 #ifdef CONFIG_COMPAT 299 static int compat_riscv_gpr_get(struct task_struct *target, 300 const struct user_regset *regset, 301 struct membuf to) 302 { 303 struct compat_user_regs_struct cregs; 304 305 regs_to_cregs(&cregs, task_pt_regs(target)); 306 307 return membuf_write(&to, &cregs, 308 sizeof(struct compat_user_regs_struct)); 309 } 310 311 static int compat_riscv_gpr_set(struct task_struct *target, 312 const struct user_regset *regset, 313 unsigned int pos, unsigned int count, 314 const void *kbuf, const void __user *ubuf) 315 { 316 int ret; 317 struct compat_user_regs_struct cregs; 318 319 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &cregs, 0, -1); 320 321 cregs_to_regs(&cregs, task_pt_regs(target)); 322 323 return ret; 324 } 325 326 static const struct user_regset compat_riscv_user_regset[] = { 327 [REGSET_X] = { 328 .core_note_type = NT_PRSTATUS, 329 .n = ELF_NGREG, 330 .size = sizeof(compat_elf_greg_t), 331 .align = sizeof(compat_elf_greg_t), 332 .regset_get = compat_riscv_gpr_get, 333 .set = compat_riscv_gpr_set, 334 }, 335 #ifdef CONFIG_FPU 336 [REGSET_F] = { 337 .core_note_type = NT_PRFPREG, 338 .n = ELF_NFPREG, 339 .size = sizeof(elf_fpreg_t), 340 .align = sizeof(elf_fpreg_t), 341 .regset_get = riscv_fpr_get, 342 .set = riscv_fpr_set, 343 }, 344 #endif 345 }; 346 347 static const struct user_regset_view compat_riscv_user_native_view = { 348 .name = "riscv", 349 .e_machine = EM_RISCV, 350 .regsets = compat_riscv_user_regset, 351 .n = ARRAY_SIZE(compat_riscv_user_regset), 352 }; 353 354 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 355 compat_ulong_t caddr, compat_ulong_t cdata) 356 { 357 long ret = -EIO; 358 359 switch (request) { 360 default: 361 ret = compat_ptrace_request(child, request, caddr, cdata); 362 break; 363 } 364 365 return ret; 366 } 367 #endif /* CONFIG_COMPAT */ 368 369 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 370 { 371 #ifdef CONFIG_COMPAT 372 if (test_tsk_thread_flag(task, TIF_32BIT)) 373 return &compat_riscv_user_native_view; 374 else 375 #endif 376 return &riscv_user_native_view; 377 } 378