1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copied from arch/arm64/kernel/cpufeature.c 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitmap.h> 11 #include <linux/ctype.h> 12 #include <linux/log2.h> 13 #include <linux/memory.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <asm/acpi.h> 17 #include <asm/alternative.h> 18 #include <asm/cacheflush.h> 19 #include <asm/cpufeature.h> 20 #include <asm/hwcap.h> 21 #include <asm/patch.h> 22 #include <asm/processor.h> 23 #include <asm/vector.h> 24 25 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) 26 27 unsigned long elf_hwcap __read_mostly; 28 29 /* Host ISA bitmap */ 30 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; 31 32 /* Per-cpu ISA extensions. */ 33 struct riscv_isainfo hart_isa[NR_CPUS]; 34 35 /* Performance information */ 36 DEFINE_PER_CPU(long, misaligned_access_speed); 37 38 /** 39 * riscv_isa_extension_base() - Get base extension word 40 * 41 * @isa_bitmap: ISA bitmap to use 42 * Return: base extension word as unsigned long value 43 * 44 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. 45 */ 46 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) 47 { 48 if (!isa_bitmap) 49 return riscv_isa[0]; 50 return isa_bitmap[0]; 51 } 52 EXPORT_SYMBOL_GPL(riscv_isa_extension_base); 53 54 /** 55 * __riscv_isa_extension_available() - Check whether given extension 56 * is available or not 57 * 58 * @isa_bitmap: ISA bitmap to use 59 * @bit: bit position of the desired extension 60 * Return: true or false 61 * 62 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. 63 */ 64 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit) 65 { 66 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa; 67 68 if (bit >= RISCV_ISA_EXT_MAX) 69 return false; 70 71 return test_bit(bit, bmap) ? true : false; 72 } 73 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); 74 75 static bool riscv_isa_extension_check(int id) 76 { 77 switch (id) { 78 case RISCV_ISA_EXT_ZICBOM: 79 if (!riscv_cbom_block_size) { 80 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); 81 return false; 82 } else if (!is_power_of_2(riscv_cbom_block_size)) { 83 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); 84 return false; 85 } 86 return true; 87 case RISCV_ISA_EXT_ZICBOZ: 88 if (!riscv_cboz_block_size) { 89 pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); 90 return false; 91 } else if (!is_power_of_2(riscv_cboz_block_size)) { 92 pr_err("cboz-block-size present, but is not a power-of-2\n"); 93 return false; 94 } 95 return true; 96 } 97 98 return true; 99 } 100 101 void __init riscv_fill_hwcap(void) 102 { 103 struct device_node *node; 104 const char *isa; 105 char print_str[NUM_ALPHA_EXTS + 1]; 106 int i, j, rc; 107 unsigned long isa2hwcap[26] = {0}; 108 struct acpi_table_header *rhct; 109 acpi_status status; 110 unsigned int cpu; 111 112 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; 113 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; 114 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; 115 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; 116 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; 117 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; 118 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; 119 120 elf_hwcap = 0; 121 122 bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); 123 124 if (!acpi_disabled) { 125 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); 126 if (ACPI_FAILURE(status)) 127 return; 128 } 129 130 for_each_possible_cpu(cpu) { 131 struct riscv_isainfo *isainfo = &hart_isa[cpu]; 132 unsigned long this_hwcap = 0; 133 134 if (acpi_disabled) { 135 node = of_cpu_device_node_get(cpu); 136 if (!node) { 137 pr_warn("Unable to find cpu node\n"); 138 continue; 139 } 140 141 rc = of_property_read_string(node, "riscv,isa", &isa); 142 of_node_put(node); 143 if (rc) { 144 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); 145 continue; 146 } 147 } else { 148 rc = acpi_get_riscv_isa(rhct, cpu, &isa); 149 if (rc < 0) { 150 pr_warn("Unable to get ISA for the hart - %d\n", cpu); 151 continue; 152 } 153 } 154 155 /* 156 * For all possible cpus, we have already validated in 157 * the boot process that they at least contain "rv" and 158 * whichever of "32"/"64" this kernel supports, and so this 159 * section can be skipped. 160 */ 161 isa += 4; 162 163 while (*isa) { 164 const char *ext = isa++; 165 const char *ext_end = isa; 166 bool ext_long = false, ext_err = false; 167 168 switch (*ext) { 169 case 's': 170 /* 171 * Workaround for invalid single-letter 's' & 'u'(QEMU). 172 * No need to set the bit in riscv_isa as 's' & 'u' are 173 * not valid ISA extensions. It works until multi-letter 174 * extension starting with "Su" appears. 175 */ 176 if (ext[-1] != '_' && ext[1] == 'u') { 177 ++isa; 178 ext_err = true; 179 break; 180 } 181 fallthrough; 182 case 'S': 183 case 'x': 184 case 'X': 185 case 'z': 186 case 'Z': 187 /* 188 * Before attempting to parse the extension itself, we find its end. 189 * As multi-letter extensions must be split from other multi-letter 190 * extensions with an "_", the end of a multi-letter extension will 191 * either be the null character or the "_" at the start of the next 192 * multi-letter extension. 193 * 194 * Next, as the extensions version is currently ignored, we 195 * eliminate that portion. This is done by parsing backwards from 196 * the end of the extension, removing any numbers. This may be a 197 * major or minor number however, so the process is repeated if a 198 * minor number was found. 199 * 200 * ext_end is intended to represent the first character *after* the 201 * name portion of an extension, but will be decremented to the last 202 * character itself while eliminating the extensions version number. 203 * A simple re-increment solves this problem. 204 */ 205 ext_long = true; 206 for (; *isa && *isa != '_'; ++isa) 207 if (unlikely(!isalnum(*isa))) 208 ext_err = true; 209 210 ext_end = isa; 211 if (unlikely(ext_err)) 212 break; 213 214 if (!isdigit(ext_end[-1])) 215 break; 216 217 while (isdigit(*--ext_end)) 218 ; 219 220 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { 221 ++ext_end; 222 break; 223 } 224 225 while (isdigit(*--ext_end)) 226 ; 227 228 ++ext_end; 229 break; 230 default: 231 /* 232 * Things are a little easier for single-letter extensions, as they 233 * are parsed forwards. 234 * 235 * After checking that our starting position is valid, we need to 236 * ensure that, when isa was incremented at the start of the loop, 237 * that it arrived at the start of the next extension. 238 * 239 * If we are already on a non-digit, there is nothing to do. Either 240 * we have a multi-letter extension's _, or the start of an 241 * extension. 242 * 243 * Otherwise we have found the current extension's major version 244 * number. Parse past it, and a subsequent p/minor version number 245 * if present. The `p` extension must not appear immediately after 246 * a number, so there is no fear of missing it. 247 * 248 */ 249 if (unlikely(!isalpha(*ext))) { 250 ext_err = true; 251 break; 252 } 253 254 if (!isdigit(*isa)) 255 break; 256 257 while (isdigit(*++isa)) 258 ; 259 260 if (tolower(*isa) != 'p') 261 break; 262 263 if (!isdigit(*++isa)) { 264 --isa; 265 break; 266 } 267 268 while (isdigit(*++isa)) 269 ; 270 271 break; 272 } 273 274 /* 275 * The parser expects that at the start of an iteration isa points to the 276 * first character of the next extension. As we stop parsing an extension 277 * on meeting a non-alphanumeric character, an extra increment is needed 278 * where the succeeding extension is a multi-letter prefixed with an "_". 279 */ 280 if (*isa == '_') 281 ++isa; 282 283 #define SET_ISA_EXT_MAP(name, bit) \ 284 do { \ 285 if ((ext_end - ext == sizeof(name) - 1) && \ 286 !strncasecmp(ext, name, sizeof(name) - 1) && \ 287 riscv_isa_extension_check(bit)) \ 288 set_bit(bit, isainfo->isa); \ 289 } while (false) \ 290 291 if (unlikely(ext_err)) 292 continue; 293 if (!ext_long) { 294 int nr = tolower(*ext) - 'a'; 295 296 if (riscv_isa_extension_check(nr)) { 297 this_hwcap |= isa2hwcap[nr]; 298 set_bit(nr, isainfo->isa); 299 } 300 } else { 301 /* sorted alphabetically */ 302 SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); 303 SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); 304 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); 305 SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); 306 SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); 307 SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); 308 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); 309 SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); 310 SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); 311 SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); 312 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); 313 SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); 314 SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); 315 } 316 #undef SET_ISA_EXT_MAP 317 } 318 319 /* 320 * These ones were as they were part of the base ISA when the 321 * port & dt-bindings were upstreamed, and so can be set 322 * unconditionally where `i` is in riscv,isa on DT systems. 323 */ 324 if (acpi_disabled) { 325 set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa); 326 set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa); 327 set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa); 328 set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa); 329 } 330 331 /* 332 * All "okay" hart should have same isa. Set HWCAP based on 333 * common capabilities of every "okay" hart, in case they don't 334 * have. 335 */ 336 if (elf_hwcap) 337 elf_hwcap &= this_hwcap; 338 else 339 elf_hwcap = this_hwcap; 340 341 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 342 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 343 else 344 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 345 } 346 347 if (!acpi_disabled && rhct) 348 acpi_put_table((struct acpi_table_header *)rhct); 349 350 /* We don't support systems with F but without D, so mask those out 351 * here. */ 352 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { 353 pr_info("This kernel does not support systems with F but not D\n"); 354 elf_hwcap &= ~COMPAT_HWCAP_ISA_F; 355 } 356 357 if (elf_hwcap & COMPAT_HWCAP_ISA_V) { 358 riscv_v_setup_vsize(); 359 /* 360 * ISA string in device tree might have 'v' flag, but 361 * CONFIG_RISCV_ISA_V is disabled in kernel. 362 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. 363 */ 364 if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) 365 elf_hwcap &= ~COMPAT_HWCAP_ISA_V; 366 } 367 368 memset(print_str, 0, sizeof(print_str)); 369 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) 370 if (riscv_isa[0] & BIT_MASK(i)) 371 print_str[j++] = (char)('a' + i); 372 pr_info("riscv: base ISA extensions %s\n", print_str); 373 374 memset(print_str, 0, sizeof(print_str)); 375 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) 376 if (elf_hwcap & BIT_MASK(i)) 377 print_str[j++] = (char)('a' + i); 378 pr_info("riscv: ELF capabilities %s\n", print_str); 379 } 380 381 unsigned long riscv_get_elf_hwcap(void) 382 { 383 unsigned long hwcap; 384 385 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); 386 387 if (!riscv_v_vstate_ctrl_user_allowed()) 388 hwcap &= ~COMPAT_HWCAP_ISA_V; 389 390 return hwcap; 391 } 392 393 #ifdef CONFIG_RISCV_ALTERNATIVE 394 /* 395 * Alternative patch sites consider 48 bits when determining when to patch 396 * the old instruction sequence with the new. These bits are broken into a 397 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the 398 * patch site is for an erratum, identified by the 32-bit patch ID. When 399 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures 400 * further break down patch ID into two 16-bit numbers. The lower 16 bits 401 * are the cpufeature ID and the upper 16 bits are used for a value specific 402 * to the cpufeature and patch site. If the upper 16 bits are zero, then it 403 * implies no specific value is specified. cpufeatures that want to control 404 * patching on a per-site basis will provide non-zero values and implement 405 * checks here. The checks return true when patching should be done, and 406 * false otherwise. 407 */ 408 static bool riscv_cpufeature_patch_check(u16 id, u16 value) 409 { 410 if (!value) 411 return true; 412 413 switch (id) { 414 case RISCV_ISA_EXT_ZICBOZ: 415 /* 416 * Zicboz alternative applications provide the maximum 417 * supported block size order, or zero when it doesn't 418 * matter. If the current block size exceeds the maximum, 419 * then the alternative cannot be applied. 420 */ 421 return riscv_cboz_block_size <= (1U << value); 422 } 423 424 return false; 425 } 426 427 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, 428 struct alt_entry *end, 429 unsigned int stage) 430 { 431 struct alt_entry *alt; 432 void *oldptr, *altptr; 433 u16 id, value; 434 435 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) 436 return; 437 438 for (alt = begin; alt < end; alt++) { 439 if (alt->vendor_id != 0) 440 continue; 441 442 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); 443 444 if (id >= RISCV_ISA_EXT_MAX) { 445 WARN(1, "This extension id:%d is not in ISA extension list", id); 446 continue; 447 } 448 449 if (!__riscv_isa_extension_available(NULL, id)) 450 continue; 451 452 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); 453 if (!riscv_cpufeature_patch_check(id, value)) 454 continue; 455 456 oldptr = ALT_OLD_PTR(alt); 457 altptr = ALT_ALT_PTR(alt); 458 459 mutex_lock(&text_mutex); 460 patch_text_nosync(oldptr, altptr, alt->alt_len); 461 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); 462 mutex_unlock(&text_mutex); 463 } 464 } 465 #endif 466