1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #include <linux/init.h> 7 #include <linux/seq_file.h> 8 #include <linux/of.h> 9 #include <asm/hwcap.h> 10 #include <asm/smp.h> 11 #include <asm/pgtable.h> 12 13 /* 14 * Returns the hart ID of the given device tree node, or -ENODEV if the node 15 * isn't an enabled and valid RISC-V hart node. 16 */ 17 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) 18 { 19 const char *isa; 20 21 if (!of_device_is_compatible(node, "riscv")) { 22 pr_warn("Found incompatible CPU\n"); 23 return -ENODEV; 24 } 25 26 *hart = (unsigned long) of_get_cpu_hwid(node, 0); 27 if (*hart == ~0UL) { 28 pr_warn("Found CPU without hart ID\n"); 29 return -ENODEV; 30 } 31 32 if (!of_device_is_available(node)) { 33 pr_info("CPU with hartid=%lu is not available\n", *hart); 34 return -ENODEV; 35 } 36 37 if (of_property_read_string(node, "riscv,isa", &isa)) { 38 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); 39 return -ENODEV; 40 } 41 if (isa[0] != 'r' || isa[1] != 'v') { 42 pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); 43 return -ENODEV; 44 } 45 46 return 0; 47 } 48 49 /* 50 * Find hart ID of the CPU DT node under which given DT node falls. 51 * 52 * To achieve this, we walk up the DT tree until we find an active 53 * RISC-V core (HART) node and extract the cpuid from it. 54 */ 55 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) 56 { 57 int rc; 58 59 for (; node; node = node->parent) { 60 if (of_device_is_compatible(node, "riscv")) { 61 rc = riscv_of_processor_hartid(node, hartid); 62 if (!rc) 63 return 0; 64 } 65 } 66 67 return -1; 68 } 69 70 #ifdef CONFIG_PROC_FS 71 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ 72 { \ 73 .uprop = #UPROP, \ 74 .isa_ext_id = EXTID, \ 75 } 76 /* 77 * Here are the ordering rules of extension naming defined by RISC-V 78 * specification : 79 * 1. All extensions should be separated from other multi-letter extensions 80 * by an underscore. 81 * 2. The first letter following the 'Z' conventionally indicates the most 82 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 83 * If multiple 'Z' extensions are named, they should be ordered first 84 * by category, then alphabetically within a category. 85 * 3. Standard supervisor-level extensions (starts with 'S') should be 86 * listed after standard unprivileged extensions. If multiple 87 * supervisor-level extensions are listed, they should be ordered 88 * alphabetically. 89 * 4. Non-standard extensions (starts with 'X') must be listed after all 90 * standard extensions. They must be separated from other multi-letter 91 * extensions by an underscore. 92 */ 93 static struct riscv_isa_ext_data isa_ext_arr[] = { 94 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 95 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 96 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), 97 }; 98 99 static void print_isa_ext(struct seq_file *f) 100 { 101 struct riscv_isa_ext_data *edata; 102 int i = 0, arr_sz; 103 104 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; 105 106 /* No extension support available */ 107 if (arr_sz <= 0) 108 return; 109 110 for (i = 0; i <= arr_sz; i++) { 111 edata = &isa_ext_arr[i]; 112 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) 113 continue; 114 seq_printf(f, "_%s", edata->uprop); 115 } 116 } 117 118 /* 119 * These are the only valid base (single letter) ISA extensions as per the spec. 120 * It also specifies the canonical order in which it appears in the spec. 121 * Some of the extension may just be a place holder for now (B, K, P, J). 122 * This should be updated once corresponding extensions are ratified. 123 */ 124 static const char base_riscv_exts[13] = "imafdqcbkjpvh"; 125 126 static void print_isa(struct seq_file *f, const char *isa) 127 { 128 int i; 129 130 seq_puts(f, "isa\t\t: "); 131 /* Print the rv[64/32] part */ 132 seq_write(f, isa, 4); 133 for (i = 0; i < sizeof(base_riscv_exts); i++) { 134 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) 135 /* Print only enabled the base ISA extensions */ 136 seq_write(f, &base_riscv_exts[i], 1); 137 } 138 print_isa_ext(f); 139 seq_puts(f, "\n"); 140 } 141 142 static void print_mmu(struct seq_file *f) 143 { 144 char sv_type[16]; 145 146 #ifdef CONFIG_MMU 147 #if defined(CONFIG_32BIT) 148 strncpy(sv_type, "sv32", 5); 149 #elif defined(CONFIG_64BIT) 150 if (pgtable_l5_enabled) 151 strncpy(sv_type, "sv57", 5); 152 else if (pgtable_l4_enabled) 153 strncpy(sv_type, "sv48", 5); 154 else 155 strncpy(sv_type, "sv39", 5); 156 #endif 157 #else 158 strncpy(sv_type, "none", 5); 159 #endif /* CONFIG_MMU */ 160 seq_printf(f, "mmu\t\t: %s\n", sv_type); 161 } 162 163 static void *c_start(struct seq_file *m, loff_t *pos) 164 { 165 *pos = cpumask_next(*pos - 1, cpu_online_mask); 166 if ((*pos) < nr_cpu_ids) 167 return (void *)(uintptr_t)(1 + *pos); 168 return NULL; 169 } 170 171 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 172 { 173 (*pos)++; 174 return c_start(m, pos); 175 } 176 177 static void c_stop(struct seq_file *m, void *v) 178 { 179 } 180 181 static int c_show(struct seq_file *m, void *v) 182 { 183 unsigned long cpu_id = (unsigned long)v - 1; 184 struct device_node *node = of_get_cpu_node(cpu_id, NULL); 185 const char *compat, *isa; 186 187 seq_printf(m, "processor\t: %lu\n", cpu_id); 188 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); 189 if (!of_property_read_string(node, "riscv,isa", &isa)) 190 print_isa(m, isa); 191 print_mmu(m); 192 if (!of_property_read_string(node, "compatible", &compat) 193 && strcmp(compat, "riscv")) 194 seq_printf(m, "uarch\t\t: %s\n", compat); 195 seq_puts(m, "\n"); 196 of_node_put(node); 197 198 return 0; 199 } 200 201 const struct seq_operations cpuinfo_op = { 202 .start = c_start, 203 .next = c_next, 204 .stop = c_stop, 205 .show = c_show 206 }; 207 208 #endif /* CONFIG_PROC_FS */ 209