1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/cpu.h> 8 #include <linux/ctype.h> 9 #include <linux/init.h> 10 #include <linux/seq_file.h> 11 #include <linux/of.h> 12 #include <asm/acpi.h> 13 #include <asm/cpufeature.h> 14 #include <asm/csr.h> 15 #include <asm/hwcap.h> 16 #include <asm/sbi.h> 17 #include <asm/smp.h> 18 #include <asm/pgtable.h> 19 20 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 21 { 22 return phys_id == cpuid_to_hartid_map(cpu); 23 } 24 25 /* 26 * Returns the hart ID of the given device tree node, or -ENODEV if the node 27 * isn't an enabled and valid RISC-V hart node. 28 */ 29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) 30 { 31 int cpu; 32 33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); 34 if (*hart == ~0UL) { 35 pr_warn("Found CPU without hart ID\n"); 36 return -ENODEV; 37 } 38 39 cpu = riscv_hartid_to_cpuid(*hart); 40 if (cpu < 0) 41 return cpu; 42 43 if (!cpu_possible(cpu)) 44 return -ENODEV; 45 46 return 0; 47 } 48 49 int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) 50 { 51 const char *isa; 52 53 if (!of_device_is_compatible(node, "riscv")) { 54 pr_warn("Found incompatible CPU\n"); 55 return -ENODEV; 56 } 57 58 *hart = (unsigned long)of_get_cpu_hwid(node, 0); 59 if (*hart == ~0UL) { 60 pr_warn("Found CPU without hart ID\n"); 61 return -ENODEV; 62 } 63 64 if (!of_device_is_available(node)) { 65 pr_info("CPU with hartid=%lu is not available\n", *hart); 66 return -ENODEV; 67 } 68 69 if (of_property_read_string(node, "riscv,isa", &isa)) { 70 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); 71 return -ENODEV; 72 } 73 74 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) 75 return -ENODEV; 76 77 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) 78 return -ENODEV; 79 80 return 0; 81 } 82 83 /* 84 * Find hart ID of the CPU DT node under which given DT node falls. 85 * 86 * To achieve this, we walk up the DT tree until we find an active 87 * RISC-V core (HART) node and extract the cpuid from it. 88 */ 89 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) 90 { 91 int rc; 92 93 for (; node; node = node->parent) { 94 if (of_device_is_compatible(node, "riscv")) { 95 rc = riscv_of_processor_hartid(node, hartid); 96 if (!rc) 97 return 0; 98 } 99 } 100 101 return -1; 102 } 103 104 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); 105 106 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) 107 { 108 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 109 110 return ci->mvendorid; 111 } 112 EXPORT_SYMBOL(riscv_cached_mvendorid); 113 114 unsigned long riscv_cached_marchid(unsigned int cpu_id) 115 { 116 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 117 118 return ci->marchid; 119 } 120 EXPORT_SYMBOL(riscv_cached_marchid); 121 122 unsigned long riscv_cached_mimpid(unsigned int cpu_id) 123 { 124 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 125 126 return ci->mimpid; 127 } 128 EXPORT_SYMBOL(riscv_cached_mimpid); 129 130 static int riscv_cpuinfo_starting(unsigned int cpu) 131 { 132 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); 133 134 #if IS_ENABLED(CONFIG_RISCV_SBI) 135 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); 136 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); 137 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); 138 #elif IS_ENABLED(CONFIG_RISCV_M_MODE) 139 ci->mvendorid = csr_read(CSR_MVENDORID); 140 ci->marchid = csr_read(CSR_MARCHID); 141 ci->mimpid = csr_read(CSR_MIMPID); 142 #else 143 ci->mvendorid = 0; 144 ci->marchid = 0; 145 ci->mimpid = 0; 146 #endif 147 148 return 0; 149 } 150 151 static int __init riscv_cpuinfo_init(void) 152 { 153 int ret; 154 155 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", 156 riscv_cpuinfo_starting, NULL); 157 if (ret < 0) { 158 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 159 return ret; 160 } 161 162 return 0; 163 } 164 arch_initcall(riscv_cpuinfo_init); 165 166 #ifdef CONFIG_PROC_FS 167 168 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ 169 { \ 170 .uprop = #UPROP, \ 171 .isa_ext_id = EXTID, \ 172 } 173 174 /* 175 * The canonical order of ISA extension names in the ISA string is defined in 176 * chapter 27 of the unprivileged specification. 177 * 178 * Ordinarily, for in-kernel data structures, this order is unimportant but 179 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. 180 * 181 * The specification uses vague wording, such as should, when it comes to 182 * ordering, so for our purposes the following rules apply: 183 * 184 * 1. All multi-letter extensions must be separated from other extensions by an 185 * underscore. 186 * 187 * 2. Additional standard extensions (starting with 'Z') must be sorted after 188 * single-letter extensions and before any higher-privileged extensions. 189 190 * 3. The first letter following the 'Z' conventionally indicates the most 191 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 192 * If multiple 'Z' extensions are named, they must be ordered first by 193 * category, then alphabetically within a category. 194 * 195 * 3. Standard supervisor-level extensions (starting with 'S') must be listed 196 * after standard unprivileged extensions. If multiple supervisor-level 197 * extensions are listed, they must be ordered alphabetically. 198 * 199 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed 200 * after any lower-privileged, standard extensions. If multiple 201 * machine-level extensions are listed, they must be ordered 202 * alphabetically. 203 * 204 * 5. Non-standard extensions (starting with 'X') must be listed after all 205 * standard extensions. If multiple non-standard extensions are listed, they 206 * must be ordered alphabetically. 207 * 208 * An example string following the order is: 209 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux 210 * 211 * New entries to this struct should follow the ordering rules described above. 212 */ 213 static struct riscv_isa_ext_data isa_ext_arr[] = { 214 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), 215 __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), 216 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), 217 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), 218 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), 219 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), 220 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), 221 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), 222 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), 223 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), 224 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), 225 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), 226 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 227 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), 228 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 229 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), 230 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 231 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), 232 }; 233 234 static void print_isa_ext(struct seq_file *f) 235 { 236 struct riscv_isa_ext_data *edata; 237 int i = 0, arr_sz; 238 239 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; 240 241 /* No extension support available */ 242 if (arr_sz <= 0) 243 return; 244 245 for (i = 0; i <= arr_sz; i++) { 246 edata = &isa_ext_arr[i]; 247 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) 248 continue; 249 seq_printf(f, "_%s", edata->uprop); 250 } 251 } 252 253 /* 254 * These are the only valid base (single letter) ISA extensions as per the spec. 255 * It also specifies the canonical order in which it appears in the spec. 256 * Some of the extension may just be a place holder for now (B, K, P, J). 257 * This should be updated once corresponding extensions are ratified. 258 */ 259 static const char base_riscv_exts[13] = "imafdqcbkjpvh"; 260 261 static void print_isa(struct seq_file *f, const char *isa) 262 { 263 int i; 264 265 seq_puts(f, "isa\t\t: "); 266 /* Print the rv[64/32] part */ 267 seq_write(f, isa, 4); 268 for (i = 0; i < sizeof(base_riscv_exts); i++) { 269 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) 270 /* Print only enabled the base ISA extensions */ 271 seq_write(f, &base_riscv_exts[i], 1); 272 } 273 print_isa_ext(f); 274 seq_puts(f, "\n"); 275 } 276 277 static void print_mmu(struct seq_file *f) 278 { 279 char sv_type[16]; 280 281 #ifdef CONFIG_MMU 282 #if defined(CONFIG_32BIT) 283 strncpy(sv_type, "sv32", 5); 284 #elif defined(CONFIG_64BIT) 285 if (pgtable_l5_enabled) 286 strncpy(sv_type, "sv57", 5); 287 else if (pgtable_l4_enabled) 288 strncpy(sv_type, "sv48", 5); 289 else 290 strncpy(sv_type, "sv39", 5); 291 #endif 292 #else 293 strncpy(sv_type, "none", 5); 294 #endif /* CONFIG_MMU */ 295 seq_printf(f, "mmu\t\t: %s\n", sv_type); 296 } 297 298 static void *c_start(struct seq_file *m, loff_t *pos) 299 { 300 if (*pos == nr_cpu_ids) 301 return NULL; 302 303 *pos = cpumask_next(*pos - 1, cpu_online_mask); 304 if ((*pos) < nr_cpu_ids) 305 return (void *)(uintptr_t)(1 + *pos); 306 return NULL; 307 } 308 309 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 310 { 311 (*pos)++; 312 return c_start(m, pos); 313 } 314 315 static void c_stop(struct seq_file *m, void *v) 316 { 317 } 318 319 static int c_show(struct seq_file *m, void *v) 320 { 321 unsigned long cpu_id = (unsigned long)v - 1; 322 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 323 struct device_node *node; 324 const char *compat, *isa; 325 326 seq_printf(m, "processor\t: %lu\n", cpu_id); 327 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); 328 329 if (acpi_disabled) { 330 node = of_get_cpu_node(cpu_id, NULL); 331 if (!of_property_read_string(node, "riscv,isa", &isa)) 332 print_isa(m, isa); 333 334 print_mmu(m); 335 if (!of_property_read_string(node, "compatible", &compat) && 336 strcmp(compat, "riscv")) 337 seq_printf(m, "uarch\t\t: %s\n", compat); 338 339 of_node_put(node); 340 } else { 341 if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) 342 print_isa(m, isa); 343 344 print_mmu(m); 345 } 346 347 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); 348 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); 349 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); 350 seq_puts(m, "\n"); 351 352 return 0; 353 } 354 355 const struct seq_operations cpuinfo_op = { 356 .start = c_start, 357 .next = c_next, 358 .stop = c_stop, 359 .show = c_show 360 }; 361 362 #endif /* CONFIG_PROC_FS */ 363