xref: /openbmc/linux/arch/riscv/kernel/cpu.c (revision 7effbd18) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2012 Regents of the University of California
4  */
5 
6 #include <linux/cpu.h>
7 #include <linux/init.h>
8 #include <linux/seq_file.h>
9 #include <linux/of.h>
10 #include <asm/csr.h>
11 #include <asm/hwcap.h>
12 #include <asm/sbi.h>
13 #include <asm/smp.h>
14 #include <asm/pgtable.h>
15 
16 /*
17  * Returns the hart ID of the given device tree node, or -ENODEV if the node
18  * isn't an enabled and valid RISC-V hart node.
19  */
20 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
21 {
22 	const char *isa;
23 
24 	if (!of_device_is_compatible(node, "riscv")) {
25 		pr_warn("Found incompatible CPU\n");
26 		return -ENODEV;
27 	}
28 
29 	*hart = (unsigned long) of_get_cpu_hwid(node, 0);
30 	if (*hart == ~0UL) {
31 		pr_warn("Found CPU without hart ID\n");
32 		return -ENODEV;
33 	}
34 
35 	if (!of_device_is_available(node)) {
36 		pr_info("CPU with hartid=%lu is not available\n", *hart);
37 		return -ENODEV;
38 	}
39 
40 	if (of_property_read_string(node, "riscv,isa", &isa)) {
41 		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
42 		return -ENODEV;
43 	}
44 	if (isa[0] != 'r' || isa[1] != 'v') {
45 		pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
46 		return -ENODEV;
47 	}
48 
49 	return 0;
50 }
51 
52 /*
53  * Find hart ID of the CPU DT node under which given DT node falls.
54  *
55  * To achieve this, we walk up the DT tree until we find an active
56  * RISC-V core (HART) node and extract the cpuid from it.
57  */
58 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
59 {
60 	int rc;
61 
62 	for (; node; node = node->parent) {
63 		if (of_device_is_compatible(node, "riscv")) {
64 			rc = riscv_of_processor_hartid(node, hartid);
65 			if (!rc)
66 				return 0;
67 		}
68 	}
69 
70 	return -1;
71 }
72 
73 struct riscv_cpuinfo {
74 	unsigned long mvendorid;
75 	unsigned long marchid;
76 	unsigned long mimpid;
77 };
78 static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
79 
80 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
81 {
82 	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
83 
84 	return ci->mvendorid;
85 }
86 EXPORT_SYMBOL(riscv_cached_mvendorid);
87 
88 unsigned long riscv_cached_marchid(unsigned int cpu_id)
89 {
90 	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
91 
92 	return ci->marchid;
93 }
94 EXPORT_SYMBOL(riscv_cached_marchid);
95 
96 unsigned long riscv_cached_mimpid(unsigned int cpu_id)
97 {
98 	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
99 
100 	return ci->mimpid;
101 }
102 EXPORT_SYMBOL(riscv_cached_mimpid);
103 
104 static int riscv_cpuinfo_starting(unsigned int cpu)
105 {
106 	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
107 
108 #if IS_ENABLED(CONFIG_RISCV_SBI)
109 	ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
110 	ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
111 	ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
112 #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
113 	ci->mvendorid = csr_read(CSR_MVENDORID);
114 	ci->marchid = csr_read(CSR_MARCHID);
115 	ci->mimpid = csr_read(CSR_MIMPID);
116 #else
117 	ci->mvendorid = 0;
118 	ci->marchid = 0;
119 	ci->mimpid = 0;
120 #endif
121 
122 	return 0;
123 }
124 
125 static int __init riscv_cpuinfo_init(void)
126 {
127 	int ret;
128 
129 	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
130 				riscv_cpuinfo_starting, NULL);
131 	if (ret < 0) {
132 		pr_err("cpuinfo: failed to register hotplug callbacks.\n");
133 		return ret;
134 	}
135 
136 	return 0;
137 }
138 arch_initcall(riscv_cpuinfo_init);
139 
140 #ifdef CONFIG_PROC_FS
141 
142 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
143 	{							\
144 		.uprop = #UPROP,				\
145 		.isa_ext_id = EXTID,				\
146 	}
147 
148 /*
149  * The canonical order of ISA extension names in the ISA string is defined in
150  * chapter 27 of the unprivileged specification.
151  *
152  * Ordinarily, for in-kernel data structures, this order is unimportant but
153  * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
154  *
155  * The specification uses vague wording, such as should, when it comes to
156  * ordering, so for our purposes the following rules apply:
157  *
158  * 1. All multi-letter extensions must be separated from other extensions by an
159  *    underscore.
160  *
161  * 2. Additional standard extensions (starting with 'Z') must be sorted after
162  *    single-letter extensions and before any higher-privileged extensions.
163 
164  * 3. The first letter following the 'Z' conventionally indicates the most
165  *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
166  *    If multiple 'Z' extensions are named, they must be ordered first by
167  *    category, then alphabetically within a category.
168  *
169  * 3. Standard supervisor-level extensions (starting with 'S') must be listed
170  *    after standard unprivileged extensions.  If multiple supervisor-level
171  *    extensions are listed, they must be ordered alphabetically.
172  *
173  * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
174  *    after any lower-privileged, standard extensions.  If multiple
175  *    machine-level extensions are listed, they must be ordered
176  *    alphabetically.
177  *
178  * 5. Non-standard extensions (starting with 'X') must be listed after all
179  *    standard extensions. If multiple non-standard extensions are listed, they
180  *    must be ordered alphabetically.
181  *
182  * An example string following the order is:
183  *    rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
184  *
185  * New entries to this struct should follow the ordering rules described above.
186  */
187 static struct riscv_isa_ext_data isa_ext_arr[] = {
188 	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
189 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
190 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
191 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
192 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
193 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
194 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
195 	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
196 };
197 
198 static void print_isa_ext(struct seq_file *f)
199 {
200 	struct riscv_isa_ext_data *edata;
201 	int i = 0, arr_sz;
202 
203 	arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
204 
205 	/* No extension support available */
206 	if (arr_sz <= 0)
207 		return;
208 
209 	for (i = 0; i <= arr_sz; i++) {
210 		edata = &isa_ext_arr[i];
211 		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
212 			continue;
213 		seq_printf(f, "_%s", edata->uprop);
214 	}
215 }
216 
217 /*
218  * These are the only valid base (single letter) ISA extensions as per the spec.
219  * It also specifies the canonical order in which it appears in the spec.
220  * Some of the extension may just be a place holder for now (B, K, P, J).
221  * This should be updated once corresponding extensions are ratified.
222  */
223 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
224 
225 static void print_isa(struct seq_file *f, const char *isa)
226 {
227 	int i;
228 
229 	seq_puts(f, "isa\t\t: ");
230 	/* Print the rv[64/32] part */
231 	seq_write(f, isa, 4);
232 	for (i = 0; i < sizeof(base_riscv_exts); i++) {
233 		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
234 			/* Print only enabled the base ISA extensions */
235 			seq_write(f, &base_riscv_exts[i], 1);
236 	}
237 	print_isa_ext(f);
238 	seq_puts(f, "\n");
239 }
240 
241 static void print_mmu(struct seq_file *f)
242 {
243 	char sv_type[16];
244 
245 #ifdef CONFIG_MMU
246 #if defined(CONFIG_32BIT)
247 	strncpy(sv_type, "sv32", 5);
248 #elif defined(CONFIG_64BIT)
249 	if (pgtable_l5_enabled)
250 		strncpy(sv_type, "sv57", 5);
251 	else if (pgtable_l4_enabled)
252 		strncpy(sv_type, "sv48", 5);
253 	else
254 		strncpy(sv_type, "sv39", 5);
255 #endif
256 #else
257 	strncpy(sv_type, "none", 5);
258 #endif /* CONFIG_MMU */
259 	seq_printf(f, "mmu\t\t: %s\n", sv_type);
260 }
261 
262 static void *c_start(struct seq_file *m, loff_t *pos)
263 {
264 	if (*pos == nr_cpu_ids)
265 		return NULL;
266 
267 	*pos = cpumask_next(*pos - 1, cpu_online_mask);
268 	if ((*pos) < nr_cpu_ids)
269 		return (void *)(uintptr_t)(1 + *pos);
270 	return NULL;
271 }
272 
273 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
274 {
275 	(*pos)++;
276 	return c_start(m, pos);
277 }
278 
279 static void c_stop(struct seq_file *m, void *v)
280 {
281 }
282 
283 static int c_show(struct seq_file *m, void *v)
284 {
285 	unsigned long cpu_id = (unsigned long)v - 1;
286 	struct device_node *node = of_get_cpu_node(cpu_id, NULL);
287 	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
288 	const char *compat, *isa;
289 
290 	seq_printf(m, "processor\t: %lu\n", cpu_id);
291 	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
292 	if (!of_property_read_string(node, "riscv,isa", &isa))
293 		print_isa(m, isa);
294 	print_mmu(m);
295 	if (!of_property_read_string(node, "compatible", &compat)
296 	    && strcmp(compat, "riscv"))
297 		seq_printf(m, "uarch\t\t: %s\n", compat);
298 	seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
299 	seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
300 	seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
301 	seq_puts(m, "\n");
302 	of_node_put(node);
303 
304 	return 0;
305 }
306 
307 const struct seq_operations cpuinfo_op = {
308 	.start	= c_start,
309 	.next	= c_next,
310 	.stop	= c_stop,
311 	.show	= c_show
312 };
313 
314 #endif /* CONFIG_PROC_FS */
315