xref: /openbmc/linux/arch/riscv/kernel/cpu.c (revision 603c09f2)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2012 Regents of the University of California
4  */
5 
6 #include <linux/init.h>
7 #include <linux/seq_file.h>
8 #include <linux/of.h>
9 #include <asm/hwcap.h>
10 #include <asm/smp.h>
11 #include <asm/pgtable.h>
12 
13 /*
14  * Returns the hart ID of the given device tree node, or -ENODEV if the node
15  * isn't an enabled and valid RISC-V hart node.
16  */
17 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
18 {
19 	const char *isa;
20 
21 	if (!of_device_is_compatible(node, "riscv")) {
22 		pr_warn("Found incompatible CPU\n");
23 		return -ENODEV;
24 	}
25 
26 	*hart = (unsigned long) of_get_cpu_hwid(node, 0);
27 	if (*hart == ~0UL) {
28 		pr_warn("Found CPU without hart ID\n");
29 		return -ENODEV;
30 	}
31 
32 	if (!of_device_is_available(node)) {
33 		pr_info("CPU with hartid=%lu is not available\n", *hart);
34 		return -ENODEV;
35 	}
36 
37 	if (of_property_read_string(node, "riscv,isa", &isa)) {
38 		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
39 		return -ENODEV;
40 	}
41 	if (isa[0] != 'r' || isa[1] != 'v') {
42 		pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
43 		return -ENODEV;
44 	}
45 
46 	return 0;
47 }
48 
49 /*
50  * Find hart ID of the CPU DT node under which given DT node falls.
51  *
52  * To achieve this, we walk up the DT tree until we find an active
53  * RISC-V core (HART) node and extract the cpuid from it.
54  */
55 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
56 {
57 	int rc;
58 
59 	for (; node; node = node->parent) {
60 		if (of_device_is_compatible(node, "riscv")) {
61 			rc = riscv_of_processor_hartid(node, hartid);
62 			if (!rc)
63 				return 0;
64 		}
65 	}
66 
67 	return -1;
68 }
69 
70 #ifdef CONFIG_PROC_FS
71 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
72 	{							\
73 		.uprop = #UPROP,				\
74 		.isa_ext_id = EXTID,				\
75 	}
76 /*
77  * Here are the ordering rules of extension naming defined by RISC-V
78  * specification :
79  * 1. All extensions should be separated from other multi-letter extensions
80  *    by an underscore.
81  * 2. The first letter following the 'Z' conventionally indicates the most
82  *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
83  *    If multiple 'Z' extensions are named, they should be ordered first
84  *    by category, then alphabetically within a category.
85  * 3. Standard supervisor-level extensions (starts with 'S') should be
86  *    listed after standard unprivileged extensions.  If multiple
87  *    supervisor-level extensions are listed, they should be ordered
88  *    alphabetically.
89  * 4. Non-standard extensions (starts with 'X') must be listed after all
90  *    standard extensions. They must be separated from other multi-letter
91  *    extensions by an underscore.
92  */
93 static struct riscv_isa_ext_data isa_ext_arr[] = {
94 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
95 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
96 	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
97 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
98 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
99 	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
100 };
101 
102 static void print_isa_ext(struct seq_file *f)
103 {
104 	struct riscv_isa_ext_data *edata;
105 	int i = 0, arr_sz;
106 
107 	arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
108 
109 	/* No extension support available */
110 	if (arr_sz <= 0)
111 		return;
112 
113 	for (i = 0; i <= arr_sz; i++) {
114 		edata = &isa_ext_arr[i];
115 		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
116 			continue;
117 		seq_printf(f, "_%s", edata->uprop);
118 	}
119 }
120 
121 /*
122  * These are the only valid base (single letter) ISA extensions as per the spec.
123  * It also specifies the canonical order in which it appears in the spec.
124  * Some of the extension may just be a place holder for now (B, K, P, J).
125  * This should be updated once corresponding extensions are ratified.
126  */
127 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
128 
129 static void print_isa(struct seq_file *f, const char *isa)
130 {
131 	int i;
132 
133 	seq_puts(f, "isa\t\t: ");
134 	/* Print the rv[64/32] part */
135 	seq_write(f, isa, 4);
136 	for (i = 0; i < sizeof(base_riscv_exts); i++) {
137 		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
138 			/* Print only enabled the base ISA extensions */
139 			seq_write(f, &base_riscv_exts[i], 1);
140 	}
141 	print_isa_ext(f);
142 	seq_puts(f, "\n");
143 }
144 
145 static void print_mmu(struct seq_file *f)
146 {
147 	char sv_type[16];
148 
149 #ifdef CONFIG_MMU
150 #if defined(CONFIG_32BIT)
151 	strncpy(sv_type, "sv32", 5);
152 #elif defined(CONFIG_64BIT)
153 	if (pgtable_l5_enabled)
154 		strncpy(sv_type, "sv57", 5);
155 	else if (pgtable_l4_enabled)
156 		strncpy(sv_type, "sv48", 5);
157 	else
158 		strncpy(sv_type, "sv39", 5);
159 #endif
160 #else
161 	strncpy(sv_type, "none", 5);
162 #endif /* CONFIG_MMU */
163 	seq_printf(f, "mmu\t\t: %s\n", sv_type);
164 }
165 
166 static void *c_start(struct seq_file *m, loff_t *pos)
167 {
168 	*pos = cpumask_next(*pos - 1, cpu_online_mask);
169 	if ((*pos) < nr_cpu_ids)
170 		return (void *)(uintptr_t)(1 + *pos);
171 	return NULL;
172 }
173 
174 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
175 {
176 	(*pos)++;
177 	return c_start(m, pos);
178 }
179 
180 static void c_stop(struct seq_file *m, void *v)
181 {
182 }
183 
184 static int c_show(struct seq_file *m, void *v)
185 {
186 	unsigned long cpu_id = (unsigned long)v - 1;
187 	struct device_node *node = of_get_cpu_node(cpu_id, NULL);
188 	const char *compat, *isa;
189 
190 	seq_printf(m, "processor\t: %lu\n", cpu_id);
191 	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
192 	if (!of_property_read_string(node, "riscv,isa", &isa))
193 		print_isa(m, isa);
194 	print_mmu(m);
195 	if (!of_property_read_string(node, "compatible", &compat)
196 	    && strcmp(compat, "riscv"))
197 		seq_printf(m, "uarch\t\t: %s\n", compat);
198 	seq_puts(m, "\n");
199 	of_node_put(node);
200 
201 	return 0;
202 }
203 
204 const struct seq_operations cpuinfo_op = {
205 	.start	= c_start,
206 	.next	= c_next,
207 	.stop	= c_stop,
208 	.show	= c_show
209 };
210 
211 #endif /* CONFIG_PROC_FS */
212