1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/cpu.h> 8 #include <linux/ctype.h> 9 #include <linux/init.h> 10 #include <linux/seq_file.h> 11 #include <linux/of.h> 12 #include <asm/acpi.h> 13 #include <asm/cpufeature.h> 14 #include <asm/csr.h> 15 #include <asm/hwcap.h> 16 #include <asm/sbi.h> 17 #include <asm/smp.h> 18 #include <asm/pgtable.h> 19 20 /* 21 * Returns the hart ID of the given device tree node, or -ENODEV if the node 22 * isn't an enabled and valid RISC-V hart node. 23 */ 24 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) 25 { 26 int cpu; 27 28 *hart = (unsigned long)of_get_cpu_hwid(node, 0); 29 if (*hart == ~0UL) { 30 pr_warn("Found CPU without hart ID\n"); 31 return -ENODEV; 32 } 33 34 cpu = riscv_hartid_to_cpuid(*hart); 35 if (cpu < 0) 36 return cpu; 37 38 if (!cpu_possible(cpu)) 39 return -ENODEV; 40 41 return 0; 42 } 43 44 int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) 45 { 46 const char *isa; 47 48 if (!of_device_is_compatible(node, "riscv")) { 49 pr_warn("Found incompatible CPU\n"); 50 return -ENODEV; 51 } 52 53 *hart = (unsigned long)of_get_cpu_hwid(node, 0); 54 if (*hart == ~0UL) { 55 pr_warn("Found CPU without hart ID\n"); 56 return -ENODEV; 57 } 58 59 if (!of_device_is_available(node)) { 60 pr_info("CPU with hartid=%lu is not available\n", *hart); 61 return -ENODEV; 62 } 63 64 if (of_property_read_string(node, "riscv,isa", &isa)) { 65 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); 66 return -ENODEV; 67 } 68 69 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) 70 return -ENODEV; 71 72 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) 73 return -ENODEV; 74 75 return 0; 76 } 77 78 /* 79 * Find hart ID of the CPU DT node under which given DT node falls. 80 * 81 * To achieve this, we walk up the DT tree until we find an active 82 * RISC-V core (HART) node and extract the cpuid from it. 83 */ 84 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) 85 { 86 int rc; 87 88 for (; node; node = node->parent) { 89 if (of_device_is_compatible(node, "riscv")) { 90 rc = riscv_of_processor_hartid(node, hartid); 91 if (!rc) 92 return 0; 93 } 94 } 95 96 return -1; 97 } 98 99 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); 100 101 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) 102 { 103 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 104 105 return ci->mvendorid; 106 } 107 EXPORT_SYMBOL(riscv_cached_mvendorid); 108 109 unsigned long riscv_cached_marchid(unsigned int cpu_id) 110 { 111 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 112 113 return ci->marchid; 114 } 115 EXPORT_SYMBOL(riscv_cached_marchid); 116 117 unsigned long riscv_cached_mimpid(unsigned int cpu_id) 118 { 119 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 120 121 return ci->mimpid; 122 } 123 EXPORT_SYMBOL(riscv_cached_mimpid); 124 125 static int riscv_cpuinfo_starting(unsigned int cpu) 126 { 127 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); 128 129 #if IS_ENABLED(CONFIG_RISCV_SBI) 130 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); 131 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); 132 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); 133 #elif IS_ENABLED(CONFIG_RISCV_M_MODE) 134 ci->mvendorid = csr_read(CSR_MVENDORID); 135 ci->marchid = csr_read(CSR_MARCHID); 136 ci->mimpid = csr_read(CSR_MIMPID); 137 #else 138 ci->mvendorid = 0; 139 ci->marchid = 0; 140 ci->mimpid = 0; 141 #endif 142 143 return 0; 144 } 145 146 static int __init riscv_cpuinfo_init(void) 147 { 148 int ret; 149 150 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", 151 riscv_cpuinfo_starting, NULL); 152 if (ret < 0) { 153 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 154 return ret; 155 } 156 157 return 0; 158 } 159 arch_initcall(riscv_cpuinfo_init); 160 161 #ifdef CONFIG_PROC_FS 162 163 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ 164 { \ 165 .uprop = #UPROP, \ 166 .isa_ext_id = EXTID, \ 167 } 168 169 /* 170 * The canonical order of ISA extension names in the ISA string is defined in 171 * chapter 27 of the unprivileged specification. 172 * 173 * Ordinarily, for in-kernel data structures, this order is unimportant but 174 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. 175 * 176 * The specification uses vague wording, such as should, when it comes to 177 * ordering, so for our purposes the following rules apply: 178 * 179 * 1. All multi-letter extensions must be separated from other extensions by an 180 * underscore. 181 * 182 * 2. Additional standard extensions (starting with 'Z') must be sorted after 183 * single-letter extensions and before any higher-privileged extensions. 184 185 * 3. The first letter following the 'Z' conventionally indicates the most 186 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 187 * If multiple 'Z' extensions are named, they must be ordered first by 188 * category, then alphabetically within a category. 189 * 190 * 3. Standard supervisor-level extensions (starting with 'S') must be listed 191 * after standard unprivileged extensions. If multiple supervisor-level 192 * extensions are listed, they must be ordered alphabetically. 193 * 194 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed 195 * after any lower-privileged, standard extensions. If multiple 196 * machine-level extensions are listed, they must be ordered 197 * alphabetically. 198 * 199 * 5. Non-standard extensions (starting with 'X') must be listed after all 200 * standard extensions. If multiple non-standard extensions are listed, they 201 * must be ordered alphabetically. 202 * 203 * An example string following the order is: 204 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux 205 * 206 * New entries to this struct should follow the ordering rules described above. 207 */ 208 static struct riscv_isa_ext_data isa_ext_arr[] = { 209 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), 210 __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), 211 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), 212 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), 213 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), 214 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), 215 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), 216 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), 217 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), 218 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), 219 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), 220 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), 221 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 222 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), 223 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 224 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), 225 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 226 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), 227 }; 228 229 static void print_isa_ext(struct seq_file *f) 230 { 231 struct riscv_isa_ext_data *edata; 232 int i = 0, arr_sz; 233 234 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; 235 236 /* No extension support available */ 237 if (arr_sz <= 0) 238 return; 239 240 for (i = 0; i <= arr_sz; i++) { 241 edata = &isa_ext_arr[i]; 242 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) 243 continue; 244 seq_printf(f, "_%s", edata->uprop); 245 } 246 } 247 248 /* 249 * These are the only valid base (single letter) ISA extensions as per the spec. 250 * It also specifies the canonical order in which it appears in the spec. 251 * Some of the extension may just be a place holder for now (B, K, P, J). 252 * This should be updated once corresponding extensions are ratified. 253 */ 254 static const char base_riscv_exts[13] = "imafdqcbkjpvh"; 255 256 static void print_isa(struct seq_file *f, const char *isa) 257 { 258 int i; 259 260 seq_puts(f, "isa\t\t: "); 261 /* Print the rv[64/32] part */ 262 seq_write(f, isa, 4); 263 for (i = 0; i < sizeof(base_riscv_exts); i++) { 264 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) 265 /* Print only enabled the base ISA extensions */ 266 seq_write(f, &base_riscv_exts[i], 1); 267 } 268 print_isa_ext(f); 269 seq_puts(f, "\n"); 270 } 271 272 static void print_mmu(struct seq_file *f) 273 { 274 char sv_type[16]; 275 276 #ifdef CONFIG_MMU 277 #if defined(CONFIG_32BIT) 278 strncpy(sv_type, "sv32", 5); 279 #elif defined(CONFIG_64BIT) 280 if (pgtable_l5_enabled) 281 strncpy(sv_type, "sv57", 5); 282 else if (pgtable_l4_enabled) 283 strncpy(sv_type, "sv48", 5); 284 else 285 strncpy(sv_type, "sv39", 5); 286 #endif 287 #else 288 strncpy(sv_type, "none", 5); 289 #endif /* CONFIG_MMU */ 290 seq_printf(f, "mmu\t\t: %s\n", sv_type); 291 } 292 293 static void *c_start(struct seq_file *m, loff_t *pos) 294 { 295 if (*pos == nr_cpu_ids) 296 return NULL; 297 298 *pos = cpumask_next(*pos - 1, cpu_online_mask); 299 if ((*pos) < nr_cpu_ids) 300 return (void *)(uintptr_t)(1 + *pos); 301 return NULL; 302 } 303 304 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 305 { 306 (*pos)++; 307 return c_start(m, pos); 308 } 309 310 static void c_stop(struct seq_file *m, void *v) 311 { 312 } 313 314 static int c_show(struct seq_file *m, void *v) 315 { 316 unsigned long cpu_id = (unsigned long)v - 1; 317 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 318 struct device_node *node; 319 const char *compat, *isa; 320 321 seq_printf(m, "processor\t: %lu\n", cpu_id); 322 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); 323 324 if (acpi_disabled) { 325 node = of_get_cpu_node(cpu_id, NULL); 326 if (!of_property_read_string(node, "riscv,isa", &isa)) 327 print_isa(m, isa); 328 329 print_mmu(m); 330 if (!of_property_read_string(node, "compatible", &compat) && 331 strcmp(compat, "riscv")) 332 seq_printf(m, "uarch\t\t: %s\n", compat); 333 334 of_node_put(node); 335 } else { 336 if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) 337 print_isa(m, isa); 338 339 print_mmu(m); 340 } 341 342 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); 343 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); 344 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); 345 seq_puts(m, "\n"); 346 347 return 0; 348 } 349 350 const struct seq_operations cpuinfo_op = { 351 .start = c_start, 352 .next = c_next, 353 .stop = c_stop, 354 .show = c_show 355 }; 356 357 #endif /* CONFIG_PROC_FS */ 358