1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #include <linux/cpu.h> 7 #include <linux/init.h> 8 #include <linux/seq_file.h> 9 #include <linux/of.h> 10 #include <asm/csr.h> 11 #include <asm/hwcap.h> 12 #include <asm/sbi.h> 13 #include <asm/smp.h> 14 #include <asm/pgtable.h> 15 16 /* 17 * Returns the hart ID of the given device tree node, or -ENODEV if the node 18 * isn't an enabled and valid RISC-V hart node. 19 */ 20 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) 21 { 22 const char *isa; 23 24 if (!of_device_is_compatible(node, "riscv")) { 25 pr_warn("Found incompatible CPU\n"); 26 return -ENODEV; 27 } 28 29 *hart = (unsigned long) of_get_cpu_hwid(node, 0); 30 if (*hart == ~0UL) { 31 pr_warn("Found CPU without hart ID\n"); 32 return -ENODEV; 33 } 34 35 if (!of_device_is_available(node)) { 36 pr_info("CPU with hartid=%lu is not available\n", *hart); 37 return -ENODEV; 38 } 39 40 if (of_property_read_string(node, "riscv,isa", &isa)) { 41 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); 42 return -ENODEV; 43 } 44 if (isa[0] != 'r' || isa[1] != 'v') { 45 pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); 46 return -ENODEV; 47 } 48 49 return 0; 50 } 51 52 /* 53 * Find hart ID of the CPU DT node under which given DT node falls. 54 * 55 * To achieve this, we walk up the DT tree until we find an active 56 * RISC-V core (HART) node and extract the cpuid from it. 57 */ 58 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) 59 { 60 int rc; 61 62 for (; node; node = node->parent) { 63 if (of_device_is_compatible(node, "riscv")) { 64 rc = riscv_of_processor_hartid(node, hartid); 65 if (!rc) 66 return 0; 67 } 68 } 69 70 return -1; 71 } 72 73 struct riscv_cpuinfo { 74 unsigned long mvendorid; 75 unsigned long marchid; 76 unsigned long mimpid; 77 }; 78 static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); 79 80 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) 81 { 82 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 83 84 return ci->mvendorid; 85 } 86 EXPORT_SYMBOL(riscv_cached_mvendorid); 87 88 unsigned long riscv_cached_marchid(unsigned int cpu_id) 89 { 90 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 91 92 return ci->marchid; 93 } 94 EXPORT_SYMBOL(riscv_cached_marchid); 95 96 unsigned long riscv_cached_mimpid(unsigned int cpu_id) 97 { 98 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 99 100 return ci->mimpid; 101 } 102 EXPORT_SYMBOL(riscv_cached_mimpid); 103 104 static int riscv_cpuinfo_starting(unsigned int cpu) 105 { 106 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); 107 108 #if IS_ENABLED(CONFIG_RISCV_SBI) 109 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); 110 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); 111 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); 112 #elif IS_ENABLED(CONFIG_RISCV_M_MODE) 113 ci->mvendorid = csr_read(CSR_MVENDORID); 114 ci->marchid = csr_read(CSR_MARCHID); 115 ci->mimpid = csr_read(CSR_MIMPID); 116 #else 117 ci->mvendorid = 0; 118 ci->marchid = 0; 119 ci->mimpid = 0; 120 #endif 121 122 return 0; 123 } 124 125 static int __init riscv_cpuinfo_init(void) 126 { 127 int ret; 128 129 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", 130 riscv_cpuinfo_starting, NULL); 131 if (ret < 0) { 132 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 133 return ret; 134 } 135 136 return 0; 137 } 138 arch_initcall(riscv_cpuinfo_init); 139 140 #ifdef CONFIG_PROC_FS 141 142 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ 143 { \ 144 .uprop = #UPROP, \ 145 .isa_ext_id = EXTID, \ 146 } 147 /* 148 * Here are the ordering rules of extension naming defined by RISC-V 149 * specification : 150 * 1. All extensions should be separated from other multi-letter extensions 151 * by an underscore. 152 * 2. The first letter following the 'Z' conventionally indicates the most 153 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 154 * If multiple 'Z' extensions are named, they should be ordered first 155 * by category, then alphabetically within a category. 156 * 3. Standard supervisor-level extensions (starts with 'S') should be 157 * listed after standard unprivileged extensions. If multiple 158 * supervisor-level extensions are listed, they should be ordered 159 * alphabetically. 160 * 4. Non-standard extensions (starts with 'X') must be listed after all 161 * standard extensions. They must be separated from other multi-letter 162 * extensions by an underscore. 163 */ 164 static struct riscv_isa_ext_data isa_ext_arr[] = { 165 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 166 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), 167 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 168 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 169 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), 170 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), 171 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), 172 }; 173 174 static void print_isa_ext(struct seq_file *f) 175 { 176 struct riscv_isa_ext_data *edata; 177 int i = 0, arr_sz; 178 179 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; 180 181 /* No extension support available */ 182 if (arr_sz <= 0) 183 return; 184 185 for (i = 0; i <= arr_sz; i++) { 186 edata = &isa_ext_arr[i]; 187 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) 188 continue; 189 seq_printf(f, "_%s", edata->uprop); 190 } 191 } 192 193 /* 194 * These are the only valid base (single letter) ISA extensions as per the spec. 195 * It also specifies the canonical order in which it appears in the spec. 196 * Some of the extension may just be a place holder for now (B, K, P, J). 197 * This should be updated once corresponding extensions are ratified. 198 */ 199 static const char base_riscv_exts[13] = "imafdqcbkjpvh"; 200 201 static void print_isa(struct seq_file *f, const char *isa) 202 { 203 int i; 204 205 seq_puts(f, "isa\t\t: "); 206 /* Print the rv[64/32] part */ 207 seq_write(f, isa, 4); 208 for (i = 0; i < sizeof(base_riscv_exts); i++) { 209 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) 210 /* Print only enabled the base ISA extensions */ 211 seq_write(f, &base_riscv_exts[i], 1); 212 } 213 print_isa_ext(f); 214 seq_puts(f, "\n"); 215 } 216 217 static void print_mmu(struct seq_file *f) 218 { 219 char sv_type[16]; 220 221 #ifdef CONFIG_MMU 222 #if defined(CONFIG_32BIT) 223 strncpy(sv_type, "sv32", 5); 224 #elif defined(CONFIG_64BIT) 225 if (pgtable_l5_enabled) 226 strncpy(sv_type, "sv57", 5); 227 else if (pgtable_l4_enabled) 228 strncpy(sv_type, "sv48", 5); 229 else 230 strncpy(sv_type, "sv39", 5); 231 #endif 232 #else 233 strncpy(sv_type, "none", 5); 234 #endif /* CONFIG_MMU */ 235 seq_printf(f, "mmu\t\t: %s\n", sv_type); 236 } 237 238 static void *c_start(struct seq_file *m, loff_t *pos) 239 { 240 if (*pos == nr_cpu_ids) 241 return NULL; 242 243 *pos = cpumask_next(*pos - 1, cpu_online_mask); 244 if ((*pos) < nr_cpu_ids) 245 return (void *)(uintptr_t)(1 + *pos); 246 return NULL; 247 } 248 249 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 250 { 251 (*pos)++; 252 return c_start(m, pos); 253 } 254 255 static void c_stop(struct seq_file *m, void *v) 256 { 257 } 258 259 static int c_show(struct seq_file *m, void *v) 260 { 261 unsigned long cpu_id = (unsigned long)v - 1; 262 struct device_node *node = of_get_cpu_node(cpu_id, NULL); 263 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 264 const char *compat, *isa; 265 266 seq_printf(m, "processor\t: %lu\n", cpu_id); 267 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); 268 if (!of_property_read_string(node, "riscv,isa", &isa)) 269 print_isa(m, isa); 270 print_mmu(m); 271 if (!of_property_read_string(node, "compatible", &compat) 272 && strcmp(compat, "riscv")) 273 seq_printf(m, "uarch\t\t: %s\n", compat); 274 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); 275 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); 276 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); 277 seq_puts(m, "\n"); 278 of_node_put(node); 279 280 return 0; 281 } 282 283 const struct seq_operations cpuinfo_op = { 284 .start = c_start, 285 .next = c_next, 286 .stop = c_stop, 287 .show = c_show 288 }; 289 290 #endif /* CONFIG_PROC_FS */ 291