1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * alternative runtime patching 4 * inspired by the ARM64 and x86 version 5 * 6 * Copyright (C) 2021 Sifive. 7 */ 8 9 #include <linux/init.h> 10 #include <linux/module.h> 11 #include <linux/cpu.h> 12 #include <linux/uaccess.h> 13 #include <asm/alternative.h> 14 #include <asm/module.h> 15 #include <asm/sections.h> 16 #include <asm/vdso.h> 17 #include <asm/vendorid_list.h> 18 #include <asm/sbi.h> 19 #include <asm/csr.h> 20 #include <asm/insn.h> 21 #include <asm/patch.h> 22 23 struct cpu_manufacturer_info_t { 24 unsigned long vendor_id; 25 unsigned long arch_id; 26 unsigned long imp_id; 27 void (*patch_func)(struct alt_entry *begin, struct alt_entry *end, 28 unsigned long archid, unsigned long impid, 29 unsigned int stage); 30 void (*feature_probe_func)(unsigned int cpu, unsigned long archid, 31 unsigned long impid); 32 }; 33 34 static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info) 35 { 36 #ifdef CONFIG_RISCV_M_MODE 37 cpu_mfr_info->vendor_id = csr_read(CSR_MVENDORID); 38 cpu_mfr_info->arch_id = csr_read(CSR_MARCHID); 39 cpu_mfr_info->imp_id = csr_read(CSR_MIMPID); 40 #else 41 cpu_mfr_info->vendor_id = sbi_get_mvendorid(); 42 cpu_mfr_info->arch_id = sbi_get_marchid(); 43 cpu_mfr_info->imp_id = sbi_get_mimpid(); 44 #endif 45 46 cpu_mfr_info->feature_probe_func = NULL; 47 switch (cpu_mfr_info->vendor_id) { 48 #ifdef CONFIG_ERRATA_SIFIVE 49 case SIFIVE_VENDOR_ID: 50 cpu_mfr_info->patch_func = sifive_errata_patch_func; 51 break; 52 #endif 53 #ifdef CONFIG_ERRATA_THEAD 54 case THEAD_VENDOR_ID: 55 cpu_mfr_info->patch_func = thead_errata_patch_func; 56 cpu_mfr_info->feature_probe_func = thead_feature_probe_func; 57 break; 58 #endif 59 default: 60 cpu_mfr_info->patch_func = NULL; 61 } 62 } 63 64 static u32 riscv_instruction_at(void *p) 65 { 66 u16 *parcel = p; 67 68 return (u32)parcel[0] | (u32)parcel[1] << 16; 69 } 70 71 static void riscv_alternative_fix_auipc_jalr(void *ptr, u32 auipc_insn, 72 u32 jalr_insn, int patch_offset) 73 { 74 u32 call[2] = { auipc_insn, jalr_insn }; 75 s32 imm; 76 77 /* get and adjust new target address */ 78 imm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn); 79 imm -= patch_offset; 80 81 /* update instructions */ 82 riscv_insn_insert_utype_itype_imm(&call[0], &call[1], imm); 83 84 /* patch the call place again */ 85 patch_text_nosync(ptr, call, sizeof(u32) * 2); 86 } 87 88 static void riscv_alternative_fix_jal(void *ptr, u32 jal_insn, int patch_offset) 89 { 90 s32 imm; 91 92 /* get and adjust new target address */ 93 imm = riscv_insn_extract_jtype_imm(jal_insn); 94 imm -= patch_offset; 95 96 /* update instruction */ 97 riscv_insn_insert_jtype_imm(&jal_insn, imm); 98 99 /* patch the call place again */ 100 patch_text_nosync(ptr, &jal_insn, sizeof(u32)); 101 } 102 103 void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len, 104 int patch_offset) 105 { 106 int num_insn = len / sizeof(u32); 107 int i; 108 109 for (i = 0; i < num_insn; i++) { 110 u32 insn = riscv_instruction_at(alt_ptr + i * sizeof(u32)); 111 112 /* 113 * May be the start of an auipc + jalr pair 114 * Needs to check that at least one more instruction 115 * is in the list. 116 */ 117 if (riscv_insn_is_auipc(insn) && i < num_insn - 1) { 118 u32 insn2 = riscv_instruction_at(alt_ptr + (i + 1) * sizeof(u32)); 119 120 if (!riscv_insn_is_jalr(insn2)) 121 continue; 122 123 /* if instruction pair is a call, it will use the ra register */ 124 if (RV_EXTRACT_RD_REG(insn) != 1) 125 continue; 126 127 riscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32), 128 insn, insn2, patch_offset); 129 i++; 130 } 131 132 if (riscv_insn_is_jal(insn)) { 133 s32 imm = riscv_insn_extract_jtype_imm(insn); 134 135 /* Don't modify jumps inside the alternative block */ 136 if ((alt_ptr + i * sizeof(u32) + imm) >= alt_ptr && 137 (alt_ptr + i * sizeof(u32) + imm) < (alt_ptr + len)) 138 continue; 139 140 riscv_alternative_fix_jal(alt_ptr + i * sizeof(u32), 141 insn, patch_offset); 142 } 143 } 144 } 145 146 /* Called on each CPU as it starts */ 147 void probe_vendor_features(unsigned int cpu) 148 { 149 struct cpu_manufacturer_info_t cpu_mfr_info; 150 151 riscv_fill_cpu_mfr_info(&cpu_mfr_info); 152 if (!cpu_mfr_info.feature_probe_func) 153 return; 154 155 cpu_mfr_info.feature_probe_func(cpu, 156 cpu_mfr_info.arch_id, 157 cpu_mfr_info.imp_id); 158 } 159 160 /* 161 * This is called very early in the boot process (directly after we run 162 * a feature detect on the boot CPU). No need to worry about other CPUs 163 * here. 164 */ 165 static void __init_or_module _apply_alternatives(struct alt_entry *begin, 166 struct alt_entry *end, 167 unsigned int stage) 168 { 169 struct cpu_manufacturer_info_t cpu_mfr_info; 170 171 riscv_fill_cpu_mfr_info(&cpu_mfr_info); 172 173 riscv_cpufeature_patch_func(begin, end, stage); 174 175 if (!cpu_mfr_info.patch_func) 176 return; 177 178 cpu_mfr_info.patch_func(begin, end, 179 cpu_mfr_info.arch_id, 180 cpu_mfr_info.imp_id, 181 stage); 182 } 183 184 #ifdef CONFIG_MMU 185 static void __init apply_vdso_alternatives(void) 186 { 187 const Elf_Ehdr *hdr; 188 const Elf_Shdr *shdr; 189 const Elf_Shdr *alt; 190 struct alt_entry *begin, *end; 191 192 hdr = (Elf_Ehdr *)vdso_start; 193 shdr = (void *)hdr + hdr->e_shoff; 194 alt = find_section(hdr, shdr, ".alternative"); 195 if (!alt) 196 return; 197 198 begin = (void *)hdr + alt->sh_offset, 199 end = (void *)hdr + alt->sh_offset + alt->sh_size, 200 201 _apply_alternatives((struct alt_entry *)begin, 202 (struct alt_entry *)end, 203 RISCV_ALTERNATIVES_BOOT); 204 } 205 #else 206 static void __init apply_vdso_alternatives(void) { } 207 #endif 208 209 void __init apply_boot_alternatives(void) 210 { 211 /* If called on non-boot cpu things could go wrong */ 212 WARN_ON(smp_processor_id() != 0); 213 214 probe_vendor_features(0); 215 _apply_alternatives((struct alt_entry *)__alt_start, 216 (struct alt_entry *)__alt_end, 217 RISCV_ALTERNATIVES_BOOT); 218 219 apply_vdso_alternatives(); 220 } 221 222 /* 223 * apply_early_boot_alternatives() is called from setup_vm() with MMU-off. 224 * 225 * Following requirements should be honoured for it to work correctly: 226 * 1) It should use PC-relative addressing for accessing kernel symbols. 227 * To achieve this we always use GCC cmodel=medany. 228 * 2) The compiler instrumentation for FTRACE will not work for setup_vm() 229 * so disable compiler instrumentation when FTRACE is enabled. 230 * 231 * Currently, the above requirements are honoured by using custom CFLAGS 232 * for alternative.o in kernel/Makefile. 233 */ 234 void __init apply_early_boot_alternatives(void) 235 { 236 #ifdef CONFIG_RISCV_ALTERNATIVE_EARLY 237 _apply_alternatives((struct alt_entry *)__alt_start, 238 (struct alt_entry *)__alt_end, 239 RISCV_ALTERNATIVES_EARLY_BOOT); 240 #endif 241 } 242 243 #ifdef CONFIG_MODULES 244 void apply_module_alternatives(void *start, size_t length) 245 { 246 _apply_alternatives((struct alt_entry *)start, 247 (struct alt_entry *)(start + length), 248 RISCV_ALTERNATIVES_MODULE); 249 } 250 #endif 251