1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #ifndef __LINUX_KVM_RISCV_H 10 #define __LINUX_KVM_RISCV_H 11 12 #ifndef __ASSEMBLY__ 13 14 #include <linux/types.h> 15 #include <asm/bitsperlong.h> 16 #include <asm/ptrace.h> 17 18 #define __KVM_HAVE_IRQ_LINE 19 #define __KVM_HAVE_READONLY_MEM 20 21 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 22 23 #define KVM_INTERRUPT_SET -1U 24 #define KVM_INTERRUPT_UNSET -2U 25 26 /* for KVM_GET_REGS and KVM_SET_REGS */ 27 struct kvm_regs { 28 }; 29 30 /* for KVM_GET_FPU and KVM_SET_FPU */ 31 struct kvm_fpu { 32 }; 33 34 /* KVM Debug exit structure */ 35 struct kvm_debug_exit_arch { 36 }; 37 38 /* for KVM_SET_GUEST_DEBUG */ 39 struct kvm_guest_debug_arch { 40 }; 41 42 /* definition of registers in kvm_run */ 43 struct kvm_sync_regs { 44 }; 45 46 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 47 struct kvm_sregs { 48 }; 49 50 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 51 struct kvm_riscv_config { 52 unsigned long isa; 53 unsigned long zicbom_block_size; 54 unsigned long mvendorid; 55 unsigned long marchid; 56 unsigned long mimpid; 57 unsigned long zicboz_block_size; 58 }; 59 60 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 61 struct kvm_riscv_core { 62 struct user_regs_struct regs; 63 unsigned long mode; 64 }; 65 66 /* Possible privilege modes for kvm_riscv_core */ 67 #define KVM_RISCV_MODE_S 1 68 #define KVM_RISCV_MODE_U 0 69 70 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 71 struct kvm_riscv_csr { 72 unsigned long sstatus; 73 unsigned long sie; 74 unsigned long stvec; 75 unsigned long sscratch; 76 unsigned long sepc; 77 unsigned long scause; 78 unsigned long stval; 79 unsigned long sip; 80 unsigned long satp; 81 unsigned long scounteren; 82 }; 83 84 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 85 struct kvm_riscv_aia_csr { 86 unsigned long siselect; 87 unsigned long iprio1; 88 unsigned long iprio2; 89 unsigned long sieh; 90 unsigned long siph; 91 unsigned long iprio1h; 92 unsigned long iprio2h; 93 }; 94 95 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 96 struct kvm_riscv_timer { 97 __u64 frequency; 98 __u64 time; 99 __u64 compare; 100 __u64 state; 101 }; 102 103 /* 104 * ISA extension IDs specific to KVM. This is not the same as the host ISA 105 * extension IDs as that is internal to the host and should not be exposed 106 * to the guest. This should always be contiguous to keep the mapping simple 107 * in KVM implementation. 108 */ 109 enum KVM_RISCV_ISA_EXT_ID { 110 KVM_RISCV_ISA_EXT_A = 0, 111 KVM_RISCV_ISA_EXT_C, 112 KVM_RISCV_ISA_EXT_D, 113 KVM_RISCV_ISA_EXT_F, 114 KVM_RISCV_ISA_EXT_H, 115 KVM_RISCV_ISA_EXT_I, 116 KVM_RISCV_ISA_EXT_M, 117 KVM_RISCV_ISA_EXT_SVPBMT, 118 KVM_RISCV_ISA_EXT_SSTC, 119 KVM_RISCV_ISA_EXT_SVINVAL, 120 KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 121 KVM_RISCV_ISA_EXT_ZICBOM, 122 KVM_RISCV_ISA_EXT_ZICBOZ, 123 KVM_RISCV_ISA_EXT_ZBB, 124 KVM_RISCV_ISA_EXT_SSAIA, 125 KVM_RISCV_ISA_EXT_V, 126 KVM_RISCV_ISA_EXT_SVNAPOT, 127 KVM_RISCV_ISA_EXT_MAX, 128 }; 129 130 /* 131 * SBI extension IDs specific to KVM. This is not the same as the SBI 132 * extension IDs defined by the RISC-V SBI specification. 133 */ 134 enum KVM_RISCV_SBI_EXT_ID { 135 KVM_RISCV_SBI_EXT_V01 = 0, 136 KVM_RISCV_SBI_EXT_TIME, 137 KVM_RISCV_SBI_EXT_IPI, 138 KVM_RISCV_SBI_EXT_RFENCE, 139 KVM_RISCV_SBI_EXT_SRST, 140 KVM_RISCV_SBI_EXT_HSM, 141 KVM_RISCV_SBI_EXT_PMU, 142 KVM_RISCV_SBI_EXT_EXPERIMENTAL, 143 KVM_RISCV_SBI_EXT_VENDOR, 144 KVM_RISCV_SBI_EXT_MAX, 145 }; 146 147 /* Possible states for kvm_riscv_timer */ 148 #define KVM_RISCV_TIMER_STATE_OFF 0 149 #define KVM_RISCV_TIMER_STATE_ON 1 150 151 #define KVM_REG_SIZE(id) \ 152 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 153 154 /* If you need to interpret the index values, here is the key: */ 155 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 156 #define KVM_REG_RISCV_TYPE_SHIFT 24 157 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 158 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 159 160 /* Config registers are mapped as type 1 */ 161 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 162 #define KVM_REG_RISCV_CONFIG_REG(name) \ 163 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 164 165 /* Core registers are mapped as type 2 */ 166 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 167 #define KVM_REG_RISCV_CORE_REG(name) \ 168 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 169 170 /* Control and status registers are mapped as type 3 */ 171 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 172 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 173 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 174 #define KVM_REG_RISCV_CSR_REG(name) \ 175 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 176 #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 177 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 178 179 /* Timer registers are mapped as type 4 */ 180 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 181 #define KVM_REG_RISCV_TIMER_REG(name) \ 182 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 183 184 /* F extension registers are mapped as type 5 */ 185 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 186 #define KVM_REG_RISCV_FP_F_REG(name) \ 187 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 188 189 /* D extension registers are mapped as type 6 */ 190 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 191 #define KVM_REG_RISCV_FP_D_REG(name) \ 192 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 193 194 /* ISA Extension registers are mapped as type 7 */ 195 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 196 197 /* SBI extension registers are mapped as type 8 */ 198 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 199 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 200 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 201 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 202 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 203 ((__ext_id) / __BITS_PER_LONG) 204 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 205 (1UL << ((__ext_id) % __BITS_PER_LONG)) 206 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 207 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 208 209 /* V extension registers are mapped as type 9 */ 210 #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 211 #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 212 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 213 #define KVM_REG_RISCV_VECTOR_REG(n) \ 214 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 215 216 /* Device Control API: RISC-V AIA */ 217 #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 218 #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 219 #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 220 #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 221 #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 222 223 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 224 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 225 #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 226 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 227 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 228 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 229 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 230 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 231 232 /* 233 * Modes of RISC-V AIA device: 234 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC 235 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files 236 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever 237 * available otherwise fallback to trap-n-emulation 238 */ 239 #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 240 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 241 #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 242 243 #define KVM_DEV_RISCV_AIA_IDS_MIN 63 244 #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 245 #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 246 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 247 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 248 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 249 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 250 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 251 252 #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 253 #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 254 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 255 #define KVM_DEV_RISCV_AIA_ADDR_MAX \ 256 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 257 258 #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 259 #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 260 261 /* 262 * The device attribute type contains the memory mapped offset of the 263 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. 264 */ 265 #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 266 267 /* 268 * The lower 12-bits of the device attribute type contains the iselect 269 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order 270 * bits contains the VCPU id. 271 */ 272 #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 273 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 274 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ 275 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 276 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ 277 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ 278 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 279 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ 280 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 281 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ 282 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 283 284 /* One single KVM irqchip, ie. the AIA */ 285 #define KVM_NR_IRQCHIPS 1 286 287 #endif 288 289 #endif /* __LINUX_KVM_RISCV_H */ 290