1ad5d1122SVincent Chen /* SPDX-License-Identifier: GPL-2.0-only */
2ad5d1122SVincent Chen #ifndef __ASM_VDSO_PROCESSOR_H
3ad5d1122SVincent Chen #define __ASM_VDSO_PROCESSOR_H
4ad5d1122SVincent Chen 
5ad5d1122SVincent Chen #ifndef __ASSEMBLY__
6ad5d1122SVincent Chen 
730aca1baSRandy Dunlap #include <asm/barrier.h>
830aca1baSRandy Dunlap 
cpu_relax(void)9ad5d1122SVincent Chen static inline void cpu_relax(void)
10ad5d1122SVincent Chen {
11ad5d1122SVincent Chen #ifdef __riscv_muldiv
12ad5d1122SVincent Chen 	int dummy;
13ad5d1122SVincent Chen 	/* In lieu of a halt instruction, induce a long-latency stall. */
14ad5d1122SVincent Chen 	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
15ad5d1122SVincent Chen #endif
163c349eacSPalmer Dabbelt 
17*7aa18f77SMinda Chen #ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
188eb060e1SDao Lu 	/*
198eb060e1SDao Lu 	 * Reduce instruction retirement.
208eb060e1SDao Lu 	 * This assumes the PC changes.
218eb060e1SDao Lu 	 */
228eb060e1SDao Lu 	__asm__ __volatile__ ("pause");
238eb060e1SDao Lu #else
248eb060e1SDao Lu 	/* Encoding of the pause instruction */
258eb060e1SDao Lu 	__asm__ __volatile__ (".4byte 0x100000F");
268eb060e1SDao Lu #endif
27ad5d1122SVincent Chen 	barrier();
28ad5d1122SVincent Chen }
29ad5d1122SVincent Chen 
30ad5d1122SVincent Chen #endif /* __ASSEMBLY__ */
31ad5d1122SVincent Chen 
32ad5d1122SVincent Chen #endif /* __ASM_VDSO_PROCESSOR_H */
33