1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef __ASSEMBLY__ 15 16 /* Page Upper Directory not used in RISC-V */ 17 #include <asm-generic/pgtable-nopud.h> 18 #include <asm/page.h> 19 #include <asm/tlbflush.h> 20 #include <linux/mm_types.h> 21 22 #ifdef CONFIG_64BIT 23 #include <asm/pgtable-64.h> 24 #else 25 #include <asm/pgtable-32.h> 26 #endif /* CONFIG_64BIT */ 27 28 #ifdef CONFIG_MMU 29 /* Number of entries in the page global directory */ 30 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 31 /* Number of entries in the page table */ 32 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 33 34 /* Number of PGD entries that a user-mode program can use */ 35 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 36 37 /* Page protection bits */ 38 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 39 40 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) 41 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 42 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 43 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 44 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 45 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 46 _PAGE_EXEC | _PAGE_WRITE) 47 48 #define PAGE_COPY PAGE_READ 49 #define PAGE_COPY_EXEC PAGE_EXEC 50 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 51 #define PAGE_SHARED PAGE_WRITE 52 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 53 54 #define _PAGE_KERNEL (_PAGE_READ \ 55 | _PAGE_WRITE \ 56 | _PAGE_PRESENT \ 57 | _PAGE_ACCESSED \ 58 | _PAGE_DIRTY) 59 60 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 61 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 62 63 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 64 65 /* 66 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't 67 * change the properties of memory regions. 68 */ 69 #define _PAGE_IOREMAP _PAGE_KERNEL 70 71 extern pgd_t swapper_pg_dir[]; 72 73 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 74 #define __P000 PAGE_NONE 75 #define __P001 PAGE_READ 76 #define __P010 PAGE_COPY 77 #define __P011 PAGE_COPY 78 #define __P100 PAGE_EXEC 79 #define __P101 PAGE_READ_EXEC 80 #define __P110 PAGE_COPY_EXEC 81 #define __P111 PAGE_COPY_READ_EXEC 82 83 /* MAP_SHARED permissions: xwr */ 84 #define __S000 PAGE_NONE 85 #define __S001 PAGE_READ 86 #define __S010 PAGE_SHARED 87 #define __S011 PAGE_SHARED 88 #define __S100 PAGE_EXEC 89 #define __S101 PAGE_READ_EXEC 90 #define __S110 PAGE_SHARED_EXEC 91 #define __S111 PAGE_SHARED_EXEC 92 93 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 94 #define VMALLOC_END (PAGE_OFFSET - 1) 95 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 96 97 /* 98 * Roughly size the vmemmap space to be large enough to fit enough 99 * struct pages to map half the virtual address space. Then 100 * position vmemmap directly below the VMALLOC region. 101 */ 102 #define VMEMMAP_SHIFT \ 103 (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 104 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 105 #define VMEMMAP_END (VMALLOC_START - 1) 106 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 107 108 /* 109 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 110 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 111 */ 112 #define vmemmap ((struct page *)VMEMMAP_START) 113 114 static inline int pmd_present(pmd_t pmd) 115 { 116 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 117 } 118 119 static inline int pmd_none(pmd_t pmd) 120 { 121 return (pmd_val(pmd) == 0); 122 } 123 124 static inline int pmd_bad(pmd_t pmd) 125 { 126 return !pmd_present(pmd); 127 } 128 129 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 130 { 131 *pmdp = pmd; 132 } 133 134 static inline void pmd_clear(pmd_t *pmdp) 135 { 136 set_pmd(pmdp, __pmd(0)); 137 } 138 139 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 140 { 141 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 142 } 143 144 static inline unsigned long _pgd_pfn(pgd_t pgd) 145 { 146 return pgd_val(pgd) >> _PAGE_PFN_SHIFT; 147 } 148 149 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 150 151 /* Locate an entry in the page global directory */ 152 static inline pgd_t *pgd_offset(const struct mm_struct *mm, unsigned long addr) 153 { 154 return mm->pgd + pgd_index(addr); 155 } 156 /* Locate an entry in the kernel page global directory */ 157 #define pgd_offset_k(addr) pgd_offset(&init_mm, (addr)) 158 159 static inline struct page *pmd_page(pmd_t pmd) 160 { 161 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 162 } 163 164 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 165 { 166 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 167 } 168 169 /* Yields the page frame number (PFN) of a page table entry */ 170 static inline unsigned long pte_pfn(pte_t pte) 171 { 172 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 173 } 174 175 #define pte_page(x) pfn_to_page(pte_pfn(x)) 176 177 /* Constructs a page table entry */ 178 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 179 { 180 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 181 } 182 183 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 184 185 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 186 187 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long addr) 188 { 189 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(addr); 190 } 191 192 #define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr)) 193 #define pte_unmap(pte) ((void)(pte)) 194 195 static inline int pte_present(pte_t pte) 196 { 197 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 198 } 199 200 static inline int pte_none(pte_t pte) 201 { 202 return (pte_val(pte) == 0); 203 } 204 205 static inline int pte_write(pte_t pte) 206 { 207 return pte_val(pte) & _PAGE_WRITE; 208 } 209 210 static inline int pte_exec(pte_t pte) 211 { 212 return pte_val(pte) & _PAGE_EXEC; 213 } 214 215 static inline int pte_huge(pte_t pte) 216 { 217 return pte_present(pte) 218 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 219 } 220 221 static inline int pte_dirty(pte_t pte) 222 { 223 return pte_val(pte) & _PAGE_DIRTY; 224 } 225 226 static inline int pte_young(pte_t pte) 227 { 228 return pte_val(pte) & _PAGE_ACCESSED; 229 } 230 231 static inline int pte_special(pte_t pte) 232 { 233 return pte_val(pte) & _PAGE_SPECIAL; 234 } 235 236 /* static inline pte_t pte_rdprotect(pte_t pte) */ 237 238 static inline pte_t pte_wrprotect(pte_t pte) 239 { 240 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 241 } 242 243 /* static inline pte_t pte_mkread(pte_t pte) */ 244 245 static inline pte_t pte_mkwrite(pte_t pte) 246 { 247 return __pte(pte_val(pte) | _PAGE_WRITE); 248 } 249 250 /* static inline pte_t pte_mkexec(pte_t pte) */ 251 252 static inline pte_t pte_mkdirty(pte_t pte) 253 { 254 return __pte(pte_val(pte) | _PAGE_DIRTY); 255 } 256 257 static inline pte_t pte_mkclean(pte_t pte) 258 { 259 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 260 } 261 262 static inline pte_t pte_mkyoung(pte_t pte) 263 { 264 return __pte(pte_val(pte) | _PAGE_ACCESSED); 265 } 266 267 static inline pte_t pte_mkold(pte_t pte) 268 { 269 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 270 } 271 272 static inline pte_t pte_mkspecial(pte_t pte) 273 { 274 return __pte(pte_val(pte) | _PAGE_SPECIAL); 275 } 276 277 static inline pte_t pte_mkhuge(pte_t pte) 278 { 279 return pte; 280 } 281 282 /* Modify page protection bits */ 283 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 284 { 285 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 286 } 287 288 #define pgd_ERROR(e) \ 289 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 290 291 292 /* Commit new configuration to MMU hardware */ 293 static inline void update_mmu_cache(struct vm_area_struct *vma, 294 unsigned long address, pte_t *ptep) 295 { 296 /* 297 * The kernel assumes that TLBs don't cache invalid entries, but 298 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 299 * cache flush; it is necessary even after writing invalid entries. 300 * Relying on flush_tlb_fix_spurious_fault would suffice, but 301 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 302 */ 303 local_flush_tlb_page(address); 304 } 305 306 #define __HAVE_ARCH_PTE_SAME 307 static inline int pte_same(pte_t pte_a, pte_t pte_b) 308 { 309 return pte_val(pte_a) == pte_val(pte_b); 310 } 311 312 /* 313 * Certain architectures need to do special things when PTEs within 314 * a page table are directly modified. Thus, the following hook is 315 * made available. 316 */ 317 static inline void set_pte(pte_t *ptep, pte_t pteval) 318 { 319 *ptep = pteval; 320 } 321 322 void flush_icache_pte(pte_t pte); 323 324 static inline void set_pte_at(struct mm_struct *mm, 325 unsigned long addr, pte_t *ptep, pte_t pteval) 326 { 327 if (pte_present(pteval) && pte_exec(pteval)) 328 flush_icache_pte(pteval); 329 330 set_pte(ptep, pteval); 331 } 332 333 static inline void pte_clear(struct mm_struct *mm, 334 unsigned long addr, pte_t *ptep) 335 { 336 set_pte_at(mm, addr, ptep, __pte(0)); 337 } 338 339 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 340 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 341 unsigned long address, pte_t *ptep, 342 pte_t entry, int dirty) 343 { 344 if (!pte_same(*ptep, entry)) 345 set_pte_at(vma->vm_mm, address, ptep, entry); 346 /* 347 * update_mmu_cache will unconditionally execute, handling both 348 * the case that the PTE changed and the spurious fault case. 349 */ 350 return true; 351 } 352 353 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 354 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 355 unsigned long address, pte_t *ptep) 356 { 357 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 358 } 359 360 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 361 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 362 unsigned long address, 363 pte_t *ptep) 364 { 365 if (!pte_young(*ptep)) 366 return 0; 367 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 368 } 369 370 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 371 static inline void ptep_set_wrprotect(struct mm_struct *mm, 372 unsigned long address, pte_t *ptep) 373 { 374 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 375 } 376 377 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 378 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 379 unsigned long address, pte_t *ptep) 380 { 381 /* 382 * This comment is borrowed from x86, but applies equally to RISC-V: 383 * 384 * Clearing the accessed bit without a TLB flush 385 * doesn't cause data corruption. [ It could cause incorrect 386 * page aging and the (mistaken) reclaim of hot pages, but the 387 * chance of that should be relatively low. ] 388 * 389 * So as a performance optimization don't flush the TLB when 390 * clearing the accessed bit, it will eventually be flushed by 391 * a context switch or a VM operation anyway. [ In the rare 392 * event of it not getting flushed for a long time the delay 393 * shouldn't really matter because there's no real memory 394 * pressure for swapout to react to. ] 395 */ 396 return ptep_test_and_clear_young(vma, address, ptep); 397 } 398 399 /* 400 * Encode and decode a swap entry 401 * 402 * Format of swap PTE: 403 * bit 0: _PAGE_PRESENT (zero) 404 * bit 1: _PAGE_PROT_NONE (zero) 405 * bits 2 to 6: swap type 406 * bits 7 to XLEN-1: swap offset 407 */ 408 #define __SWP_TYPE_SHIFT 2 409 #define __SWP_TYPE_BITS 5 410 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 411 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 412 413 #define MAX_SWAPFILES_CHECK() \ 414 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 415 416 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 417 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 418 #define __swp_entry(type, offset) ((swp_entry_t) \ 419 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 420 421 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 422 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 423 424 #define PCI_IO_SIZE SZ_16M 425 #define PCI_IO_END VMEMMAP_START 426 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 427 428 #define FIXADDR_TOP PCI_IO_START 429 #ifdef CONFIG_64BIT 430 #define FIXADDR_SIZE PMD_SIZE 431 #else 432 #define FIXADDR_SIZE PGDIR_SIZE 433 #endif 434 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 435 436 /* 437 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 438 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 439 */ 440 #ifdef CONFIG_64BIT 441 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 442 #else 443 #define TASK_SIZE FIXADDR_START 444 #endif 445 446 #else /* CONFIG_MMU */ 447 448 #define PAGE_KERNEL __pgprot(0) 449 #define swapper_pg_dir NULL 450 #define VMALLOC_START 0 451 452 #define TASK_SIZE 0xffffffffUL 453 454 #endif /* !CONFIG_MMU */ 455 456 #define kern_addr_valid(addr) (1) /* FIXME */ 457 458 extern void *dtb_early_va; 459 void setup_bootmem(void); 460 void paging_init(void); 461 462 #define FIRST_USER_ADDRESS 0 463 464 /* 465 * ZERO_PAGE is a global shared page that is always zero, 466 * used for zero-mapped memory areas, etc. 467 */ 468 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 469 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 470 471 #include <asm-generic/pgtable.h> 472 473 #endif /* !__ASSEMBLY__ */ 474 475 #endif /* _ASM_RISCV_PGTABLE_H */ 476