1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #define KERNEL_LINK_ADDR PAGE_OFFSET 16 #define KERN_VIRT_SIZE (UL(-1)) 17 #else 18 19 #define ADDRESS_SPACE_END (UL(-1)) 20 21 #ifdef CONFIG_64BIT 22 /* Leave 2GB for kernel and BPF at the end of the address space */ 23 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 24 #else 25 #define KERNEL_LINK_ADDR PAGE_OFFSET 26 #endif 27 28 /* Number of entries in the page global directory */ 29 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 30 /* Number of entries in the page table */ 31 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 32 33 /* 34 * Half of the kernel address space (half of the entries of the page global 35 * directory) is for the direct mapping. 36 */ 37 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 38 39 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 40 #define VMALLOC_END PAGE_OFFSET 41 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 42 43 #define BPF_JIT_REGION_SIZE (SZ_128M) 44 #ifdef CONFIG_64BIT 45 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 46 #define BPF_JIT_REGION_END (MODULES_END) 47 #else 48 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 49 #define BPF_JIT_REGION_END (VMALLOC_END) 50 #endif 51 52 /* Modules always live before the kernel */ 53 #ifdef CONFIG_64BIT 54 /* This is used to define the end of the KASAN shadow region */ 55 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 56 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 57 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 58 #endif 59 60 /* 61 * Roughly size the vmemmap space to be large enough to fit enough 62 * struct pages to map half the virtual address space. Then 63 * position vmemmap directly below the VMALLOC region. 64 */ 65 #ifdef CONFIG_64BIT 66 #define VA_BITS (pgtable_l4_enabled ? 48 : 39) 67 #else 68 #define VA_BITS 32 69 #endif 70 71 #define VMEMMAP_SHIFT \ 72 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 73 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 74 #define VMEMMAP_END VMALLOC_START 75 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 76 77 /* 78 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 79 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 80 */ 81 #define vmemmap ((struct page *)VMEMMAP_START) 82 83 #define PCI_IO_SIZE SZ_16M 84 #define PCI_IO_END VMEMMAP_START 85 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 86 87 #define FIXADDR_TOP PCI_IO_START 88 #ifdef CONFIG_64BIT 89 #define FIXADDR_SIZE PMD_SIZE 90 #else 91 #define FIXADDR_SIZE PGDIR_SIZE 92 #endif 93 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 94 95 #endif 96 97 #ifdef CONFIG_XIP_KERNEL 98 #define XIP_OFFSET SZ_32M 99 #define XIP_OFFSET_MASK (SZ_32M - 1) 100 #else 101 #define XIP_OFFSET 0 102 #endif 103 104 #ifndef __ASSEMBLY__ 105 106 #include <asm-generic/pgtable-nop4d.h> 107 #include <asm/page.h> 108 #include <asm/tlbflush.h> 109 #include <linux/mm_types.h> 110 111 #ifdef CONFIG_64BIT 112 #include <asm/pgtable-64.h> 113 #else 114 #include <asm/pgtable-32.h> 115 #endif /* CONFIG_64BIT */ 116 117 #ifdef CONFIG_XIP_KERNEL 118 #define XIP_FIXUP(addr) ({ \ 119 uintptr_t __a = (uintptr_t)(addr); \ 120 (__a >= CONFIG_XIP_PHYS_ADDR && \ 121 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ? \ 122 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ 123 __a; \ 124 }) 125 #else 126 #define XIP_FIXUP(addr) (addr) 127 #endif /* CONFIG_XIP_KERNEL */ 128 129 struct pt_alloc_ops { 130 pte_t *(*get_pte_virt)(phys_addr_t pa); 131 phys_addr_t (*alloc_pte)(uintptr_t va); 132 #ifndef __PAGETABLE_PMD_FOLDED 133 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 134 phys_addr_t (*alloc_pmd)(uintptr_t va); 135 pud_t *(*get_pud_virt)(phys_addr_t pa); 136 phys_addr_t (*alloc_pud)(uintptr_t va); 137 #endif 138 }; 139 140 extern struct pt_alloc_ops pt_ops __initdata; 141 142 #ifdef CONFIG_MMU 143 /* Number of PGD entries that a user-mode program can use */ 144 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 145 146 /* Page protection bits */ 147 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 148 149 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 150 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 151 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 152 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 153 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 155 _PAGE_EXEC | _PAGE_WRITE) 156 157 #define PAGE_COPY PAGE_READ 158 #define PAGE_COPY_EXEC PAGE_EXEC 159 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 160 #define PAGE_SHARED PAGE_WRITE 161 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 162 163 #define _PAGE_KERNEL (_PAGE_READ \ 164 | _PAGE_WRITE \ 165 | _PAGE_PRESENT \ 166 | _PAGE_ACCESSED \ 167 | _PAGE_DIRTY \ 168 | _PAGE_GLOBAL) 169 170 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 171 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 172 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 173 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 174 | _PAGE_EXEC) 175 176 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 177 178 /* 179 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't 180 * change the properties of memory regions. 181 */ 182 #define _PAGE_IOREMAP _PAGE_KERNEL 183 184 extern pgd_t swapper_pg_dir[]; 185 186 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 187 #define __P000 PAGE_NONE 188 #define __P001 PAGE_READ 189 #define __P010 PAGE_COPY 190 #define __P011 PAGE_COPY 191 #define __P100 PAGE_EXEC 192 #define __P101 PAGE_READ_EXEC 193 #define __P110 PAGE_COPY_EXEC 194 #define __P111 PAGE_COPY_READ_EXEC 195 196 /* MAP_SHARED permissions: xwr */ 197 #define __S000 PAGE_NONE 198 #define __S001 PAGE_READ 199 #define __S010 PAGE_SHARED 200 #define __S011 PAGE_SHARED 201 #define __S100 PAGE_EXEC 202 #define __S101 PAGE_READ_EXEC 203 #define __S110 PAGE_SHARED_EXEC 204 #define __S111 PAGE_SHARED_EXEC 205 206 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 207 static inline int pmd_present(pmd_t pmd) 208 { 209 /* 210 * Checking for _PAGE_LEAF is needed too because: 211 * When splitting a THP, split_huge_page() will temporarily clear 212 * the present bit, in this situation, pmd_present() and 213 * pmd_trans_huge() still needs to return true. 214 */ 215 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 216 } 217 #else 218 static inline int pmd_present(pmd_t pmd) 219 { 220 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 221 } 222 #endif 223 224 static inline int pmd_none(pmd_t pmd) 225 { 226 return (pmd_val(pmd) == 0); 227 } 228 229 static inline int pmd_bad(pmd_t pmd) 230 { 231 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 232 } 233 234 #define pmd_leaf pmd_leaf 235 static inline int pmd_leaf(pmd_t pmd) 236 { 237 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 238 } 239 240 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 241 { 242 *pmdp = pmd; 243 } 244 245 static inline void pmd_clear(pmd_t *pmdp) 246 { 247 set_pmd(pmdp, __pmd(0)); 248 } 249 250 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 251 { 252 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 253 } 254 255 static inline unsigned long _pgd_pfn(pgd_t pgd) 256 { 257 return pgd_val(pgd) >> _PAGE_PFN_SHIFT; 258 } 259 260 static inline struct page *pmd_page(pmd_t pmd) 261 { 262 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 263 } 264 265 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 266 { 267 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 268 } 269 270 static inline pte_t pmd_pte(pmd_t pmd) 271 { 272 return __pte(pmd_val(pmd)); 273 } 274 275 static inline pte_t pud_pte(pud_t pud) 276 { 277 return __pte(pud_val(pud)); 278 } 279 280 /* Yields the page frame number (PFN) of a page table entry */ 281 static inline unsigned long pte_pfn(pte_t pte) 282 { 283 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 284 } 285 286 #define pte_page(x) pfn_to_page(pte_pfn(x)) 287 288 /* Constructs a page table entry */ 289 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 290 { 291 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 292 } 293 294 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 295 296 static inline int pte_present(pte_t pte) 297 { 298 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 299 } 300 301 static inline int pte_none(pte_t pte) 302 { 303 return (pte_val(pte) == 0); 304 } 305 306 static inline int pte_write(pte_t pte) 307 { 308 return pte_val(pte) & _PAGE_WRITE; 309 } 310 311 static inline int pte_exec(pte_t pte) 312 { 313 return pte_val(pte) & _PAGE_EXEC; 314 } 315 316 static inline int pte_huge(pte_t pte) 317 { 318 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 319 } 320 321 static inline int pte_dirty(pte_t pte) 322 { 323 return pte_val(pte) & _PAGE_DIRTY; 324 } 325 326 static inline int pte_young(pte_t pte) 327 { 328 return pte_val(pte) & _PAGE_ACCESSED; 329 } 330 331 static inline int pte_special(pte_t pte) 332 { 333 return pte_val(pte) & _PAGE_SPECIAL; 334 } 335 336 /* static inline pte_t pte_rdprotect(pte_t pte) */ 337 338 static inline pte_t pte_wrprotect(pte_t pte) 339 { 340 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 341 } 342 343 /* static inline pte_t pte_mkread(pte_t pte) */ 344 345 static inline pte_t pte_mkwrite(pte_t pte) 346 { 347 return __pte(pte_val(pte) | _PAGE_WRITE); 348 } 349 350 /* static inline pte_t pte_mkexec(pte_t pte) */ 351 352 static inline pte_t pte_mkdirty(pte_t pte) 353 { 354 return __pte(pte_val(pte) | _PAGE_DIRTY); 355 } 356 357 static inline pte_t pte_mkclean(pte_t pte) 358 { 359 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 360 } 361 362 static inline pte_t pte_mkyoung(pte_t pte) 363 { 364 return __pte(pte_val(pte) | _PAGE_ACCESSED); 365 } 366 367 static inline pte_t pte_mkold(pte_t pte) 368 { 369 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 370 } 371 372 static inline pte_t pte_mkspecial(pte_t pte) 373 { 374 return __pte(pte_val(pte) | _PAGE_SPECIAL); 375 } 376 377 static inline pte_t pte_mkhuge(pte_t pte) 378 { 379 return pte; 380 } 381 382 #ifdef CONFIG_NUMA_BALANCING 383 /* 384 * See the comment in include/asm-generic/pgtable.h 385 */ 386 static inline int pte_protnone(pte_t pte) 387 { 388 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 389 } 390 391 static inline int pmd_protnone(pmd_t pmd) 392 { 393 return pte_protnone(pmd_pte(pmd)); 394 } 395 #endif 396 397 /* Modify page protection bits */ 398 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 399 { 400 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 401 } 402 403 #define pgd_ERROR(e) \ 404 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 405 406 407 /* Commit new configuration to MMU hardware */ 408 static inline void update_mmu_cache(struct vm_area_struct *vma, 409 unsigned long address, pte_t *ptep) 410 { 411 /* 412 * The kernel assumes that TLBs don't cache invalid entries, but 413 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 414 * cache flush; it is necessary even after writing invalid entries. 415 * Relying on flush_tlb_fix_spurious_fault would suffice, but 416 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 417 */ 418 local_flush_tlb_page(address); 419 } 420 421 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 422 unsigned long address, pmd_t *pmdp) 423 { 424 pte_t *ptep = (pte_t *)pmdp; 425 426 update_mmu_cache(vma, address, ptep); 427 } 428 429 #define __HAVE_ARCH_PTE_SAME 430 static inline int pte_same(pte_t pte_a, pte_t pte_b) 431 { 432 return pte_val(pte_a) == pte_val(pte_b); 433 } 434 435 /* 436 * Certain architectures need to do special things when PTEs within 437 * a page table are directly modified. Thus, the following hook is 438 * made available. 439 */ 440 static inline void set_pte(pte_t *ptep, pte_t pteval) 441 { 442 *ptep = pteval; 443 } 444 445 void flush_icache_pte(pte_t pte); 446 447 static inline void set_pte_at(struct mm_struct *mm, 448 unsigned long addr, pte_t *ptep, pte_t pteval) 449 { 450 if (pte_present(pteval) && pte_exec(pteval)) 451 flush_icache_pte(pteval); 452 453 set_pte(ptep, pteval); 454 } 455 456 static inline void pte_clear(struct mm_struct *mm, 457 unsigned long addr, pte_t *ptep) 458 { 459 set_pte_at(mm, addr, ptep, __pte(0)); 460 } 461 462 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 463 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 464 unsigned long address, pte_t *ptep, 465 pte_t entry, int dirty) 466 { 467 if (!pte_same(*ptep, entry)) 468 set_pte_at(vma->vm_mm, address, ptep, entry); 469 /* 470 * update_mmu_cache will unconditionally execute, handling both 471 * the case that the PTE changed and the spurious fault case. 472 */ 473 return true; 474 } 475 476 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 477 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 478 unsigned long address, pte_t *ptep) 479 { 480 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 481 } 482 483 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 484 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 485 unsigned long address, 486 pte_t *ptep) 487 { 488 if (!pte_young(*ptep)) 489 return 0; 490 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 491 } 492 493 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 494 static inline void ptep_set_wrprotect(struct mm_struct *mm, 495 unsigned long address, pte_t *ptep) 496 { 497 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 498 } 499 500 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 501 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 502 unsigned long address, pte_t *ptep) 503 { 504 /* 505 * This comment is borrowed from x86, but applies equally to RISC-V: 506 * 507 * Clearing the accessed bit without a TLB flush 508 * doesn't cause data corruption. [ It could cause incorrect 509 * page aging and the (mistaken) reclaim of hot pages, but the 510 * chance of that should be relatively low. ] 511 * 512 * So as a performance optimization don't flush the TLB when 513 * clearing the accessed bit, it will eventually be flushed by 514 * a context switch or a VM operation anyway. [ In the rare 515 * event of it not getting flushed for a long time the delay 516 * shouldn't really matter because there's no real memory 517 * pressure for swapout to react to. ] 518 */ 519 return ptep_test_and_clear_young(vma, address, ptep); 520 } 521 522 /* 523 * THP functions 524 */ 525 static inline pmd_t pte_pmd(pte_t pte) 526 { 527 return __pmd(pte_val(pte)); 528 } 529 530 static inline pmd_t pmd_mkhuge(pmd_t pmd) 531 { 532 return pmd; 533 } 534 535 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 536 { 537 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 538 } 539 540 #define __pmd_to_phys(pmd) (pmd_val(pmd) >> _PAGE_PFN_SHIFT << PAGE_SHIFT) 541 542 static inline unsigned long pmd_pfn(pmd_t pmd) 543 { 544 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 545 } 546 547 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 548 { 549 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 550 } 551 552 #define pmd_write pmd_write 553 static inline int pmd_write(pmd_t pmd) 554 { 555 return pte_write(pmd_pte(pmd)); 556 } 557 558 static inline int pmd_dirty(pmd_t pmd) 559 { 560 return pte_dirty(pmd_pte(pmd)); 561 } 562 563 static inline int pmd_young(pmd_t pmd) 564 { 565 return pte_young(pmd_pte(pmd)); 566 } 567 568 static inline pmd_t pmd_mkold(pmd_t pmd) 569 { 570 return pte_pmd(pte_mkold(pmd_pte(pmd))); 571 } 572 573 static inline pmd_t pmd_mkyoung(pmd_t pmd) 574 { 575 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 576 } 577 578 static inline pmd_t pmd_mkwrite(pmd_t pmd) 579 { 580 return pte_pmd(pte_mkwrite(pmd_pte(pmd))); 581 } 582 583 static inline pmd_t pmd_wrprotect(pmd_t pmd) 584 { 585 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 586 } 587 588 static inline pmd_t pmd_mkclean(pmd_t pmd) 589 { 590 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 591 } 592 593 static inline pmd_t pmd_mkdirty(pmd_t pmd) 594 { 595 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 596 } 597 598 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 599 pmd_t *pmdp, pmd_t pmd) 600 { 601 return set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); 602 } 603 604 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 605 pud_t *pudp, pud_t pud) 606 { 607 return set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); 608 } 609 610 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 611 static inline int pmd_trans_huge(pmd_t pmd) 612 { 613 return pmd_leaf(pmd); 614 } 615 616 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 617 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 618 unsigned long address, pmd_t *pmdp, 619 pmd_t entry, int dirty) 620 { 621 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 622 } 623 624 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 625 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 626 unsigned long address, pmd_t *pmdp) 627 { 628 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 629 } 630 631 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 632 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 633 unsigned long address, pmd_t *pmdp) 634 { 635 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 636 } 637 638 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 639 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 640 unsigned long address, pmd_t *pmdp) 641 { 642 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 643 } 644 645 #define pmdp_establish pmdp_establish 646 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 647 unsigned long address, pmd_t *pmdp, pmd_t pmd) 648 { 649 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 650 } 651 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 652 653 /* 654 * Encode and decode a swap entry 655 * 656 * Format of swap PTE: 657 * bit 0: _PAGE_PRESENT (zero) 658 * bit 1 to 3: _PAGE_LEAF (zero) 659 * bit 5: _PAGE_PROT_NONE (zero) 660 * bits 6 to 10: swap type 661 * bits 10 to XLEN-1: swap offset 662 */ 663 #define __SWP_TYPE_SHIFT 6 664 #define __SWP_TYPE_BITS 5 665 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 666 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 667 668 #define MAX_SWAPFILES_CHECK() \ 669 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 670 671 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 672 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 673 #define __swp_entry(type, offset) ((swp_entry_t) \ 674 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 675 676 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 677 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 678 679 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 680 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 681 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 682 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 683 684 /* 685 * In the RV64 Linux scheme, we give the user half of the virtual-address space 686 * and give the kernel the other (upper) half. 687 */ 688 #ifdef CONFIG_64BIT 689 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 690 #else 691 #define KERN_VIRT_START FIXADDR_START 692 #endif 693 694 /* 695 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 696 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 697 * Task size is: 698 * - 0x9fc00000 (~2.5GB) for RV32. 699 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 700 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 701 * 702 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 703 * Instruction Set Manual Volume II: Privileged Architecture" states that 704 * "load and store effective addresses, which are 64bits, must have bits 705 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 706 */ 707 #ifdef CONFIG_64BIT 708 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 709 #define TASK_SIZE_MIN (PGDIR_SIZE_L3 * PTRS_PER_PGD / 2) 710 #else 711 #define TASK_SIZE FIXADDR_START 712 #define TASK_SIZE_MIN TASK_SIZE 713 #endif 714 715 #else /* CONFIG_MMU */ 716 717 #define PAGE_SHARED __pgprot(0) 718 #define PAGE_KERNEL __pgprot(0) 719 #define swapper_pg_dir NULL 720 #define TASK_SIZE 0xffffffffUL 721 #define VMALLOC_START 0 722 #define VMALLOC_END TASK_SIZE 723 724 #endif /* !CONFIG_MMU */ 725 726 #define kern_addr_valid(addr) (1) /* FIXME */ 727 728 extern char _start[]; 729 extern void *_dtb_early_va; 730 extern uintptr_t _dtb_early_pa; 731 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 732 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 733 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 734 #else 735 #define dtb_early_va _dtb_early_va 736 #define dtb_early_pa _dtb_early_pa 737 #endif /* CONFIG_XIP_KERNEL */ 738 extern u64 satp_mode; 739 extern bool pgtable_l4_enabled; 740 741 void paging_init(void); 742 void misc_mem_init(void); 743 744 /* 745 * ZERO_PAGE is a global shared page that is always zero, 746 * used for zero-mapped memory areas, etc. 747 */ 748 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 749 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 750 751 #endif /* !__ASSEMBLY__ */ 752 753 #endif /* _ASM_RISCV_PGTABLE_H */ 754