1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 11 #include <asm/pgtable-bits.h> 12 13 #ifndef __ASSEMBLY__ 14 15 /* Page Upper Directory not used in RISC-V */ 16 #include <asm-generic/pgtable-nopud.h> 17 #include <asm/page.h> 18 #include <asm/tlbflush.h> 19 #include <linux/mm_types.h> 20 21 #ifdef CONFIG_64BIT 22 #include <asm/pgtable-64.h> 23 #else 24 #include <asm/pgtable-32.h> 25 #endif /* CONFIG_64BIT */ 26 27 /* Number of entries in the page global directory */ 28 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 29 /* Number of entries in the page table */ 30 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 31 32 /* Number of PGD entries that a user-mode program can use */ 33 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 34 #define FIRST_USER_ADDRESS 0 35 36 /* Page protection bits */ 37 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 38 39 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) 40 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 41 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 42 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 43 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 44 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 45 _PAGE_EXEC | _PAGE_WRITE) 46 47 #define PAGE_COPY PAGE_READ 48 #define PAGE_COPY_EXEC PAGE_EXEC 49 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 50 #define PAGE_SHARED PAGE_WRITE 51 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 52 53 #define _PAGE_KERNEL (_PAGE_READ \ 54 | _PAGE_WRITE \ 55 | _PAGE_PRESENT \ 56 | _PAGE_ACCESSED \ 57 | _PAGE_DIRTY) 58 59 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 60 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 61 62 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 63 64 extern pgd_t swapper_pg_dir[]; 65 66 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 67 #define __P000 PAGE_NONE 68 #define __P001 PAGE_READ 69 #define __P010 PAGE_COPY 70 #define __P011 PAGE_COPY 71 #define __P100 PAGE_EXEC 72 #define __P101 PAGE_READ_EXEC 73 #define __P110 PAGE_COPY_EXEC 74 #define __P111 PAGE_COPY_READ_EXEC 75 76 /* MAP_SHARED permissions: xwr */ 77 #define __S000 PAGE_NONE 78 #define __S001 PAGE_READ 79 #define __S010 PAGE_SHARED 80 #define __S011 PAGE_SHARED 81 #define __S100 PAGE_EXEC 82 #define __S101 PAGE_READ_EXEC 83 #define __S110 PAGE_SHARED_EXEC 84 #define __S111 PAGE_SHARED_EXEC 85 86 /* 87 * ZERO_PAGE is a global shared page that is always zero, 88 * used for zero-mapped memory areas, etc. 89 */ 90 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 91 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 92 93 static inline int pmd_present(pmd_t pmd) 94 { 95 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 96 } 97 98 static inline int pmd_none(pmd_t pmd) 99 { 100 return (pmd_val(pmd) == 0); 101 } 102 103 static inline int pmd_bad(pmd_t pmd) 104 { 105 return !pmd_present(pmd); 106 } 107 108 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 109 { 110 *pmdp = pmd; 111 } 112 113 static inline void pmd_clear(pmd_t *pmdp) 114 { 115 set_pmd(pmdp, __pmd(0)); 116 } 117 118 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 119 { 120 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 121 } 122 123 static inline unsigned long _pgd_pfn(pgd_t pgd) 124 { 125 return pgd_val(pgd) >> _PAGE_PFN_SHIFT; 126 } 127 128 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 129 130 /* Locate an entry in the page global directory */ 131 static inline pgd_t *pgd_offset(const struct mm_struct *mm, unsigned long addr) 132 { 133 return mm->pgd + pgd_index(addr); 134 } 135 /* Locate an entry in the kernel page global directory */ 136 #define pgd_offset_k(addr) pgd_offset(&init_mm, (addr)) 137 138 static inline struct page *pmd_page(pmd_t pmd) 139 { 140 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 141 } 142 143 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 144 { 145 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 146 } 147 148 /* Yields the page frame number (PFN) of a page table entry */ 149 static inline unsigned long pte_pfn(pte_t pte) 150 { 151 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 152 } 153 154 #define pte_page(x) pfn_to_page(pte_pfn(x)) 155 156 /* Constructs a page table entry */ 157 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 158 { 159 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 160 } 161 162 static inline pte_t mk_pte(struct page *page, pgprot_t prot) 163 { 164 return pfn_pte(page_to_pfn(page), prot); 165 } 166 167 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 168 169 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long addr) 170 { 171 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(addr); 172 } 173 174 #define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr)) 175 #define pte_unmap(pte) ((void)(pte)) 176 177 static inline int pte_present(pte_t pte) 178 { 179 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 180 } 181 182 static inline int pte_none(pte_t pte) 183 { 184 return (pte_val(pte) == 0); 185 } 186 187 static inline int pte_write(pte_t pte) 188 { 189 return pte_val(pte) & _PAGE_WRITE; 190 } 191 192 static inline int pte_exec(pte_t pte) 193 { 194 return pte_val(pte) & _PAGE_EXEC; 195 } 196 197 static inline int pte_huge(pte_t pte) 198 { 199 return pte_present(pte) 200 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 201 } 202 203 static inline int pte_dirty(pte_t pte) 204 { 205 return pte_val(pte) & _PAGE_DIRTY; 206 } 207 208 static inline int pte_young(pte_t pte) 209 { 210 return pte_val(pte) & _PAGE_ACCESSED; 211 } 212 213 static inline int pte_special(pte_t pte) 214 { 215 return pte_val(pte) & _PAGE_SPECIAL; 216 } 217 218 /* static inline pte_t pte_rdprotect(pte_t pte) */ 219 220 static inline pte_t pte_wrprotect(pte_t pte) 221 { 222 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 223 } 224 225 /* static inline pte_t pte_mkread(pte_t pte) */ 226 227 static inline pte_t pte_mkwrite(pte_t pte) 228 { 229 return __pte(pte_val(pte) | _PAGE_WRITE); 230 } 231 232 /* static inline pte_t pte_mkexec(pte_t pte) */ 233 234 static inline pte_t pte_mkdirty(pte_t pte) 235 { 236 return __pte(pte_val(pte) | _PAGE_DIRTY); 237 } 238 239 static inline pte_t pte_mkclean(pte_t pte) 240 { 241 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 242 } 243 244 static inline pte_t pte_mkyoung(pte_t pte) 245 { 246 return __pte(pte_val(pte) | _PAGE_ACCESSED); 247 } 248 249 static inline pte_t pte_mkold(pte_t pte) 250 { 251 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 252 } 253 254 static inline pte_t pte_mkspecial(pte_t pte) 255 { 256 return __pte(pte_val(pte) | _PAGE_SPECIAL); 257 } 258 259 static inline pte_t pte_mkhuge(pte_t pte) 260 { 261 return pte; 262 } 263 264 /* Modify page protection bits */ 265 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 266 { 267 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 268 } 269 270 #define pgd_ERROR(e) \ 271 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 272 273 274 /* Commit new configuration to MMU hardware */ 275 static inline void update_mmu_cache(struct vm_area_struct *vma, 276 unsigned long address, pte_t *ptep) 277 { 278 /* 279 * The kernel assumes that TLBs don't cache invalid entries, but 280 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 281 * cache flush; it is necessary even after writing invalid entries. 282 * Relying on flush_tlb_fix_spurious_fault would suffice, but 283 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 284 */ 285 local_flush_tlb_page(address); 286 } 287 288 #define __HAVE_ARCH_PTE_SAME 289 static inline int pte_same(pte_t pte_a, pte_t pte_b) 290 { 291 return pte_val(pte_a) == pte_val(pte_b); 292 } 293 294 /* 295 * Certain architectures need to do special things when PTEs within 296 * a page table are directly modified. Thus, the following hook is 297 * made available. 298 */ 299 static inline void set_pte(pte_t *ptep, pte_t pteval) 300 { 301 *ptep = pteval; 302 } 303 304 void flush_icache_pte(pte_t pte); 305 306 static inline void set_pte_at(struct mm_struct *mm, 307 unsigned long addr, pte_t *ptep, pte_t pteval) 308 { 309 if (pte_present(pteval) && pte_exec(pteval)) 310 flush_icache_pte(pteval); 311 312 set_pte(ptep, pteval); 313 } 314 315 static inline void pte_clear(struct mm_struct *mm, 316 unsigned long addr, pte_t *ptep) 317 { 318 set_pte_at(mm, addr, ptep, __pte(0)); 319 } 320 321 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 322 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 323 unsigned long address, pte_t *ptep, 324 pte_t entry, int dirty) 325 { 326 if (!pte_same(*ptep, entry)) 327 set_pte_at(vma->vm_mm, address, ptep, entry); 328 /* 329 * update_mmu_cache will unconditionally execute, handling both 330 * the case that the PTE changed and the spurious fault case. 331 */ 332 return true; 333 } 334 335 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 336 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 337 unsigned long address, pte_t *ptep) 338 { 339 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 340 } 341 342 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 343 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 344 unsigned long address, 345 pte_t *ptep) 346 { 347 if (!pte_young(*ptep)) 348 return 0; 349 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 350 } 351 352 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 353 static inline void ptep_set_wrprotect(struct mm_struct *mm, 354 unsigned long address, pte_t *ptep) 355 { 356 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 357 } 358 359 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 360 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 361 unsigned long address, pte_t *ptep) 362 { 363 /* 364 * This comment is borrowed from x86, but applies equally to RISC-V: 365 * 366 * Clearing the accessed bit without a TLB flush 367 * doesn't cause data corruption. [ It could cause incorrect 368 * page aging and the (mistaken) reclaim of hot pages, but the 369 * chance of that should be relatively low. ] 370 * 371 * So as a performance optimization don't flush the TLB when 372 * clearing the accessed bit, it will eventually be flushed by 373 * a context switch or a VM operation anyway. [ In the rare 374 * event of it not getting flushed for a long time the delay 375 * shouldn't really matter because there's no real memory 376 * pressure for swapout to react to. ] 377 */ 378 return ptep_test_and_clear_young(vma, address, ptep); 379 } 380 381 /* 382 * Encode and decode a swap entry 383 * 384 * Format of swap PTE: 385 * bit 0: _PAGE_PRESENT (zero) 386 * bit 1: _PAGE_PROT_NONE (zero) 387 * bits 2 to 6: swap type 388 * bits 7 to XLEN-1: swap offset 389 */ 390 #define __SWP_TYPE_SHIFT 2 391 #define __SWP_TYPE_BITS 5 392 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 393 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 394 395 #define MAX_SWAPFILES_CHECK() \ 396 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 397 398 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 399 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 400 #define __swp_entry(type, offset) ((swp_entry_t) \ 401 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 402 403 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 404 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 405 406 #ifdef CONFIG_FLATMEM 407 #define kern_addr_valid(addr) (1) /* FIXME */ 408 #endif 409 410 extern void *dtb_early_va; 411 extern void setup_bootmem(void); 412 extern void paging_init(void); 413 414 static inline void pgtable_cache_init(void) 415 { 416 /* No page table caches to initialize */ 417 } 418 419 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 420 #define VMALLOC_END (PAGE_OFFSET - 1) 421 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 422 423 /* 424 * Task size is 0x4000000000 for RV64 or 0xb800000 for RV32. 425 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 426 */ 427 #ifdef CONFIG_64BIT 428 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 429 #else 430 #define TASK_SIZE VMALLOC_START 431 #endif 432 433 #include <asm-generic/pgtable.h> 434 435 #endif /* !__ASSEMBLY__ */ 436 437 #endif /* _ASM_RISCV_PGTABLE_H */ 438