1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #define KERNEL_LINK_ADDR PAGE_OFFSET 16 #define KERN_VIRT_SIZE (UL(-1)) 17 #else 18 19 #define ADDRESS_SPACE_END (UL(-1)) 20 21 #ifdef CONFIG_64BIT 22 /* Leave 2GB for kernel and BPF at the end of the address space */ 23 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 24 #else 25 #define KERNEL_LINK_ADDR PAGE_OFFSET 26 #endif 27 28 /* Number of entries in the page global directory */ 29 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 30 /* Number of entries in the page table */ 31 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 32 33 /* 34 * Half of the kernel address space (1/4 of the entries of the page global 35 * directory) is for the direct mapping. 36 */ 37 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 38 39 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 40 #define VMALLOC_END PAGE_OFFSET 41 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 42 43 #define BPF_JIT_REGION_SIZE (SZ_128M) 44 #ifdef CONFIG_64BIT 45 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 46 #define BPF_JIT_REGION_END (MODULES_END) 47 #else 48 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 49 #define BPF_JIT_REGION_END (VMALLOC_END) 50 #endif 51 52 /* Modules always live before the kernel */ 53 #ifdef CONFIG_64BIT 54 /* This is used to define the end of the KASAN shadow region */ 55 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 56 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 57 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 58 #endif 59 60 /* 61 * Roughly size the vmemmap space to be large enough to fit enough 62 * struct pages to map half the virtual address space. Then 63 * position vmemmap directly below the VMALLOC region. 64 */ 65 #ifdef CONFIG_64BIT 66 #define VA_BITS (pgtable_l5_enabled ? \ 67 57 : (pgtable_l4_enabled ? 48 : 39)) 68 #else 69 #define VA_BITS 32 70 #endif 71 72 #define VMEMMAP_SHIFT \ 73 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 74 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 75 #define VMEMMAP_END VMALLOC_START 76 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 77 78 /* 79 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 80 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 81 */ 82 #define vmemmap ((struct page *)VMEMMAP_START) 83 84 #define PCI_IO_SIZE SZ_16M 85 #define PCI_IO_END VMEMMAP_START 86 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 87 88 #define FIXADDR_TOP PCI_IO_START 89 #ifdef CONFIG_64BIT 90 #define MAX_FDT_SIZE PMD_SIZE 91 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 92 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 93 #else 94 #define MAX_FDT_SIZE PGDIR_SIZE 95 #define FIX_FDT_SIZE MAX_FDT_SIZE 96 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 97 #endif 98 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 99 100 #endif 101 102 #ifdef CONFIG_XIP_KERNEL 103 #define XIP_OFFSET SZ_32M 104 #define XIP_OFFSET_MASK (SZ_32M - 1) 105 #else 106 #define XIP_OFFSET 0 107 #endif 108 109 #ifndef __ASSEMBLY__ 110 111 #include <asm/page.h> 112 #include <asm/tlbflush.h> 113 #include <linux/mm_types.h> 114 115 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 116 117 #ifdef CONFIG_64BIT 118 #include <asm/pgtable-64.h> 119 #else 120 #include <asm/pgtable-32.h> 121 #endif /* CONFIG_64BIT */ 122 123 #include <linux/page_table_check.h> 124 125 #ifdef CONFIG_XIP_KERNEL 126 #define XIP_FIXUP(addr) ({ \ 127 uintptr_t __a = (uintptr_t)(addr); \ 128 (__a >= CONFIG_XIP_PHYS_ADDR && \ 129 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ? \ 130 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ 131 __a; \ 132 }) 133 #else 134 #define XIP_FIXUP(addr) (addr) 135 #endif /* CONFIG_XIP_KERNEL */ 136 137 struct pt_alloc_ops { 138 pte_t *(*get_pte_virt)(phys_addr_t pa); 139 phys_addr_t (*alloc_pte)(uintptr_t va); 140 #ifndef __PAGETABLE_PMD_FOLDED 141 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 142 phys_addr_t (*alloc_pmd)(uintptr_t va); 143 pud_t *(*get_pud_virt)(phys_addr_t pa); 144 phys_addr_t (*alloc_pud)(uintptr_t va); 145 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 146 phys_addr_t (*alloc_p4d)(uintptr_t va); 147 #endif 148 }; 149 150 extern struct pt_alloc_ops pt_ops __initdata; 151 152 #ifdef CONFIG_MMU 153 /* Number of PGD entries that a user-mode program can use */ 154 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 155 156 /* Page protection bits */ 157 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 158 159 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 160 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 161 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 162 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 163 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 164 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 165 _PAGE_EXEC | _PAGE_WRITE) 166 167 #define PAGE_COPY PAGE_READ 168 #define PAGE_COPY_EXEC PAGE_READ_EXEC 169 #define PAGE_SHARED PAGE_WRITE 170 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 171 172 #define _PAGE_KERNEL (_PAGE_READ \ 173 | _PAGE_WRITE \ 174 | _PAGE_PRESENT \ 175 | _PAGE_ACCESSED \ 176 | _PAGE_DIRTY \ 177 | _PAGE_GLOBAL) 178 179 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 180 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 181 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 182 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 183 | _PAGE_EXEC) 184 185 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 186 187 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 188 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 189 190 extern pgd_t swapper_pg_dir[]; 191 192 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 193 static inline int pmd_present(pmd_t pmd) 194 { 195 /* 196 * Checking for _PAGE_LEAF is needed too because: 197 * When splitting a THP, split_huge_page() will temporarily clear 198 * the present bit, in this situation, pmd_present() and 199 * pmd_trans_huge() still needs to return true. 200 */ 201 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 202 } 203 #else 204 static inline int pmd_present(pmd_t pmd) 205 { 206 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 207 } 208 #endif 209 210 static inline int pmd_none(pmd_t pmd) 211 { 212 return (pmd_val(pmd) == 0); 213 } 214 215 static inline int pmd_bad(pmd_t pmd) 216 { 217 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 218 } 219 220 #define pmd_leaf pmd_leaf 221 static inline int pmd_leaf(pmd_t pmd) 222 { 223 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 224 } 225 226 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 227 { 228 *pmdp = pmd; 229 } 230 231 static inline void pmd_clear(pmd_t *pmdp) 232 { 233 set_pmd(pmdp, __pmd(0)); 234 } 235 236 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 237 { 238 unsigned long prot_val = pgprot_val(prot); 239 240 ALT_THEAD_PMA(prot_val); 241 242 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 243 } 244 245 static inline unsigned long _pgd_pfn(pgd_t pgd) 246 { 247 return __page_val_to_pfn(pgd_val(pgd)); 248 } 249 250 static inline struct page *pmd_page(pmd_t pmd) 251 { 252 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 253 } 254 255 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 256 { 257 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 258 } 259 260 static inline pte_t pmd_pte(pmd_t pmd) 261 { 262 return __pte(pmd_val(pmd)); 263 } 264 265 static inline pte_t pud_pte(pud_t pud) 266 { 267 return __pte(pud_val(pud)); 268 } 269 270 #ifdef CONFIG_RISCV_ISA_SVNAPOT 271 272 static __always_inline bool has_svnapot(void) 273 { 274 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 275 } 276 277 static inline unsigned long pte_napot(pte_t pte) 278 { 279 return pte_val(pte) & _PAGE_NAPOT; 280 } 281 282 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 283 { 284 int pos = order - 1 + _PAGE_PFN_SHIFT; 285 unsigned long napot_bit = BIT(pos); 286 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 287 288 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 289 } 290 291 #else 292 293 static __always_inline bool has_svnapot(void) { return false; } 294 295 static inline unsigned long pte_napot(pte_t pte) 296 { 297 return 0; 298 } 299 300 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 301 302 /* Yields the page frame number (PFN) of a page table entry */ 303 static inline unsigned long pte_pfn(pte_t pte) 304 { 305 unsigned long res = __page_val_to_pfn(pte_val(pte)); 306 307 if (has_svnapot() && pte_napot(pte)) 308 res = res & (res - 1UL); 309 310 return res; 311 } 312 313 #define pte_page(x) pfn_to_page(pte_pfn(x)) 314 315 /* Constructs a page table entry */ 316 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 317 { 318 unsigned long prot_val = pgprot_val(prot); 319 320 ALT_THEAD_PMA(prot_val); 321 322 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 323 } 324 325 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 326 327 static inline int pte_present(pte_t pte) 328 { 329 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 330 } 331 332 static inline int pte_none(pte_t pte) 333 { 334 return (pte_val(pte) == 0); 335 } 336 337 static inline int pte_write(pte_t pte) 338 { 339 return pte_val(pte) & _PAGE_WRITE; 340 } 341 342 static inline int pte_exec(pte_t pte) 343 { 344 return pte_val(pte) & _PAGE_EXEC; 345 } 346 347 static inline int pte_user(pte_t pte) 348 { 349 return pte_val(pte) & _PAGE_USER; 350 } 351 352 static inline int pte_huge(pte_t pte) 353 { 354 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 355 } 356 357 static inline int pte_dirty(pte_t pte) 358 { 359 return pte_val(pte) & _PAGE_DIRTY; 360 } 361 362 static inline int pte_young(pte_t pte) 363 { 364 return pte_val(pte) & _PAGE_ACCESSED; 365 } 366 367 static inline int pte_special(pte_t pte) 368 { 369 return pte_val(pte) & _PAGE_SPECIAL; 370 } 371 372 /* static inline pte_t pte_rdprotect(pte_t pte) */ 373 374 static inline pte_t pte_wrprotect(pte_t pte) 375 { 376 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 377 } 378 379 /* static inline pte_t pte_mkread(pte_t pte) */ 380 381 static inline pte_t pte_mkwrite(pte_t pte) 382 { 383 return __pte(pte_val(pte) | _PAGE_WRITE); 384 } 385 386 /* static inline pte_t pte_mkexec(pte_t pte) */ 387 388 static inline pte_t pte_mkdirty(pte_t pte) 389 { 390 return __pte(pte_val(pte) | _PAGE_DIRTY); 391 } 392 393 static inline pte_t pte_mkclean(pte_t pte) 394 { 395 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 396 } 397 398 static inline pte_t pte_mkyoung(pte_t pte) 399 { 400 return __pte(pte_val(pte) | _PAGE_ACCESSED); 401 } 402 403 static inline pte_t pte_mkold(pte_t pte) 404 { 405 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 406 } 407 408 static inline pte_t pte_mkspecial(pte_t pte) 409 { 410 return __pte(pte_val(pte) | _PAGE_SPECIAL); 411 } 412 413 static inline pte_t pte_mkhuge(pte_t pte) 414 { 415 return pte; 416 } 417 418 #ifdef CONFIG_NUMA_BALANCING 419 /* 420 * See the comment in include/asm-generic/pgtable.h 421 */ 422 static inline int pte_protnone(pte_t pte) 423 { 424 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 425 } 426 427 static inline int pmd_protnone(pmd_t pmd) 428 { 429 return pte_protnone(pmd_pte(pmd)); 430 } 431 #endif 432 433 /* Modify page protection bits */ 434 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 435 { 436 unsigned long newprot_val = pgprot_val(newprot); 437 438 ALT_THEAD_PMA(newprot_val); 439 440 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 441 } 442 443 #define pgd_ERROR(e) \ 444 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 445 446 447 /* Commit new configuration to MMU hardware */ 448 static inline void update_mmu_cache(struct vm_area_struct *vma, 449 unsigned long address, pte_t *ptep) 450 { 451 /* 452 * The kernel assumes that TLBs don't cache invalid entries, but 453 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 454 * cache flush; it is necessary even after writing invalid entries. 455 * Relying on flush_tlb_fix_spurious_fault would suffice, but 456 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 457 */ 458 local_flush_tlb_page(address); 459 } 460 461 #define __HAVE_ARCH_UPDATE_MMU_TLB 462 #define update_mmu_tlb update_mmu_cache 463 464 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 465 unsigned long address, pmd_t *pmdp) 466 { 467 pte_t *ptep = (pte_t *)pmdp; 468 469 update_mmu_cache(vma, address, ptep); 470 } 471 472 #define __HAVE_ARCH_PTE_SAME 473 static inline int pte_same(pte_t pte_a, pte_t pte_b) 474 { 475 return pte_val(pte_a) == pte_val(pte_b); 476 } 477 478 /* 479 * Certain architectures need to do special things when PTEs within 480 * a page table are directly modified. Thus, the following hook is 481 * made available. 482 */ 483 static inline void set_pte(pte_t *ptep, pte_t pteval) 484 { 485 *ptep = pteval; 486 } 487 488 void flush_icache_pte(pte_t pte); 489 490 static inline void __set_pte_at(struct mm_struct *mm, 491 unsigned long addr, pte_t *ptep, pte_t pteval) 492 { 493 if (pte_present(pteval) && pte_exec(pteval)) 494 flush_icache_pte(pteval); 495 496 set_pte(ptep, pteval); 497 } 498 499 static inline void set_pte_at(struct mm_struct *mm, 500 unsigned long addr, pte_t *ptep, pte_t pteval) 501 { 502 page_table_check_pte_set(mm, addr, ptep, pteval); 503 __set_pte_at(mm, addr, ptep, pteval); 504 } 505 506 static inline void pte_clear(struct mm_struct *mm, 507 unsigned long addr, pte_t *ptep) 508 { 509 __set_pte_at(mm, addr, ptep, __pte(0)); 510 } 511 512 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 513 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 514 unsigned long address, pte_t *ptep, 515 pte_t entry, int dirty) 516 { 517 if (!pte_same(*ptep, entry)) 518 set_pte_at(vma->vm_mm, address, ptep, entry); 519 /* 520 * update_mmu_cache will unconditionally execute, handling both 521 * the case that the PTE changed and the spurious fault case. 522 */ 523 return true; 524 } 525 526 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 527 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 528 unsigned long address, pte_t *ptep) 529 { 530 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 531 532 page_table_check_pte_clear(mm, address, pte); 533 534 return pte; 535 } 536 537 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 538 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 539 unsigned long address, 540 pte_t *ptep) 541 { 542 if (!pte_young(*ptep)) 543 return 0; 544 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 545 } 546 547 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 548 static inline void ptep_set_wrprotect(struct mm_struct *mm, 549 unsigned long address, pte_t *ptep) 550 { 551 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 552 } 553 554 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 555 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 556 unsigned long address, pte_t *ptep) 557 { 558 /* 559 * This comment is borrowed from x86, but applies equally to RISC-V: 560 * 561 * Clearing the accessed bit without a TLB flush 562 * doesn't cause data corruption. [ It could cause incorrect 563 * page aging and the (mistaken) reclaim of hot pages, but the 564 * chance of that should be relatively low. ] 565 * 566 * So as a performance optimization don't flush the TLB when 567 * clearing the accessed bit, it will eventually be flushed by 568 * a context switch or a VM operation anyway. [ In the rare 569 * event of it not getting flushed for a long time the delay 570 * shouldn't really matter because there's no real memory 571 * pressure for swapout to react to. ] 572 */ 573 return ptep_test_and_clear_young(vma, address, ptep); 574 } 575 576 #define pgprot_noncached pgprot_noncached 577 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 578 { 579 unsigned long prot = pgprot_val(_prot); 580 581 prot &= ~_PAGE_MTMASK; 582 prot |= _PAGE_IO; 583 584 return __pgprot(prot); 585 } 586 587 #define pgprot_writecombine pgprot_writecombine 588 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 589 { 590 unsigned long prot = pgprot_val(_prot); 591 592 prot &= ~_PAGE_MTMASK; 593 prot |= _PAGE_NOCACHE; 594 595 return __pgprot(prot); 596 } 597 598 /* 599 * THP functions 600 */ 601 static inline pmd_t pte_pmd(pte_t pte) 602 { 603 return __pmd(pte_val(pte)); 604 } 605 606 static inline pmd_t pmd_mkhuge(pmd_t pmd) 607 { 608 return pmd; 609 } 610 611 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 612 { 613 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 614 } 615 616 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 617 618 static inline unsigned long pmd_pfn(pmd_t pmd) 619 { 620 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 621 } 622 623 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 624 625 static inline unsigned long pud_pfn(pud_t pud) 626 { 627 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 628 } 629 630 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 631 { 632 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 633 } 634 635 #define pmd_write pmd_write 636 static inline int pmd_write(pmd_t pmd) 637 { 638 return pte_write(pmd_pte(pmd)); 639 } 640 641 static inline int pmd_dirty(pmd_t pmd) 642 { 643 return pte_dirty(pmd_pte(pmd)); 644 } 645 646 #define pmd_young pmd_young 647 static inline int pmd_young(pmd_t pmd) 648 { 649 return pte_young(pmd_pte(pmd)); 650 } 651 652 static inline int pmd_user(pmd_t pmd) 653 { 654 return pte_user(pmd_pte(pmd)); 655 } 656 657 static inline pmd_t pmd_mkold(pmd_t pmd) 658 { 659 return pte_pmd(pte_mkold(pmd_pte(pmd))); 660 } 661 662 static inline pmd_t pmd_mkyoung(pmd_t pmd) 663 { 664 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 665 } 666 667 static inline pmd_t pmd_mkwrite(pmd_t pmd) 668 { 669 return pte_pmd(pte_mkwrite(pmd_pte(pmd))); 670 } 671 672 static inline pmd_t pmd_wrprotect(pmd_t pmd) 673 { 674 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 675 } 676 677 static inline pmd_t pmd_mkclean(pmd_t pmd) 678 { 679 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 680 } 681 682 static inline pmd_t pmd_mkdirty(pmd_t pmd) 683 { 684 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 685 } 686 687 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 688 pmd_t *pmdp, pmd_t pmd) 689 { 690 page_table_check_pmd_set(mm, addr, pmdp, pmd); 691 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); 692 } 693 694 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 695 pud_t *pudp, pud_t pud) 696 { 697 page_table_check_pud_set(mm, addr, pudp, pud); 698 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); 699 } 700 701 #ifdef CONFIG_PAGE_TABLE_CHECK 702 static inline bool pte_user_accessible_page(pte_t pte) 703 { 704 return pte_present(pte) && pte_user(pte); 705 } 706 707 static inline bool pmd_user_accessible_page(pmd_t pmd) 708 { 709 return pmd_leaf(pmd) && pmd_user(pmd); 710 } 711 712 static inline bool pud_user_accessible_page(pud_t pud) 713 { 714 return pud_leaf(pud) && pud_user(pud); 715 } 716 #endif 717 718 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 719 static inline int pmd_trans_huge(pmd_t pmd) 720 { 721 return pmd_leaf(pmd); 722 } 723 724 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 725 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 726 unsigned long address, pmd_t *pmdp, 727 pmd_t entry, int dirty) 728 { 729 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 730 } 731 732 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 733 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 734 unsigned long address, pmd_t *pmdp) 735 { 736 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 737 } 738 739 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 740 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 741 unsigned long address, pmd_t *pmdp) 742 { 743 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 744 745 page_table_check_pmd_clear(mm, address, pmd); 746 747 return pmd; 748 } 749 750 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 751 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 752 unsigned long address, pmd_t *pmdp) 753 { 754 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 755 } 756 757 #define pmdp_establish pmdp_establish 758 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 759 unsigned long address, pmd_t *pmdp, pmd_t pmd) 760 { 761 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 762 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 763 } 764 765 #define pmdp_collapse_flush pmdp_collapse_flush 766 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 767 unsigned long address, pmd_t *pmdp); 768 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 769 770 /* 771 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 772 * are !pte_none() && !pte_present(). 773 * 774 * Format of swap PTE: 775 * bit 0: _PAGE_PRESENT (zero) 776 * bit 1 to 3: _PAGE_LEAF (zero) 777 * bit 5: _PAGE_PROT_NONE (zero) 778 * bit 6: exclusive marker 779 * bits 7 to 11: swap type 780 * bits 11 to XLEN-1: swap offset 781 */ 782 #define __SWP_TYPE_SHIFT 7 783 #define __SWP_TYPE_BITS 5 784 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 785 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 786 787 #define MAX_SWAPFILES_CHECK() \ 788 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 789 790 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 791 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 792 #define __swp_entry(type, offset) ((swp_entry_t) \ 793 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 794 ((offset) << __SWP_OFFSET_SHIFT) }) 795 796 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 797 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 798 799 static inline int pte_swp_exclusive(pte_t pte) 800 { 801 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 802 } 803 804 static inline pte_t pte_swp_mkexclusive(pte_t pte) 805 { 806 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 807 } 808 809 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 810 { 811 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 812 } 813 814 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 815 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 816 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 817 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 818 819 /* 820 * In the RV64 Linux scheme, we give the user half of the virtual-address space 821 * and give the kernel the other (upper) half. 822 */ 823 #ifdef CONFIG_64BIT 824 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 825 #else 826 #define KERN_VIRT_START FIXADDR_START 827 #endif 828 829 /* 830 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 831 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 832 * Task size is: 833 * - 0x9fc00000 (~2.5GB) for RV32. 834 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 835 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 836 * 837 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 838 * Instruction Set Manual Volume II: Privileged Architecture" states that 839 * "load and store effective addresses, which are 64bits, must have bits 840 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 841 */ 842 #ifdef CONFIG_64BIT 843 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 844 #define TASK_SIZE_MIN (PGDIR_SIZE_L3 * PTRS_PER_PGD / 2) 845 846 #ifdef CONFIG_COMPAT 847 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 848 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 849 TASK_SIZE_32 : TASK_SIZE_64) 850 #else 851 #define TASK_SIZE TASK_SIZE_64 852 #endif 853 854 #else 855 #define TASK_SIZE FIXADDR_START 856 #define TASK_SIZE_MIN TASK_SIZE 857 #endif 858 859 #else /* CONFIG_MMU */ 860 861 #define PAGE_SHARED __pgprot(0) 862 #define PAGE_KERNEL __pgprot(0) 863 #define swapper_pg_dir NULL 864 #define TASK_SIZE 0xffffffffUL 865 #define VMALLOC_START 0 866 #define VMALLOC_END TASK_SIZE 867 868 #endif /* !CONFIG_MMU */ 869 870 extern char _start[]; 871 extern void *_dtb_early_va; 872 extern uintptr_t _dtb_early_pa; 873 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 874 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 875 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 876 #else 877 #define dtb_early_va _dtb_early_va 878 #define dtb_early_pa _dtb_early_pa 879 #endif /* CONFIG_XIP_KERNEL */ 880 extern u64 satp_mode; 881 extern bool pgtable_l4_enabled; 882 883 void paging_init(void); 884 void misc_mem_init(void); 885 886 /* 887 * ZERO_PAGE is a global shared page that is always zero, 888 * used for zero-mapped memory areas, etc. 889 */ 890 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 891 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 892 893 #endif /* !__ASSEMBLY__ */ 894 895 #endif /* _ASM_RISCV_PGTABLE_H */ 896