1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 11 #include <asm/pgtable-bits.h> 12 13 #ifndef __ASSEMBLY__ 14 15 /* Page Upper Directory not used in RISC-V */ 16 #include <asm-generic/pgtable-nopud.h> 17 #include <asm/page.h> 18 #include <asm/tlbflush.h> 19 #include <linux/mm_types.h> 20 21 #ifdef CONFIG_64BIT 22 #include <asm/pgtable-64.h> 23 #else 24 #include <asm/pgtable-32.h> 25 #endif /* CONFIG_64BIT */ 26 27 /* Number of entries in the page global directory */ 28 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 29 /* Number of entries in the page table */ 30 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 31 32 /* Number of PGD entries that a user-mode program can use */ 33 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 34 #define FIRST_USER_ADDRESS 0 35 36 /* Page protection bits */ 37 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 38 39 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) 40 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 41 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 42 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 43 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 44 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 45 _PAGE_EXEC | _PAGE_WRITE) 46 47 #define PAGE_COPY PAGE_READ 48 #define PAGE_COPY_EXEC PAGE_EXEC 49 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 50 #define PAGE_SHARED PAGE_WRITE 51 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 52 53 #define _PAGE_KERNEL (_PAGE_READ \ 54 | _PAGE_WRITE \ 55 | _PAGE_PRESENT \ 56 | _PAGE_ACCESSED \ 57 | _PAGE_DIRTY) 58 59 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 60 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 61 62 extern pgd_t swapper_pg_dir[]; 63 64 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 65 #define __P000 PAGE_NONE 66 #define __P001 PAGE_READ 67 #define __P010 PAGE_COPY 68 #define __P011 PAGE_COPY 69 #define __P100 PAGE_EXEC 70 #define __P101 PAGE_READ_EXEC 71 #define __P110 PAGE_COPY_EXEC 72 #define __P111 PAGE_COPY_READ_EXEC 73 74 /* MAP_SHARED permissions: xwr */ 75 #define __S000 PAGE_NONE 76 #define __S001 PAGE_READ 77 #define __S010 PAGE_SHARED 78 #define __S011 PAGE_SHARED 79 #define __S100 PAGE_EXEC 80 #define __S101 PAGE_READ_EXEC 81 #define __S110 PAGE_SHARED_EXEC 82 #define __S111 PAGE_SHARED_EXEC 83 84 /* 85 * ZERO_PAGE is a global shared page that is always zero, 86 * used for zero-mapped memory areas, etc. 87 */ 88 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 89 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 90 91 static inline int pmd_present(pmd_t pmd) 92 { 93 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 94 } 95 96 static inline int pmd_none(pmd_t pmd) 97 { 98 return (pmd_val(pmd) == 0); 99 } 100 101 static inline int pmd_bad(pmd_t pmd) 102 { 103 return !pmd_present(pmd); 104 } 105 106 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 107 { 108 *pmdp = pmd; 109 } 110 111 static inline void pmd_clear(pmd_t *pmdp) 112 { 113 set_pmd(pmdp, __pmd(0)); 114 } 115 116 117 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 118 { 119 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 120 } 121 122 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 123 124 /* Locate an entry in the page global directory */ 125 static inline pgd_t *pgd_offset(const struct mm_struct *mm, unsigned long addr) 126 { 127 return mm->pgd + pgd_index(addr); 128 } 129 /* Locate an entry in the kernel page global directory */ 130 #define pgd_offset_k(addr) pgd_offset(&init_mm, (addr)) 131 132 static inline struct page *pmd_page(pmd_t pmd) 133 { 134 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 135 } 136 137 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 138 { 139 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 140 } 141 142 /* Yields the page frame number (PFN) of a page table entry */ 143 static inline unsigned long pte_pfn(pte_t pte) 144 { 145 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 146 } 147 148 #define pte_page(x) pfn_to_page(pte_pfn(x)) 149 150 /* Constructs a page table entry */ 151 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 152 { 153 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 154 } 155 156 static inline pte_t mk_pte(struct page *page, pgprot_t prot) 157 { 158 return pfn_pte(page_to_pfn(page), prot); 159 } 160 161 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 162 163 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long addr) 164 { 165 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(addr); 166 } 167 168 #define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr)) 169 #define pte_unmap(pte) ((void)(pte)) 170 171 static inline int pte_present(pte_t pte) 172 { 173 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 174 } 175 176 static inline int pte_none(pte_t pte) 177 { 178 return (pte_val(pte) == 0); 179 } 180 181 static inline int pte_write(pte_t pte) 182 { 183 return pte_val(pte) & _PAGE_WRITE; 184 } 185 186 static inline int pte_exec(pte_t pte) 187 { 188 return pte_val(pte) & _PAGE_EXEC; 189 } 190 191 static inline int pte_huge(pte_t pte) 192 { 193 return pte_present(pte) 194 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 195 } 196 197 static inline int pte_dirty(pte_t pte) 198 { 199 return pte_val(pte) & _PAGE_DIRTY; 200 } 201 202 static inline int pte_young(pte_t pte) 203 { 204 return pte_val(pte) & _PAGE_ACCESSED; 205 } 206 207 static inline int pte_special(pte_t pte) 208 { 209 return pte_val(pte) & _PAGE_SPECIAL; 210 } 211 212 /* static inline pte_t pte_rdprotect(pte_t pte) */ 213 214 static inline pte_t pte_wrprotect(pte_t pte) 215 { 216 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 217 } 218 219 /* static inline pte_t pte_mkread(pte_t pte) */ 220 221 static inline pte_t pte_mkwrite(pte_t pte) 222 { 223 return __pte(pte_val(pte) | _PAGE_WRITE); 224 } 225 226 /* static inline pte_t pte_mkexec(pte_t pte) */ 227 228 static inline pte_t pte_mkdirty(pte_t pte) 229 { 230 return __pte(pte_val(pte) | _PAGE_DIRTY); 231 } 232 233 static inline pte_t pte_mkclean(pte_t pte) 234 { 235 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 236 } 237 238 static inline pte_t pte_mkyoung(pte_t pte) 239 { 240 return __pte(pte_val(pte) | _PAGE_ACCESSED); 241 } 242 243 static inline pte_t pte_mkold(pte_t pte) 244 { 245 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 246 } 247 248 static inline pte_t pte_mkspecial(pte_t pte) 249 { 250 return __pte(pte_val(pte) | _PAGE_SPECIAL); 251 } 252 253 /* Modify page protection bits */ 254 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 255 { 256 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 257 } 258 259 #define pgd_ERROR(e) \ 260 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 261 262 263 /* Commit new configuration to MMU hardware */ 264 static inline void update_mmu_cache(struct vm_area_struct *vma, 265 unsigned long address, pte_t *ptep) 266 { 267 /* 268 * The kernel assumes that TLBs don't cache invalid entries, but 269 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 270 * cache flush; it is necessary even after writing invalid entries. 271 * Relying on flush_tlb_fix_spurious_fault would suffice, but 272 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 273 */ 274 local_flush_tlb_page(address); 275 } 276 277 #define __HAVE_ARCH_PTE_SAME 278 static inline int pte_same(pte_t pte_a, pte_t pte_b) 279 { 280 return pte_val(pte_a) == pte_val(pte_b); 281 } 282 283 /* 284 * Certain architectures need to do special things when PTEs within 285 * a page table are directly modified. Thus, the following hook is 286 * made available. 287 */ 288 static inline void set_pte(pte_t *ptep, pte_t pteval) 289 { 290 *ptep = pteval; 291 } 292 293 void flush_icache_pte(pte_t pte); 294 295 static inline void set_pte_at(struct mm_struct *mm, 296 unsigned long addr, pte_t *ptep, pte_t pteval) 297 { 298 if (pte_present(pteval) && pte_exec(pteval)) 299 flush_icache_pte(pteval); 300 301 set_pte(ptep, pteval); 302 } 303 304 static inline void pte_clear(struct mm_struct *mm, 305 unsigned long addr, pte_t *ptep) 306 { 307 set_pte_at(mm, addr, ptep, __pte(0)); 308 } 309 310 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 311 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 312 unsigned long address, pte_t *ptep, 313 pte_t entry, int dirty) 314 { 315 if (!pte_same(*ptep, entry)) 316 set_pte_at(vma->vm_mm, address, ptep, entry); 317 /* 318 * update_mmu_cache will unconditionally execute, handling both 319 * the case that the PTE changed and the spurious fault case. 320 */ 321 return true; 322 } 323 324 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 325 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 326 unsigned long address, pte_t *ptep) 327 { 328 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 329 } 330 331 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 332 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 333 unsigned long address, 334 pte_t *ptep) 335 { 336 if (!pte_young(*ptep)) 337 return 0; 338 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 339 } 340 341 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 342 static inline void ptep_set_wrprotect(struct mm_struct *mm, 343 unsigned long address, pte_t *ptep) 344 { 345 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 346 } 347 348 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 349 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 350 unsigned long address, pte_t *ptep) 351 { 352 /* 353 * This comment is borrowed from x86, but applies equally to RISC-V: 354 * 355 * Clearing the accessed bit without a TLB flush 356 * doesn't cause data corruption. [ It could cause incorrect 357 * page aging and the (mistaken) reclaim of hot pages, but the 358 * chance of that should be relatively low. ] 359 * 360 * So as a performance optimization don't flush the TLB when 361 * clearing the accessed bit, it will eventually be flushed by 362 * a context switch or a VM operation anyway. [ In the rare 363 * event of it not getting flushed for a long time the delay 364 * shouldn't really matter because there's no real memory 365 * pressure for swapout to react to. ] 366 */ 367 return ptep_test_and_clear_young(vma, address, ptep); 368 } 369 370 /* 371 * Encode and decode a swap entry 372 * 373 * Format of swap PTE: 374 * bit 0: _PAGE_PRESENT (zero) 375 * bit 1: _PAGE_PROT_NONE (zero) 376 * bits 2 to 6: swap type 377 * bits 7 to XLEN-1: swap offset 378 */ 379 #define __SWP_TYPE_SHIFT 2 380 #define __SWP_TYPE_BITS 5 381 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 382 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 383 384 #define MAX_SWAPFILES_CHECK() \ 385 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 386 387 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 388 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 389 #define __swp_entry(type, offset) ((swp_entry_t) \ 390 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 391 392 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 393 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 394 395 #ifdef CONFIG_FLATMEM 396 #define kern_addr_valid(addr) (1) /* FIXME */ 397 #endif 398 399 extern void setup_bootmem(void); 400 extern void paging_init(void); 401 402 static inline void pgtable_cache_init(void) 403 { 404 /* No page table caches to initialize */ 405 } 406 407 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 408 #define VMALLOC_END (PAGE_OFFSET - 1) 409 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 410 411 /* 412 * Task size is 0x40000000000 for RV64 or 0xb800000 for RV32. 413 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 414 */ 415 #ifdef CONFIG_64BIT 416 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 417 #else 418 #define TASK_SIZE VMALLOC_START 419 #endif 420 421 #include <asm-generic/pgtable.h> 422 423 #endif /* !__ASSEMBLY__ */ 424 425 #endif /* _ASM_RISCV_PGTABLE_H */ 426