1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef __ASSEMBLY__ 15 16 /* Page Upper Directory not used in RISC-V */ 17 #include <asm-generic/pgtable-nopud.h> 18 #include <asm/page.h> 19 #include <asm/tlbflush.h> 20 #include <linux/mm_types.h> 21 22 #ifdef CONFIG_64BIT 23 #include <asm/pgtable-64.h> 24 #else 25 #include <asm/pgtable-32.h> 26 #endif /* CONFIG_64BIT */ 27 28 #ifdef CONFIG_MMU 29 /* Number of entries in the page global directory */ 30 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 31 /* Number of entries in the page table */ 32 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 33 34 /* Number of PGD entries that a user-mode program can use */ 35 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 36 37 /* Page protection bits */ 38 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 39 40 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE) 41 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 42 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 43 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 44 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 45 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 46 _PAGE_EXEC | _PAGE_WRITE) 47 48 #define PAGE_COPY PAGE_READ 49 #define PAGE_COPY_EXEC PAGE_EXEC 50 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 51 #define PAGE_SHARED PAGE_WRITE 52 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 53 54 #define _PAGE_KERNEL (_PAGE_READ \ 55 | _PAGE_WRITE \ 56 | _PAGE_PRESENT \ 57 | _PAGE_ACCESSED \ 58 | _PAGE_DIRTY) 59 60 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 61 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 62 63 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 64 65 /* 66 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't 67 * change the properties of memory regions. 68 */ 69 #define _PAGE_IOREMAP _PAGE_KERNEL 70 71 extern pgd_t swapper_pg_dir[]; 72 73 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 74 #define __P000 PAGE_NONE 75 #define __P001 PAGE_READ 76 #define __P010 PAGE_COPY 77 #define __P011 PAGE_COPY 78 #define __P100 PAGE_EXEC 79 #define __P101 PAGE_READ_EXEC 80 #define __P110 PAGE_COPY_EXEC 81 #define __P111 PAGE_COPY_READ_EXEC 82 83 /* MAP_SHARED permissions: xwr */ 84 #define __S000 PAGE_NONE 85 #define __S001 PAGE_READ 86 #define __S010 PAGE_SHARED 87 #define __S011 PAGE_SHARED 88 #define __S100 PAGE_EXEC 89 #define __S101 PAGE_READ_EXEC 90 #define __S110 PAGE_SHARED_EXEC 91 #define __S111 PAGE_SHARED_EXEC 92 93 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 94 #define VMALLOC_END (PAGE_OFFSET - 1) 95 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 96 97 #define BPF_JIT_REGION_SIZE (SZ_128M) 98 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 99 #define BPF_JIT_REGION_END (VMALLOC_END) 100 101 /* 102 * Roughly size the vmemmap space to be large enough to fit enough 103 * struct pages to map half the virtual address space. Then 104 * position vmemmap directly below the VMALLOC region. 105 */ 106 #define VMEMMAP_SHIFT \ 107 (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 108 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 109 #define VMEMMAP_END (VMALLOC_START - 1) 110 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 111 112 /* 113 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 114 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 115 */ 116 #define vmemmap ((struct page *)VMEMMAP_START) 117 118 static inline int pmd_present(pmd_t pmd) 119 { 120 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 121 } 122 123 static inline int pmd_none(pmd_t pmd) 124 { 125 return (pmd_val(pmd) == 0); 126 } 127 128 static inline int pmd_bad(pmd_t pmd) 129 { 130 return !pmd_present(pmd); 131 } 132 133 #define pmd_leaf pmd_leaf 134 static inline int pmd_leaf(pmd_t pmd) 135 { 136 return pmd_present(pmd) && 137 (pmd_val(pmd) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 138 } 139 140 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 141 { 142 *pmdp = pmd; 143 } 144 145 static inline void pmd_clear(pmd_t *pmdp) 146 { 147 set_pmd(pmdp, __pmd(0)); 148 } 149 150 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 151 { 152 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 153 } 154 155 static inline unsigned long _pgd_pfn(pgd_t pgd) 156 { 157 return pgd_val(pgd) >> _PAGE_PFN_SHIFT; 158 } 159 160 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 161 162 /* Locate an entry in the page global directory */ 163 static inline pgd_t *pgd_offset(const struct mm_struct *mm, unsigned long addr) 164 { 165 return mm->pgd + pgd_index(addr); 166 } 167 /* Locate an entry in the kernel page global directory */ 168 #define pgd_offset_k(addr) pgd_offset(&init_mm, (addr)) 169 170 static inline struct page *pmd_page(pmd_t pmd) 171 { 172 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 173 } 174 175 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 176 { 177 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 178 } 179 180 /* Yields the page frame number (PFN) of a page table entry */ 181 static inline unsigned long pte_pfn(pte_t pte) 182 { 183 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 184 } 185 186 #define pte_page(x) pfn_to_page(pte_pfn(x)) 187 188 /* Constructs a page table entry */ 189 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 190 { 191 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 192 } 193 194 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 195 196 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 197 198 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long addr) 199 { 200 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(addr); 201 } 202 203 #define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr)) 204 #define pte_unmap(pte) ((void)(pte)) 205 206 static inline int pte_present(pte_t pte) 207 { 208 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 209 } 210 211 static inline int pte_none(pte_t pte) 212 { 213 return (pte_val(pte) == 0); 214 } 215 216 static inline int pte_write(pte_t pte) 217 { 218 return pte_val(pte) & _PAGE_WRITE; 219 } 220 221 static inline int pte_exec(pte_t pte) 222 { 223 return pte_val(pte) & _PAGE_EXEC; 224 } 225 226 static inline int pte_huge(pte_t pte) 227 { 228 return pte_present(pte) 229 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); 230 } 231 232 static inline int pte_dirty(pte_t pte) 233 { 234 return pte_val(pte) & _PAGE_DIRTY; 235 } 236 237 static inline int pte_young(pte_t pte) 238 { 239 return pte_val(pte) & _PAGE_ACCESSED; 240 } 241 242 static inline int pte_special(pte_t pte) 243 { 244 return pte_val(pte) & _PAGE_SPECIAL; 245 } 246 247 /* static inline pte_t pte_rdprotect(pte_t pte) */ 248 249 static inline pte_t pte_wrprotect(pte_t pte) 250 { 251 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 252 } 253 254 /* static inline pte_t pte_mkread(pte_t pte) */ 255 256 static inline pte_t pte_mkwrite(pte_t pte) 257 { 258 return __pte(pte_val(pte) | _PAGE_WRITE); 259 } 260 261 /* static inline pte_t pte_mkexec(pte_t pte) */ 262 263 static inline pte_t pte_mkdirty(pte_t pte) 264 { 265 return __pte(pte_val(pte) | _PAGE_DIRTY); 266 } 267 268 static inline pte_t pte_mkclean(pte_t pte) 269 { 270 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 271 } 272 273 static inline pte_t pte_mkyoung(pte_t pte) 274 { 275 return __pte(pte_val(pte) | _PAGE_ACCESSED); 276 } 277 278 static inline pte_t pte_mkold(pte_t pte) 279 { 280 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 281 } 282 283 static inline pte_t pte_mkspecial(pte_t pte) 284 { 285 return __pte(pte_val(pte) | _PAGE_SPECIAL); 286 } 287 288 static inline pte_t pte_mkhuge(pte_t pte) 289 { 290 return pte; 291 } 292 293 /* Modify page protection bits */ 294 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 295 { 296 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 297 } 298 299 #define pgd_ERROR(e) \ 300 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 301 302 303 /* Commit new configuration to MMU hardware */ 304 static inline void update_mmu_cache(struct vm_area_struct *vma, 305 unsigned long address, pte_t *ptep) 306 { 307 /* 308 * The kernel assumes that TLBs don't cache invalid entries, but 309 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 310 * cache flush; it is necessary even after writing invalid entries. 311 * Relying on flush_tlb_fix_spurious_fault would suffice, but 312 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 313 */ 314 local_flush_tlb_page(address); 315 } 316 317 #define __HAVE_ARCH_PTE_SAME 318 static inline int pte_same(pte_t pte_a, pte_t pte_b) 319 { 320 return pte_val(pte_a) == pte_val(pte_b); 321 } 322 323 /* 324 * Certain architectures need to do special things when PTEs within 325 * a page table are directly modified. Thus, the following hook is 326 * made available. 327 */ 328 static inline void set_pte(pte_t *ptep, pte_t pteval) 329 { 330 *ptep = pteval; 331 } 332 333 void flush_icache_pte(pte_t pte); 334 335 static inline void set_pte_at(struct mm_struct *mm, 336 unsigned long addr, pte_t *ptep, pte_t pteval) 337 { 338 if (pte_present(pteval) && pte_exec(pteval)) 339 flush_icache_pte(pteval); 340 341 set_pte(ptep, pteval); 342 } 343 344 static inline void pte_clear(struct mm_struct *mm, 345 unsigned long addr, pte_t *ptep) 346 { 347 set_pte_at(mm, addr, ptep, __pte(0)); 348 } 349 350 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 351 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 352 unsigned long address, pte_t *ptep, 353 pte_t entry, int dirty) 354 { 355 if (!pte_same(*ptep, entry)) 356 set_pte_at(vma->vm_mm, address, ptep, entry); 357 /* 358 * update_mmu_cache will unconditionally execute, handling both 359 * the case that the PTE changed and the spurious fault case. 360 */ 361 return true; 362 } 363 364 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 365 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 366 unsigned long address, pte_t *ptep) 367 { 368 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 369 } 370 371 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 372 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 373 unsigned long address, 374 pte_t *ptep) 375 { 376 if (!pte_young(*ptep)) 377 return 0; 378 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 379 } 380 381 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 382 static inline void ptep_set_wrprotect(struct mm_struct *mm, 383 unsigned long address, pte_t *ptep) 384 { 385 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 386 } 387 388 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 389 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 390 unsigned long address, pte_t *ptep) 391 { 392 /* 393 * This comment is borrowed from x86, but applies equally to RISC-V: 394 * 395 * Clearing the accessed bit without a TLB flush 396 * doesn't cause data corruption. [ It could cause incorrect 397 * page aging and the (mistaken) reclaim of hot pages, but the 398 * chance of that should be relatively low. ] 399 * 400 * So as a performance optimization don't flush the TLB when 401 * clearing the accessed bit, it will eventually be flushed by 402 * a context switch or a VM operation anyway. [ In the rare 403 * event of it not getting flushed for a long time the delay 404 * shouldn't really matter because there's no real memory 405 * pressure for swapout to react to. ] 406 */ 407 return ptep_test_and_clear_young(vma, address, ptep); 408 } 409 410 /* 411 * Encode and decode a swap entry 412 * 413 * Format of swap PTE: 414 * bit 0: _PAGE_PRESENT (zero) 415 * bit 1: _PAGE_PROT_NONE (zero) 416 * bits 2 to 6: swap type 417 * bits 7 to XLEN-1: swap offset 418 */ 419 #define __SWP_TYPE_SHIFT 2 420 #define __SWP_TYPE_BITS 5 421 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 422 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 423 424 #define MAX_SWAPFILES_CHECK() \ 425 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 426 427 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 428 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 429 #define __swp_entry(type, offset) ((swp_entry_t) \ 430 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 431 432 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 433 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 434 435 #define PCI_IO_SIZE SZ_16M 436 #define PCI_IO_END VMEMMAP_START 437 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 438 439 #define FIXADDR_TOP PCI_IO_START 440 #ifdef CONFIG_64BIT 441 #define FIXADDR_SIZE PMD_SIZE 442 #else 443 #define FIXADDR_SIZE PGDIR_SIZE 444 #endif 445 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 446 447 /* 448 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 449 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 450 */ 451 #ifdef CONFIG_64BIT 452 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 453 #else 454 #define TASK_SIZE FIXADDR_START 455 #endif 456 457 #else /* CONFIG_MMU */ 458 459 #define PAGE_KERNEL __pgprot(0) 460 #define swapper_pg_dir NULL 461 #define VMALLOC_START 0 462 463 #define TASK_SIZE 0xffffffffUL 464 465 #endif /* !CONFIG_MMU */ 466 467 #define kern_addr_valid(addr) (1) /* FIXME */ 468 469 extern void *dtb_early_va; 470 void setup_bootmem(void); 471 void paging_init(void); 472 473 #define FIRST_USER_ADDRESS 0 474 475 /* 476 * ZERO_PAGE is a global shared page that is always zero, 477 * used for zero-mapped memory areas, etc. 478 */ 479 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 480 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 481 482 #include <asm-generic/pgtable.h> 483 484 #endif /* !__ASSEMBLY__ */ 485 486 #endif /* _ASM_RISCV_PGTABLE_H */ 487