1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #define KERNEL_LINK_ADDR PAGE_OFFSET 16 #define KERN_VIRT_SIZE (UL(-1)) 17 #else 18 19 #define ADDRESS_SPACE_END (UL(-1)) 20 21 #ifdef CONFIG_64BIT 22 /* Leave 2GB for kernel and BPF at the end of the address space */ 23 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 24 #else 25 #define KERNEL_LINK_ADDR PAGE_OFFSET 26 #endif 27 28 /* Number of entries in the page global directory */ 29 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 30 /* Number of entries in the page table */ 31 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 32 33 /* 34 * Half of the kernel address space (1/4 of the entries of the page global 35 * directory) is for the direct mapping. 36 */ 37 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 38 39 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 40 #define VMALLOC_END PAGE_OFFSET 41 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 42 43 #define BPF_JIT_REGION_SIZE (SZ_128M) 44 #ifdef CONFIG_64BIT 45 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 46 #define BPF_JIT_REGION_END (MODULES_END) 47 #else 48 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 49 #define BPF_JIT_REGION_END (VMALLOC_END) 50 #endif 51 52 /* Modules always live before the kernel */ 53 #ifdef CONFIG_64BIT 54 /* This is used to define the end of the KASAN shadow region */ 55 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 56 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 57 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 58 #endif 59 60 /* 61 * Roughly size the vmemmap space to be large enough to fit enough 62 * struct pages to map half the virtual address space. Then 63 * position vmemmap directly below the VMALLOC region. 64 */ 65 #ifdef CONFIG_64BIT 66 #define VA_BITS (pgtable_l5_enabled ? \ 67 57 : (pgtable_l4_enabled ? 48 : 39)) 68 #else 69 #define VA_BITS 32 70 #endif 71 72 #define VMEMMAP_SHIFT \ 73 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 74 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 75 #define VMEMMAP_END VMALLOC_START 76 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 77 78 /* 79 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 80 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 81 */ 82 #define vmemmap ((struct page *)VMEMMAP_START) 83 84 #define PCI_IO_SIZE SZ_16M 85 #define PCI_IO_END VMEMMAP_START 86 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 87 88 #define FIXADDR_TOP PCI_IO_START 89 #ifdef CONFIG_64BIT 90 #define MAX_FDT_SIZE PMD_SIZE 91 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 92 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 93 #else 94 #define MAX_FDT_SIZE PGDIR_SIZE 95 #define FIX_FDT_SIZE MAX_FDT_SIZE 96 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 97 #endif 98 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 99 100 #endif 101 102 #ifdef CONFIG_XIP_KERNEL 103 #define XIP_OFFSET SZ_32M 104 #define XIP_OFFSET_MASK (SZ_32M - 1) 105 #else 106 #define XIP_OFFSET 0 107 #endif 108 109 #ifndef __ASSEMBLY__ 110 111 #include <asm/page.h> 112 #include <asm/tlbflush.h> 113 #include <linux/mm_types.h> 114 115 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 116 117 #ifdef CONFIG_64BIT 118 #include <asm/pgtable-64.h> 119 #else 120 #include <asm/pgtable-32.h> 121 #endif /* CONFIG_64BIT */ 122 123 #include <linux/page_table_check.h> 124 125 #ifdef CONFIG_XIP_KERNEL 126 #define XIP_FIXUP(addr) ({ \ 127 uintptr_t __a = (uintptr_t)(addr); \ 128 (__a >= CONFIG_XIP_PHYS_ADDR && \ 129 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ? \ 130 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ 131 __a; \ 132 }) 133 #else 134 #define XIP_FIXUP(addr) (addr) 135 #endif /* CONFIG_XIP_KERNEL */ 136 137 struct pt_alloc_ops { 138 pte_t *(*get_pte_virt)(phys_addr_t pa); 139 phys_addr_t (*alloc_pte)(uintptr_t va); 140 #ifndef __PAGETABLE_PMD_FOLDED 141 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 142 phys_addr_t (*alloc_pmd)(uintptr_t va); 143 pud_t *(*get_pud_virt)(phys_addr_t pa); 144 phys_addr_t (*alloc_pud)(uintptr_t va); 145 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 146 phys_addr_t (*alloc_p4d)(uintptr_t va); 147 #endif 148 }; 149 150 extern struct pt_alloc_ops pt_ops __initdata; 151 152 #ifdef CONFIG_MMU 153 /* Number of PGD entries that a user-mode program can use */ 154 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 155 156 /* Page protection bits */ 157 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 158 159 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 160 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 161 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 162 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 163 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 164 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 165 _PAGE_EXEC | _PAGE_WRITE) 166 167 #define PAGE_COPY PAGE_READ 168 #define PAGE_COPY_EXEC PAGE_EXEC 169 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 170 #define PAGE_SHARED PAGE_WRITE 171 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 172 173 #define _PAGE_KERNEL (_PAGE_READ \ 174 | _PAGE_WRITE \ 175 | _PAGE_PRESENT \ 176 | _PAGE_ACCESSED \ 177 | _PAGE_DIRTY \ 178 | _PAGE_GLOBAL) 179 180 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 181 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 182 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 183 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 184 | _PAGE_EXEC) 185 186 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 187 188 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 189 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 190 191 extern pgd_t swapper_pg_dir[]; 192 193 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 194 static inline int pmd_present(pmd_t pmd) 195 { 196 /* 197 * Checking for _PAGE_LEAF is needed too because: 198 * When splitting a THP, split_huge_page() will temporarily clear 199 * the present bit, in this situation, pmd_present() and 200 * pmd_trans_huge() still needs to return true. 201 */ 202 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 203 } 204 #else 205 static inline int pmd_present(pmd_t pmd) 206 { 207 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 208 } 209 #endif 210 211 static inline int pmd_none(pmd_t pmd) 212 { 213 return (pmd_val(pmd) == 0); 214 } 215 216 static inline int pmd_bad(pmd_t pmd) 217 { 218 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 219 } 220 221 #define pmd_leaf pmd_leaf 222 static inline int pmd_leaf(pmd_t pmd) 223 { 224 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 225 } 226 227 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 228 { 229 *pmdp = pmd; 230 } 231 232 static inline void pmd_clear(pmd_t *pmdp) 233 { 234 set_pmd(pmdp, __pmd(0)); 235 } 236 237 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 238 { 239 unsigned long prot_val = pgprot_val(prot); 240 241 ALT_THEAD_PMA(prot_val); 242 243 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 244 } 245 246 static inline unsigned long _pgd_pfn(pgd_t pgd) 247 { 248 return __page_val_to_pfn(pgd_val(pgd)); 249 } 250 251 static inline struct page *pmd_page(pmd_t pmd) 252 { 253 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 254 } 255 256 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 257 { 258 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 259 } 260 261 static inline pte_t pmd_pte(pmd_t pmd) 262 { 263 return __pte(pmd_val(pmd)); 264 } 265 266 static inline pte_t pud_pte(pud_t pud) 267 { 268 return __pte(pud_val(pud)); 269 } 270 271 #ifdef CONFIG_RISCV_ISA_SVNAPOT 272 273 static __always_inline bool has_svnapot(void) 274 { 275 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 276 } 277 278 static inline unsigned long pte_napot(pte_t pte) 279 { 280 return pte_val(pte) & _PAGE_NAPOT; 281 } 282 283 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 284 { 285 int pos = order - 1 + _PAGE_PFN_SHIFT; 286 unsigned long napot_bit = BIT(pos); 287 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 288 289 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 290 } 291 292 #else 293 294 static __always_inline bool has_svnapot(void) { return false; } 295 296 static inline unsigned long pte_napot(pte_t pte) 297 { 298 return 0; 299 } 300 301 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 302 303 /* Yields the page frame number (PFN) of a page table entry */ 304 static inline unsigned long pte_pfn(pte_t pte) 305 { 306 unsigned long res = __page_val_to_pfn(pte_val(pte)); 307 308 if (has_svnapot() && pte_napot(pte)) 309 res = res & (res - 1UL); 310 311 return res; 312 } 313 314 #define pte_page(x) pfn_to_page(pte_pfn(x)) 315 316 /* Constructs a page table entry */ 317 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 318 { 319 unsigned long prot_val = pgprot_val(prot); 320 321 ALT_THEAD_PMA(prot_val); 322 323 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 324 } 325 326 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 327 328 static inline int pte_present(pte_t pte) 329 { 330 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 331 } 332 333 static inline int pte_none(pte_t pte) 334 { 335 return (pte_val(pte) == 0); 336 } 337 338 static inline int pte_write(pte_t pte) 339 { 340 return pte_val(pte) & _PAGE_WRITE; 341 } 342 343 static inline int pte_exec(pte_t pte) 344 { 345 return pte_val(pte) & _PAGE_EXEC; 346 } 347 348 static inline int pte_user(pte_t pte) 349 { 350 return pte_val(pte) & _PAGE_USER; 351 } 352 353 static inline int pte_huge(pte_t pte) 354 { 355 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 356 } 357 358 static inline int pte_dirty(pte_t pte) 359 { 360 return pte_val(pte) & _PAGE_DIRTY; 361 } 362 363 static inline int pte_young(pte_t pte) 364 { 365 return pte_val(pte) & _PAGE_ACCESSED; 366 } 367 368 static inline int pte_special(pte_t pte) 369 { 370 return pte_val(pte) & _PAGE_SPECIAL; 371 } 372 373 /* static inline pte_t pte_rdprotect(pte_t pte) */ 374 375 static inline pte_t pte_wrprotect(pte_t pte) 376 { 377 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 378 } 379 380 /* static inline pte_t pte_mkread(pte_t pte) */ 381 382 static inline pte_t pte_mkwrite(pte_t pte) 383 { 384 return __pte(pte_val(pte) | _PAGE_WRITE); 385 } 386 387 /* static inline pte_t pte_mkexec(pte_t pte) */ 388 389 static inline pte_t pte_mkdirty(pte_t pte) 390 { 391 return __pte(pte_val(pte) | _PAGE_DIRTY); 392 } 393 394 static inline pte_t pte_mkclean(pte_t pte) 395 { 396 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 397 } 398 399 static inline pte_t pte_mkyoung(pte_t pte) 400 { 401 return __pte(pte_val(pte) | _PAGE_ACCESSED); 402 } 403 404 static inline pte_t pte_mkold(pte_t pte) 405 { 406 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 407 } 408 409 static inline pte_t pte_mkspecial(pte_t pte) 410 { 411 return __pte(pte_val(pte) | _PAGE_SPECIAL); 412 } 413 414 static inline pte_t pte_mkhuge(pte_t pte) 415 { 416 return pte; 417 } 418 419 #ifdef CONFIG_NUMA_BALANCING 420 /* 421 * See the comment in include/asm-generic/pgtable.h 422 */ 423 static inline int pte_protnone(pte_t pte) 424 { 425 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 426 } 427 428 static inline int pmd_protnone(pmd_t pmd) 429 { 430 return pte_protnone(pmd_pte(pmd)); 431 } 432 #endif 433 434 /* Modify page protection bits */ 435 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 436 { 437 unsigned long newprot_val = pgprot_val(newprot); 438 439 ALT_THEAD_PMA(newprot_val); 440 441 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 442 } 443 444 #define pgd_ERROR(e) \ 445 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 446 447 448 /* Commit new configuration to MMU hardware */ 449 static inline void update_mmu_cache(struct vm_area_struct *vma, 450 unsigned long address, pte_t *ptep) 451 { 452 /* 453 * The kernel assumes that TLBs don't cache invalid entries, but 454 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 455 * cache flush; it is necessary even after writing invalid entries. 456 * Relying on flush_tlb_fix_spurious_fault would suffice, but 457 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 458 */ 459 local_flush_tlb_page(address); 460 } 461 462 #define __HAVE_ARCH_UPDATE_MMU_TLB 463 #define update_mmu_tlb update_mmu_cache 464 465 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 466 unsigned long address, pmd_t *pmdp) 467 { 468 pte_t *ptep = (pte_t *)pmdp; 469 470 update_mmu_cache(vma, address, ptep); 471 } 472 473 #define __HAVE_ARCH_PTE_SAME 474 static inline int pte_same(pte_t pte_a, pte_t pte_b) 475 { 476 return pte_val(pte_a) == pte_val(pte_b); 477 } 478 479 /* 480 * Certain architectures need to do special things when PTEs within 481 * a page table are directly modified. Thus, the following hook is 482 * made available. 483 */ 484 static inline void set_pte(pte_t *ptep, pte_t pteval) 485 { 486 *ptep = pteval; 487 } 488 489 void flush_icache_pte(pte_t pte); 490 491 static inline void __set_pte_at(struct mm_struct *mm, 492 unsigned long addr, pte_t *ptep, pte_t pteval) 493 { 494 if (pte_present(pteval) && pte_exec(pteval)) 495 flush_icache_pte(pteval); 496 497 set_pte(ptep, pteval); 498 } 499 500 static inline void set_pte_at(struct mm_struct *mm, 501 unsigned long addr, pte_t *ptep, pte_t pteval) 502 { 503 page_table_check_pte_set(mm, addr, ptep, pteval); 504 __set_pte_at(mm, addr, ptep, pteval); 505 } 506 507 static inline void pte_clear(struct mm_struct *mm, 508 unsigned long addr, pte_t *ptep) 509 { 510 __set_pte_at(mm, addr, ptep, __pte(0)); 511 } 512 513 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 514 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 515 unsigned long address, pte_t *ptep, 516 pte_t entry, int dirty) 517 { 518 if (!pte_same(*ptep, entry)) 519 set_pte_at(vma->vm_mm, address, ptep, entry); 520 /* 521 * update_mmu_cache will unconditionally execute, handling both 522 * the case that the PTE changed and the spurious fault case. 523 */ 524 return true; 525 } 526 527 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 528 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 529 unsigned long address, pte_t *ptep) 530 { 531 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 532 533 page_table_check_pte_clear(mm, address, pte); 534 535 return pte; 536 } 537 538 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 539 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 540 unsigned long address, 541 pte_t *ptep) 542 { 543 if (!pte_young(*ptep)) 544 return 0; 545 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 546 } 547 548 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 549 static inline void ptep_set_wrprotect(struct mm_struct *mm, 550 unsigned long address, pte_t *ptep) 551 { 552 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 553 } 554 555 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 556 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 557 unsigned long address, pte_t *ptep) 558 { 559 /* 560 * This comment is borrowed from x86, but applies equally to RISC-V: 561 * 562 * Clearing the accessed bit without a TLB flush 563 * doesn't cause data corruption. [ It could cause incorrect 564 * page aging and the (mistaken) reclaim of hot pages, but the 565 * chance of that should be relatively low. ] 566 * 567 * So as a performance optimization don't flush the TLB when 568 * clearing the accessed bit, it will eventually be flushed by 569 * a context switch or a VM operation anyway. [ In the rare 570 * event of it not getting flushed for a long time the delay 571 * shouldn't really matter because there's no real memory 572 * pressure for swapout to react to. ] 573 */ 574 return ptep_test_and_clear_young(vma, address, ptep); 575 } 576 577 #define pgprot_noncached pgprot_noncached 578 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 579 { 580 unsigned long prot = pgprot_val(_prot); 581 582 prot &= ~_PAGE_MTMASK; 583 prot |= _PAGE_IO; 584 585 return __pgprot(prot); 586 } 587 588 #define pgprot_writecombine pgprot_writecombine 589 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 590 { 591 unsigned long prot = pgprot_val(_prot); 592 593 prot &= ~_PAGE_MTMASK; 594 prot |= _PAGE_NOCACHE; 595 596 return __pgprot(prot); 597 } 598 599 /* 600 * THP functions 601 */ 602 static inline pmd_t pte_pmd(pte_t pte) 603 { 604 return __pmd(pte_val(pte)); 605 } 606 607 static inline pmd_t pmd_mkhuge(pmd_t pmd) 608 { 609 return pmd; 610 } 611 612 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 613 { 614 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 615 } 616 617 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 618 619 static inline unsigned long pmd_pfn(pmd_t pmd) 620 { 621 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 622 } 623 624 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 625 626 static inline unsigned long pud_pfn(pud_t pud) 627 { 628 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 629 } 630 631 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 632 { 633 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 634 } 635 636 #define pmd_write pmd_write 637 static inline int pmd_write(pmd_t pmd) 638 { 639 return pte_write(pmd_pte(pmd)); 640 } 641 642 static inline int pmd_dirty(pmd_t pmd) 643 { 644 return pte_dirty(pmd_pte(pmd)); 645 } 646 647 #define pmd_young pmd_young 648 static inline int pmd_young(pmd_t pmd) 649 { 650 return pte_young(pmd_pte(pmd)); 651 } 652 653 static inline int pmd_user(pmd_t pmd) 654 { 655 return pte_user(pmd_pte(pmd)); 656 } 657 658 static inline pmd_t pmd_mkold(pmd_t pmd) 659 { 660 return pte_pmd(pte_mkold(pmd_pte(pmd))); 661 } 662 663 static inline pmd_t pmd_mkyoung(pmd_t pmd) 664 { 665 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 666 } 667 668 static inline pmd_t pmd_mkwrite(pmd_t pmd) 669 { 670 return pte_pmd(pte_mkwrite(pmd_pte(pmd))); 671 } 672 673 static inline pmd_t pmd_wrprotect(pmd_t pmd) 674 { 675 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 676 } 677 678 static inline pmd_t pmd_mkclean(pmd_t pmd) 679 { 680 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 681 } 682 683 static inline pmd_t pmd_mkdirty(pmd_t pmd) 684 { 685 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 686 } 687 688 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 689 pmd_t *pmdp, pmd_t pmd) 690 { 691 page_table_check_pmd_set(mm, addr, pmdp, pmd); 692 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); 693 } 694 695 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 696 pud_t *pudp, pud_t pud) 697 { 698 page_table_check_pud_set(mm, addr, pudp, pud); 699 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); 700 } 701 702 #ifdef CONFIG_PAGE_TABLE_CHECK 703 static inline bool pte_user_accessible_page(pte_t pte) 704 { 705 return pte_present(pte) && pte_user(pte); 706 } 707 708 static inline bool pmd_user_accessible_page(pmd_t pmd) 709 { 710 return pmd_leaf(pmd) && pmd_user(pmd); 711 } 712 713 static inline bool pud_user_accessible_page(pud_t pud) 714 { 715 return pud_leaf(pud) && pud_user(pud); 716 } 717 #endif 718 719 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 720 static inline int pmd_trans_huge(pmd_t pmd) 721 { 722 return pmd_leaf(pmd); 723 } 724 725 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 726 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 727 unsigned long address, pmd_t *pmdp, 728 pmd_t entry, int dirty) 729 { 730 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 731 } 732 733 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 734 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 735 unsigned long address, pmd_t *pmdp) 736 { 737 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 738 } 739 740 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 741 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 742 unsigned long address, pmd_t *pmdp) 743 { 744 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 745 746 page_table_check_pmd_clear(mm, address, pmd); 747 748 return pmd; 749 } 750 751 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 752 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 753 unsigned long address, pmd_t *pmdp) 754 { 755 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 756 } 757 758 #define pmdp_establish pmdp_establish 759 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 760 unsigned long address, pmd_t *pmdp, pmd_t pmd) 761 { 762 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 763 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 764 } 765 766 #define pmdp_collapse_flush pmdp_collapse_flush 767 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 768 unsigned long address, pmd_t *pmdp); 769 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 770 771 /* 772 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 773 * are !pte_none() && !pte_present(). 774 * 775 * Format of swap PTE: 776 * bit 0: _PAGE_PRESENT (zero) 777 * bit 1 to 3: _PAGE_LEAF (zero) 778 * bit 5: _PAGE_PROT_NONE (zero) 779 * bit 6: exclusive marker 780 * bits 7 to 11: swap type 781 * bits 11 to XLEN-1: swap offset 782 */ 783 #define __SWP_TYPE_SHIFT 7 784 #define __SWP_TYPE_BITS 5 785 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 786 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 787 788 #define MAX_SWAPFILES_CHECK() \ 789 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 790 791 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 792 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 793 #define __swp_entry(type, offset) ((swp_entry_t) \ 794 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 795 ((offset) << __SWP_OFFSET_SHIFT) }) 796 797 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 798 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 799 800 static inline int pte_swp_exclusive(pte_t pte) 801 { 802 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 803 } 804 805 static inline pte_t pte_swp_mkexclusive(pte_t pte) 806 { 807 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 808 } 809 810 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 811 { 812 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 813 } 814 815 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 816 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 817 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 818 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 819 820 /* 821 * In the RV64 Linux scheme, we give the user half of the virtual-address space 822 * and give the kernel the other (upper) half. 823 */ 824 #ifdef CONFIG_64BIT 825 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 826 #else 827 #define KERN_VIRT_START FIXADDR_START 828 #endif 829 830 /* 831 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 832 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 833 * Task size is: 834 * - 0x9fc00000 (~2.5GB) for RV32. 835 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 836 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 837 * 838 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 839 * Instruction Set Manual Volume II: Privileged Architecture" states that 840 * "load and store effective addresses, which are 64bits, must have bits 841 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 842 */ 843 #ifdef CONFIG_64BIT 844 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 845 #define TASK_SIZE_MIN (PGDIR_SIZE_L3 * PTRS_PER_PGD / 2) 846 847 #ifdef CONFIG_COMPAT 848 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 849 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 850 TASK_SIZE_32 : TASK_SIZE_64) 851 #else 852 #define TASK_SIZE TASK_SIZE_64 853 #endif 854 855 #else 856 #define TASK_SIZE FIXADDR_START 857 #define TASK_SIZE_MIN TASK_SIZE 858 #endif 859 860 #else /* CONFIG_MMU */ 861 862 #define PAGE_SHARED __pgprot(0) 863 #define PAGE_KERNEL __pgprot(0) 864 #define swapper_pg_dir NULL 865 #define TASK_SIZE 0xffffffffUL 866 #define VMALLOC_START 0 867 #define VMALLOC_END TASK_SIZE 868 869 #endif /* !CONFIG_MMU */ 870 871 extern char _start[]; 872 extern void *_dtb_early_va; 873 extern uintptr_t _dtb_early_pa; 874 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 875 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 876 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 877 #else 878 #define dtb_early_va _dtb_early_va 879 #define dtb_early_pa _dtb_early_pa 880 #endif /* CONFIG_XIP_KERNEL */ 881 extern u64 satp_mode; 882 extern bool pgtable_l4_enabled; 883 884 void paging_init(void); 885 void misc_mem_init(void); 886 887 /* 888 * ZERO_PAGE is a global shared page that is always zero, 889 * used for zero-mapped memory areas, etc. 890 */ 891 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 892 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 893 894 #endif /* !__ASSEMBLY__ */ 895 896 #endif /* _ASM_RISCV_PGTABLE_H */ 897