1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #define KERNEL_LINK_ADDR PAGE_OFFSET 16 #else 17 18 #define ADDRESS_SPACE_END (UL(-1)) 19 20 #ifdef CONFIG_64BIT 21 /* Leave 2GB for kernel and BPF at the end of the address space */ 22 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 23 #else 24 #define KERNEL_LINK_ADDR PAGE_OFFSET 25 #endif 26 27 /* Number of entries in the page global directory */ 28 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 29 /* Number of entries in the page table */ 30 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 31 32 /* 33 * Half of the kernel address space (half of the entries of the page global 34 * directory) is for the direct mapping. 35 */ 36 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 37 38 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 39 #define VMALLOC_END PAGE_OFFSET 40 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 41 42 #define BPF_JIT_REGION_SIZE (SZ_128M) 43 #ifdef CONFIG_64BIT 44 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 45 #define BPF_JIT_REGION_END (MODULES_END) 46 #else 47 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 48 #define BPF_JIT_REGION_END (VMALLOC_END) 49 #endif 50 51 /* Modules always live before the kernel */ 52 #ifdef CONFIG_64BIT 53 /* This is used to define the end of the KASAN shadow region */ 54 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 55 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 56 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 57 #endif 58 59 /* 60 * Roughly size the vmemmap space to be large enough to fit enough 61 * struct pages to map half the virtual address space. Then 62 * position vmemmap directly below the VMALLOC region. 63 */ 64 #ifdef CONFIG_64BIT 65 #define VA_BITS (pgtable_l4_enabled ? 48 : 39) 66 #else 67 #define VA_BITS 32 68 #endif 69 70 #define VMEMMAP_SHIFT \ 71 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 72 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 73 #define VMEMMAP_END VMALLOC_START 74 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 75 76 /* 77 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 78 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 79 */ 80 #define vmemmap ((struct page *)VMEMMAP_START) 81 82 #define PCI_IO_SIZE SZ_16M 83 #define PCI_IO_END VMEMMAP_START 84 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 85 86 #define FIXADDR_TOP PCI_IO_START 87 #ifdef CONFIG_64BIT 88 #define FIXADDR_SIZE PMD_SIZE 89 #else 90 #define FIXADDR_SIZE PGDIR_SIZE 91 #endif 92 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 93 94 #endif 95 96 #ifdef CONFIG_XIP_KERNEL 97 #define XIP_OFFSET SZ_32M 98 #define XIP_OFFSET_MASK (SZ_32M - 1) 99 #else 100 #define XIP_OFFSET 0 101 #endif 102 103 #ifndef __ASSEMBLY__ 104 105 #include <asm-generic/pgtable-nop4d.h> 106 #include <asm/page.h> 107 #include <asm/tlbflush.h> 108 #include <linux/mm_types.h> 109 110 #ifdef CONFIG_64BIT 111 #include <asm/pgtable-64.h> 112 #else 113 #include <asm/pgtable-32.h> 114 #endif /* CONFIG_64BIT */ 115 116 #ifdef CONFIG_XIP_KERNEL 117 #define XIP_FIXUP(addr) ({ \ 118 uintptr_t __a = (uintptr_t)(addr); \ 119 (__a >= CONFIG_XIP_PHYS_ADDR && \ 120 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ? \ 121 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ 122 __a; \ 123 }) 124 #else 125 #define XIP_FIXUP(addr) (addr) 126 #endif /* CONFIG_XIP_KERNEL */ 127 128 struct pt_alloc_ops { 129 pte_t *(*get_pte_virt)(phys_addr_t pa); 130 phys_addr_t (*alloc_pte)(uintptr_t va); 131 #ifndef __PAGETABLE_PMD_FOLDED 132 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 133 phys_addr_t (*alloc_pmd)(uintptr_t va); 134 pud_t *(*get_pud_virt)(phys_addr_t pa); 135 phys_addr_t (*alloc_pud)(uintptr_t va); 136 #endif 137 }; 138 139 extern struct pt_alloc_ops pt_ops __initdata; 140 141 #ifdef CONFIG_MMU 142 /* Number of PGD entries that a user-mode program can use */ 143 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 144 145 /* Page protection bits */ 146 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 147 148 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 149 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 150 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 151 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 152 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 154 _PAGE_EXEC | _PAGE_WRITE) 155 156 #define PAGE_COPY PAGE_READ 157 #define PAGE_COPY_EXEC PAGE_EXEC 158 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC 159 #define PAGE_SHARED PAGE_WRITE 160 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 161 162 #define _PAGE_KERNEL (_PAGE_READ \ 163 | _PAGE_WRITE \ 164 | _PAGE_PRESENT \ 165 | _PAGE_ACCESSED \ 166 | _PAGE_DIRTY \ 167 | _PAGE_GLOBAL) 168 169 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 170 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 171 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 172 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 173 | _PAGE_EXEC) 174 175 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 176 177 /* 178 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't 179 * change the properties of memory regions. 180 */ 181 #define _PAGE_IOREMAP _PAGE_KERNEL 182 183 extern pgd_t swapper_pg_dir[]; 184 185 /* MAP_PRIVATE permissions: xwr (copy-on-write) */ 186 #define __P000 PAGE_NONE 187 #define __P001 PAGE_READ 188 #define __P010 PAGE_COPY 189 #define __P011 PAGE_COPY 190 #define __P100 PAGE_EXEC 191 #define __P101 PAGE_READ_EXEC 192 #define __P110 PAGE_COPY_EXEC 193 #define __P111 PAGE_COPY_READ_EXEC 194 195 /* MAP_SHARED permissions: xwr */ 196 #define __S000 PAGE_NONE 197 #define __S001 PAGE_READ 198 #define __S010 PAGE_SHARED 199 #define __S011 PAGE_SHARED 200 #define __S100 PAGE_EXEC 201 #define __S101 PAGE_READ_EXEC 202 #define __S110 PAGE_SHARED_EXEC 203 #define __S111 PAGE_SHARED_EXEC 204 205 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 206 static inline int pmd_present(pmd_t pmd) 207 { 208 /* 209 * Checking for _PAGE_LEAF is needed too because: 210 * When splitting a THP, split_huge_page() will temporarily clear 211 * the present bit, in this situation, pmd_present() and 212 * pmd_trans_huge() still needs to return true. 213 */ 214 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 215 } 216 #else 217 static inline int pmd_present(pmd_t pmd) 218 { 219 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 220 } 221 #endif 222 223 static inline int pmd_none(pmd_t pmd) 224 { 225 return (pmd_val(pmd) == 0); 226 } 227 228 static inline int pmd_bad(pmd_t pmd) 229 { 230 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 231 } 232 233 #define pmd_leaf pmd_leaf 234 static inline int pmd_leaf(pmd_t pmd) 235 { 236 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 237 } 238 239 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 240 { 241 *pmdp = pmd; 242 } 243 244 static inline void pmd_clear(pmd_t *pmdp) 245 { 246 set_pmd(pmdp, __pmd(0)); 247 } 248 249 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 250 { 251 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 252 } 253 254 static inline unsigned long _pgd_pfn(pgd_t pgd) 255 { 256 return pgd_val(pgd) >> _PAGE_PFN_SHIFT; 257 } 258 259 static inline struct page *pmd_page(pmd_t pmd) 260 { 261 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 262 } 263 264 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 265 { 266 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); 267 } 268 269 static inline pte_t pmd_pte(pmd_t pmd) 270 { 271 return __pte(pmd_val(pmd)); 272 } 273 274 static inline pte_t pud_pte(pud_t pud) 275 { 276 return __pte(pud_val(pud)); 277 } 278 279 /* Yields the page frame number (PFN) of a page table entry */ 280 static inline unsigned long pte_pfn(pte_t pte) 281 { 282 return (pte_val(pte) >> _PAGE_PFN_SHIFT); 283 } 284 285 #define pte_page(x) pfn_to_page(pte_pfn(x)) 286 287 /* Constructs a page table entry */ 288 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 289 { 290 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); 291 } 292 293 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 294 295 static inline int pte_present(pte_t pte) 296 { 297 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 298 } 299 300 static inline int pte_none(pte_t pte) 301 { 302 return (pte_val(pte) == 0); 303 } 304 305 static inline int pte_write(pte_t pte) 306 { 307 return pte_val(pte) & _PAGE_WRITE; 308 } 309 310 static inline int pte_exec(pte_t pte) 311 { 312 return pte_val(pte) & _PAGE_EXEC; 313 } 314 315 static inline int pte_huge(pte_t pte) 316 { 317 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 318 } 319 320 static inline int pte_dirty(pte_t pte) 321 { 322 return pte_val(pte) & _PAGE_DIRTY; 323 } 324 325 static inline int pte_young(pte_t pte) 326 { 327 return pte_val(pte) & _PAGE_ACCESSED; 328 } 329 330 static inline int pte_special(pte_t pte) 331 { 332 return pte_val(pte) & _PAGE_SPECIAL; 333 } 334 335 /* static inline pte_t pte_rdprotect(pte_t pte) */ 336 337 static inline pte_t pte_wrprotect(pte_t pte) 338 { 339 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 340 } 341 342 /* static inline pte_t pte_mkread(pte_t pte) */ 343 344 static inline pte_t pte_mkwrite(pte_t pte) 345 { 346 return __pte(pte_val(pte) | _PAGE_WRITE); 347 } 348 349 /* static inline pte_t pte_mkexec(pte_t pte) */ 350 351 static inline pte_t pte_mkdirty(pte_t pte) 352 { 353 return __pte(pte_val(pte) | _PAGE_DIRTY); 354 } 355 356 static inline pte_t pte_mkclean(pte_t pte) 357 { 358 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 359 } 360 361 static inline pte_t pte_mkyoung(pte_t pte) 362 { 363 return __pte(pte_val(pte) | _PAGE_ACCESSED); 364 } 365 366 static inline pte_t pte_mkold(pte_t pte) 367 { 368 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 369 } 370 371 static inline pte_t pte_mkspecial(pte_t pte) 372 { 373 return __pte(pte_val(pte) | _PAGE_SPECIAL); 374 } 375 376 static inline pte_t pte_mkhuge(pte_t pte) 377 { 378 return pte; 379 } 380 381 #ifdef CONFIG_NUMA_BALANCING 382 /* 383 * See the comment in include/asm-generic/pgtable.h 384 */ 385 static inline int pte_protnone(pte_t pte) 386 { 387 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 388 } 389 390 static inline int pmd_protnone(pmd_t pmd) 391 { 392 return pte_protnone(pmd_pte(pmd)); 393 } 394 #endif 395 396 /* Modify page protection bits */ 397 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 398 { 399 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 400 } 401 402 #define pgd_ERROR(e) \ 403 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 404 405 406 /* Commit new configuration to MMU hardware */ 407 static inline void update_mmu_cache(struct vm_area_struct *vma, 408 unsigned long address, pte_t *ptep) 409 { 410 /* 411 * The kernel assumes that TLBs don't cache invalid entries, but 412 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 413 * cache flush; it is necessary even after writing invalid entries. 414 * Relying on flush_tlb_fix_spurious_fault would suffice, but 415 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 416 */ 417 local_flush_tlb_page(address); 418 } 419 420 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 421 unsigned long address, pmd_t *pmdp) 422 { 423 pte_t *ptep = (pte_t *)pmdp; 424 425 update_mmu_cache(vma, address, ptep); 426 } 427 428 #define __HAVE_ARCH_PTE_SAME 429 static inline int pte_same(pte_t pte_a, pte_t pte_b) 430 { 431 return pte_val(pte_a) == pte_val(pte_b); 432 } 433 434 /* 435 * Certain architectures need to do special things when PTEs within 436 * a page table are directly modified. Thus, the following hook is 437 * made available. 438 */ 439 static inline void set_pte(pte_t *ptep, pte_t pteval) 440 { 441 *ptep = pteval; 442 } 443 444 void flush_icache_pte(pte_t pte); 445 446 static inline void set_pte_at(struct mm_struct *mm, 447 unsigned long addr, pte_t *ptep, pte_t pteval) 448 { 449 if (pte_present(pteval) && pte_exec(pteval)) 450 flush_icache_pte(pteval); 451 452 set_pte(ptep, pteval); 453 } 454 455 static inline void pte_clear(struct mm_struct *mm, 456 unsigned long addr, pte_t *ptep) 457 { 458 set_pte_at(mm, addr, ptep, __pte(0)); 459 } 460 461 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 462 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 463 unsigned long address, pte_t *ptep, 464 pte_t entry, int dirty) 465 { 466 if (!pte_same(*ptep, entry)) 467 set_pte_at(vma->vm_mm, address, ptep, entry); 468 /* 469 * update_mmu_cache will unconditionally execute, handling both 470 * the case that the PTE changed and the spurious fault case. 471 */ 472 return true; 473 } 474 475 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 476 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 477 unsigned long address, pte_t *ptep) 478 { 479 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 480 } 481 482 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 483 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 484 unsigned long address, 485 pte_t *ptep) 486 { 487 if (!pte_young(*ptep)) 488 return 0; 489 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); 490 } 491 492 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 493 static inline void ptep_set_wrprotect(struct mm_struct *mm, 494 unsigned long address, pte_t *ptep) 495 { 496 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 497 } 498 499 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 500 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 501 unsigned long address, pte_t *ptep) 502 { 503 /* 504 * This comment is borrowed from x86, but applies equally to RISC-V: 505 * 506 * Clearing the accessed bit without a TLB flush 507 * doesn't cause data corruption. [ It could cause incorrect 508 * page aging and the (mistaken) reclaim of hot pages, but the 509 * chance of that should be relatively low. ] 510 * 511 * So as a performance optimization don't flush the TLB when 512 * clearing the accessed bit, it will eventually be flushed by 513 * a context switch or a VM operation anyway. [ In the rare 514 * event of it not getting flushed for a long time the delay 515 * shouldn't really matter because there's no real memory 516 * pressure for swapout to react to. ] 517 */ 518 return ptep_test_and_clear_young(vma, address, ptep); 519 } 520 521 /* 522 * THP functions 523 */ 524 static inline pmd_t pte_pmd(pte_t pte) 525 { 526 return __pmd(pte_val(pte)); 527 } 528 529 static inline pmd_t pmd_mkhuge(pmd_t pmd) 530 { 531 return pmd; 532 } 533 534 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 535 { 536 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 537 } 538 539 #define __pmd_to_phys(pmd) (pmd_val(pmd) >> _PAGE_PFN_SHIFT << PAGE_SHIFT) 540 541 static inline unsigned long pmd_pfn(pmd_t pmd) 542 { 543 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 544 } 545 546 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 547 { 548 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 549 } 550 551 #define pmd_write pmd_write 552 static inline int pmd_write(pmd_t pmd) 553 { 554 return pte_write(pmd_pte(pmd)); 555 } 556 557 static inline int pmd_dirty(pmd_t pmd) 558 { 559 return pte_dirty(pmd_pte(pmd)); 560 } 561 562 static inline int pmd_young(pmd_t pmd) 563 { 564 return pte_young(pmd_pte(pmd)); 565 } 566 567 static inline pmd_t pmd_mkold(pmd_t pmd) 568 { 569 return pte_pmd(pte_mkold(pmd_pte(pmd))); 570 } 571 572 static inline pmd_t pmd_mkyoung(pmd_t pmd) 573 { 574 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 575 } 576 577 static inline pmd_t pmd_mkwrite(pmd_t pmd) 578 { 579 return pte_pmd(pte_mkwrite(pmd_pte(pmd))); 580 } 581 582 static inline pmd_t pmd_wrprotect(pmd_t pmd) 583 { 584 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 585 } 586 587 static inline pmd_t pmd_mkclean(pmd_t pmd) 588 { 589 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 590 } 591 592 static inline pmd_t pmd_mkdirty(pmd_t pmd) 593 { 594 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 595 } 596 597 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 598 pmd_t *pmdp, pmd_t pmd) 599 { 600 return set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); 601 } 602 603 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 604 pud_t *pudp, pud_t pud) 605 { 606 return set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); 607 } 608 609 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 610 static inline int pmd_trans_huge(pmd_t pmd) 611 { 612 return pmd_leaf(pmd); 613 } 614 615 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 616 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 617 unsigned long address, pmd_t *pmdp, 618 pmd_t entry, int dirty) 619 { 620 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 621 } 622 623 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 624 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 625 unsigned long address, pmd_t *pmdp) 626 { 627 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 628 } 629 630 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 631 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 632 unsigned long address, pmd_t *pmdp) 633 { 634 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 635 } 636 637 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 638 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 639 unsigned long address, pmd_t *pmdp) 640 { 641 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 642 } 643 644 #define pmdp_establish pmdp_establish 645 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 646 unsigned long address, pmd_t *pmdp, pmd_t pmd) 647 { 648 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 649 } 650 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 651 652 /* 653 * Encode and decode a swap entry 654 * 655 * Format of swap PTE: 656 * bit 0: _PAGE_PRESENT (zero) 657 * bit 1 to 3: _PAGE_LEAF (zero) 658 * bit 5: _PAGE_PROT_NONE (zero) 659 * bits 6 to 10: swap type 660 * bits 10 to XLEN-1: swap offset 661 */ 662 #define __SWP_TYPE_SHIFT 6 663 #define __SWP_TYPE_BITS 5 664 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 665 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 666 667 #define MAX_SWAPFILES_CHECK() \ 668 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 669 670 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 671 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 672 #define __swp_entry(type, offset) ((swp_entry_t) \ 673 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 674 675 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 676 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 677 678 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 679 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 680 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 681 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 682 683 /* 684 * In the RV64 Linux scheme, we give the user half of the virtual-address space 685 * and give the kernel the other (upper) half. 686 */ 687 #ifdef CONFIG_64BIT 688 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 689 #else 690 #define KERN_VIRT_START FIXADDR_START 691 #endif 692 693 /* 694 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 695 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 696 * Task size is: 697 * - 0x9fc00000 (~2.5GB) for RV32. 698 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 699 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 700 * 701 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 702 * Instruction Set Manual Volume II: Privileged Architecture" states that 703 * "load and store effective addresses, which are 64bits, must have bits 704 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 705 */ 706 #ifdef CONFIG_64BIT 707 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) 708 #define TASK_SIZE_MIN (PGDIR_SIZE_L3 * PTRS_PER_PGD / 2) 709 #else 710 #define TASK_SIZE FIXADDR_START 711 #define TASK_SIZE_MIN TASK_SIZE 712 #endif 713 714 #else /* CONFIG_MMU */ 715 716 #define PAGE_SHARED __pgprot(0) 717 #define PAGE_KERNEL __pgprot(0) 718 #define swapper_pg_dir NULL 719 #define TASK_SIZE 0xffffffffUL 720 #define VMALLOC_START 0 721 #define VMALLOC_END TASK_SIZE 722 723 #endif /* !CONFIG_MMU */ 724 725 #define kern_addr_valid(addr) (1) /* FIXME */ 726 727 extern char _start[]; 728 extern void *_dtb_early_va; 729 extern uintptr_t _dtb_early_pa; 730 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 731 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 732 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 733 #else 734 #define dtb_early_va _dtb_early_va 735 #define dtb_early_pa _dtb_early_pa 736 #endif /* CONFIG_XIP_KERNEL */ 737 extern u64 satp_mode; 738 extern bool pgtable_l4_enabled; 739 740 void paging_init(void); 741 void misc_mem_init(void); 742 743 /* 744 * ZERO_PAGE is a global shared page that is always zero, 745 * used for zero-mapped memory areas, etc. 746 */ 747 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 748 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 749 750 #endif /* !__ASSEMBLY__ */ 751 752 #endif /* _ASM_RISCV_PGTABLE_H */ 753