1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 SiFive 4 * Copyright (C) 2018 Andes Technology Corporation 5 * 6 */ 7 8 #ifndef _ASM_RISCV_PERF_EVENT_H 9 #define _ASM_RISCV_PERF_EVENT_H 10 11 #include <linux/perf_event.h> 12 #include <linux/ptrace.h> 13 14 #define RISCV_BASE_COUNTERS 2 15 16 /* 17 * The RISCV_MAX_COUNTERS parameter should be specified. 18 */ 19 20 #ifdef CONFIG_RISCV_BASE_PMU 21 #define RISCV_MAX_COUNTERS 2 22 #endif 23 24 #ifndef RISCV_MAX_COUNTERS 25 #error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." 26 #endif 27 28 /* 29 * These are the indexes of bits in counteren register *minus* 1, 30 * except for cycle. It would be coherent if it can directly mapped 31 * to counteren bit definition, but there is a *time* register at 32 * counteren[1]. Per-cpu structure is scarce resource here. 33 * 34 * According to the spec, an implementation can support counter up to 35 * mhpmcounter31, but many high-end processors has at most 6 general 36 * PMCs, we give the definition to MHPMCOUNTER8 here. 37 */ 38 #define RISCV_PMU_CYCLE 0 39 #define RISCV_PMU_INSTRET 1 40 #define RISCV_PMU_MHPMCOUNTER3 2 41 #define RISCV_PMU_MHPMCOUNTER4 3 42 #define RISCV_PMU_MHPMCOUNTER5 4 43 #define RISCV_PMU_MHPMCOUNTER6 5 44 #define RISCV_PMU_MHPMCOUNTER7 6 45 #define RISCV_PMU_MHPMCOUNTER8 7 46 47 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) 48 49 struct cpu_hw_events { 50 /* # currently enabled events*/ 51 int n_events; 52 /* currently enabled events */ 53 struct perf_event *events[RISCV_MAX_COUNTERS]; 54 /* vendor-defined PMU data */ 55 void *platform; 56 }; 57 58 struct riscv_pmu { 59 struct pmu *pmu; 60 61 /* generic hw/cache events table */ 62 const int *hw_events; 63 const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] 64 [PERF_COUNT_HW_CACHE_OP_MAX] 65 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 66 /* method used to map hw/cache events */ 67 int (*map_hw_event)(u64 config); 68 int (*map_cache_event)(u64 config); 69 70 /* max generic hw events in map */ 71 int max_events; 72 /* number total counters, 2(base) + x(general) */ 73 int num_counters; 74 /* the width of the counter */ 75 int counter_width; 76 77 /* vendor-defined PMU features */ 78 void *platform; 79 80 irqreturn_t (*handle_irq)(int irq_num, void *dev); 81 int irq; 82 }; 83 84 #endif /* _ASM_RISCV_PERF_EVENT_H */ 85