1 /* 2 * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h 3 * which was based on arch/arm/include/io.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 * Copyright (C) 2014 Regents of the University of California 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation, version 2. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _ASM_RISCV_IO_H 20 #define _ASM_RISCV_IO_H 21 22 #include <linux/types.h> 23 24 #ifdef CONFIG_MMU 25 26 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size); 27 28 /* 29 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't 30 * change the properties of memory regions. This should be fixed by the 31 * upcoming platform spec. 32 */ 33 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 34 #define ioremap_wc(addr, size) ioremap((addr), (size)) 35 #define ioremap_wt(addr, size) ioremap((addr), (size)) 36 37 extern void iounmap(volatile void __iomem *addr); 38 39 #endif /* CONFIG_MMU */ 40 41 /* Generic IO read/write. These perform native-endian accesses. */ 42 #define __raw_writeb __raw_writeb 43 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 44 { 45 asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); 46 } 47 48 #define __raw_writew __raw_writew 49 static inline void __raw_writew(u16 val, volatile void __iomem *addr) 50 { 51 asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); 52 } 53 54 #define __raw_writel __raw_writel 55 static inline void __raw_writel(u32 val, volatile void __iomem *addr) 56 { 57 asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); 58 } 59 60 #ifdef CONFIG_64BIT 61 #define __raw_writeq __raw_writeq 62 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) 63 { 64 asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); 65 } 66 #endif 67 68 #define __raw_readb __raw_readb 69 static inline u8 __raw_readb(const volatile void __iomem *addr) 70 { 71 u8 val; 72 73 asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); 74 return val; 75 } 76 77 #define __raw_readw __raw_readw 78 static inline u16 __raw_readw(const volatile void __iomem *addr) 79 { 80 u16 val; 81 82 asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); 83 return val; 84 } 85 86 #define __raw_readl __raw_readl 87 static inline u32 __raw_readl(const volatile void __iomem *addr) 88 { 89 u32 val; 90 91 asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); 92 return val; 93 } 94 95 #ifdef CONFIG_64BIT 96 #define __raw_readq __raw_readq 97 static inline u64 __raw_readq(const volatile void __iomem *addr) 98 { 99 u64 val; 100 101 asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); 102 return val; 103 } 104 #endif 105 106 /* 107 * FIXME: I'm flip-flopping on whether or not we should keep this or enforce 108 * the ordering with I/O on spinlocks like PowerPC does. The worry is that 109 * drivers won't get this correct, but I also don't want to introduce a fence 110 * into the lock code that otherwise only uses AMOs (and is essentially defined 111 * by the ISA to be correct). For now I'm leaving this here: "o,w" is 112 * sufficient to ensure that all writes to the device have completed before the 113 * write to the spinlock is allowed to commit. I surmised this from reading 114 * "ACQUIRES VS I/O ACCESSES" in memory-barriers.txt. 115 */ 116 #define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); 117 118 /* 119 * Unordered I/O memory access primitives. These are even more relaxed than 120 * the relaxed versions, as they don't even order accesses between successive 121 * operations to the I/O regions. 122 */ 123 #define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) 124 #define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) 125 #define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) 126 127 #define writeb_cpu(v,c) ((void)__raw_writeb((v),(c))) 128 #define writew_cpu(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) 129 #define writel_cpu(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) 130 131 #ifdef CONFIG_64BIT 132 #define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) 133 #define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) 134 #endif 135 136 /* 137 * Relaxed I/O memory access primitives. These follow the Device memory 138 * ordering rules but do not guarantee any ordering relative to Normal memory 139 * accesses. These are defined to order the indicated access (either a read or 140 * write) with all other I/O memory accesses. Since the platform specification 141 * defines that all I/O regions are strongly ordered on channel 2, no explicit 142 * fences are required to enforce this ordering. 143 */ 144 /* FIXME: These are now the same as asm-generic */ 145 #define __io_rbr() do {} while (0) 146 #define __io_rar() do {} while (0) 147 #define __io_rbw() do {} while (0) 148 #define __io_raw() do {} while (0) 149 150 #define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) 151 #define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) 152 #define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) 153 154 #define writeb_relaxed(v,c) ({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); }) 155 #define writew_relaxed(v,c) ({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); }) 156 #define writel_relaxed(v,c) ({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); }) 157 158 #ifdef CONFIG_64BIT 159 #define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) 160 #define writeq_relaxed(v,c) ({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); }) 161 #endif 162 163 /* 164 * I/O memory access primitives. Reads are ordered relative to any 165 * following Normal memory access. Writes are ordered relative to any prior 166 * Normal memory access. The memory barriers here are necessary as RISC-V 167 * doesn't define any ordering between the memory space and the I/O space. 168 */ 169 #define __io_br() do {} while (0) 170 #define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory"); 171 #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); 172 #define __io_aw() do {} while (0) 173 174 #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(); __v; }) 175 #define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(); __v; }) 176 #define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(); __v; }) 177 178 #define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); }) 179 #define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); }) 180 #define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); }) 181 182 #ifdef CONFIG_64BIT 183 #define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(); __v; }) 184 #define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); }) 185 #endif 186 187 /* 188 * Emulation routines for the port-mapped IO space used by some PCI drivers. 189 * These are defined as being "fully synchronous", but also "not guaranteed to 190 * be fully ordered with respect to other memory and I/O operations". We're 191 * going to be on the safe side here and just make them: 192 * - Fully ordered WRT each other, by bracketing them with two fences. The 193 * outer set contains both I/O so inX is ordered with outX, while the inner just 194 * needs the type of the access (I for inX and O for outX). 195 * - Ordered in the same manner as readX/writeX WRT memory by subsuming their 196 * fences. 197 * - Ordered WRT timer reads, so udelay and friends don't get elided by the 198 * implementation. 199 * Note that there is no way to actually enforce that outX is a non-posted 200 * operation on RISC-V, but hopefully the timer ordering constraint is 201 * sufficient to ensure this works sanely on controllers that support I/O 202 * writes. 203 */ 204 #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); 205 #define __io_par() __asm__ __volatile__ ("fence i,ior" : : : "memory"); 206 #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); 207 #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); 208 209 #define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) 210 #define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) 211 #define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) 212 213 #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) 214 #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) 215 #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) 216 217 #ifdef CONFIG_64BIT 218 #define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; }) 219 #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); }) 220 #endif 221 222 /* 223 * Accesses from a single hart to a single I/O address must be ordered. This 224 * allows us to use the raw read macros, but we still need to fence before and 225 * after the block to ensure ordering WRT other macros. These are defined to 226 * perform host-endian accesses so we use __raw instead of __cpu. 227 */ 228 #define __io_reads_ins(port, ctype, len, bfence, afence) \ 229 static inline void __ ## port ## len(const volatile void __iomem *addr, \ 230 void *buffer, \ 231 unsigned int count) \ 232 { \ 233 bfence; \ 234 if (count) { \ 235 ctype *buf = buffer; \ 236 \ 237 do { \ 238 ctype x = __raw_read ## len(addr); \ 239 *buf++ = x; \ 240 } while (--count); \ 241 } \ 242 afence; \ 243 } 244 245 #define __io_writes_outs(port, ctype, len, bfence, afence) \ 246 static inline void __ ## port ## len(volatile void __iomem *addr, \ 247 const void *buffer, \ 248 unsigned int count) \ 249 { \ 250 bfence; \ 251 if (count) { \ 252 const ctype *buf = buffer; \ 253 \ 254 do { \ 255 __raw_write ## len(*buf++, addr); \ 256 } while (--count); \ 257 } \ 258 afence; \ 259 } 260 261 __io_reads_ins(reads, u8, b, __io_br(), __io_ar()) 262 __io_reads_ins(reads, u16, w, __io_br(), __io_ar()) 263 __io_reads_ins(reads, u32, l, __io_br(), __io_ar()) 264 #define readsb(addr, buffer, count) __readsb(addr, buffer, count) 265 #define readsw(addr, buffer, count) __readsw(addr, buffer, count) 266 #define readsl(addr, buffer, count) __readsl(addr, buffer, count) 267 268 __io_reads_ins(ins, u8, b, __io_pbr(), __io_par()) 269 __io_reads_ins(ins, u16, w, __io_pbr(), __io_par()) 270 __io_reads_ins(ins, u32, l, __io_pbr(), __io_par()) 271 #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count) 272 #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count) 273 #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count) 274 275 __io_writes_outs(writes, u8, b, __io_bw(), __io_aw()) 276 __io_writes_outs(writes, u16, w, __io_bw(), __io_aw()) 277 __io_writes_outs(writes, u32, l, __io_bw(), __io_aw()) 278 #define writesb(addr, buffer, count) __writesb(addr, buffer, count) 279 #define writesw(addr, buffer, count) __writesw(addr, buffer, count) 280 #define writesl(addr, buffer, count) __writesl(addr, buffer, count) 281 282 __io_writes_outs(outs, u8, b, __io_pbw(), __io_paw()) 283 __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw()) 284 __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw()) 285 #define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count) 286 #define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count) 287 #define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count) 288 289 #ifdef CONFIG_64BIT 290 __io_reads_ins(reads, u64, q, __io_br(), __io_ar()) 291 #define readsq(addr, buffer, count) __readsq(addr, buffer, count) 292 293 __io_reads_ins(ins, u64, q, __io_pbr(), __io_par()) 294 #define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count) 295 296 __io_writes_outs(writes, u64, q, __io_bw(), __io_aw()) 297 #define writesq(addr, buffer, count) __writesq(addr, buffer, count) 298 299 __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) 300 #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count) 301 #endif 302 303 #include <asm-generic/io.h> 304 305 #endif /* _ASM_RISCV_IO_H */ 306